A Universal, Low-Delay, SEC-DEC-TAEC Code for State Register Protection

Finite State Machine (FSM) is widely used in electronic systems and its reliability is critical to the system. Ionizing radiation induced soft error is one of the major concerns in the design of electronic systems, especially in avionics or space applications. Nowadays, the majority of electronic systems relies on single-error correction, double-error detection (SEC-DED) codes to mitigate soft errors. However, the presence of multiple bit upsets is becoming more prevalent as CMOS technology scales down. In addition, state registers in FSMs usually have variable bit-widths and have strict requirement on encoding and decoding delay, which poses challenges for error mitigation techniques. This paper presents an Error Detection and Correction (EDAC) code for state register protection, which can achieve single-error correction, double-error correction and triple-adjacent-error correction (SEC-DEC-TAEC) ability. The proposed code can be used to protect data with 4n bit-width (n = 2,3,4,...) using one common encoder and decoder code block and introduces minimal delay. Experiment results show that the proposed code has better error correction ability than most existing MCU correction codes. Besides, it reduces area occupation by 30% and delay by 15% compared with Orthogonal Latin Square (OLS) code in the case of 8 bit-width data.


I. INTRODUCTION
In the design of electronic systems, reliability is one of the major concerns. One reliability issue is the ionizing radiation induced soft errors, which is common in avionics or space applications. These errors can cause single event upset, which could be harmful to the functionality of the electronic systems. Error detection and correction (EDAC) codes have been traditionally used to protect electronic systems from single event upset problems. Single-error correction, double-error detection (SEC-DED) codes are one of the most commonly used EDAC schemes [1]- [4]. These codes have few redundant check bits, simple logic, and fast encoding and decoding speed. However, as CMOS technology scales down, the number of transistors per unit area increases and the operation voltage of transistors decreases. Therefore, a single highenergy radiating particle or ionizing radiation will cause multiple errors, resulting in multiple cells unpsets (MCU) [5]- [9]. The traditional SEC-DED codes cannot correct this kind of error. Therefore, methods to detect and correct multiple errors are needed to protect electronic systems from data corruption.
With the development of programmable ASIC technology, the implementation of electronic systems using programmable ASICs is becoming prevalent. The application of programmable ASICs greatly reduces the development cost and cycle of electronic systems. In an electronic system using programmable ASICs, finite state machines (FSMs) are the brain of the system and are utilized to generate control signals and schedule other function units. State registers in FSMs are responsible for storing the current state. The protection of state registers is of great importance to the reliability of the system. However, the characteristics of state registers pose challenges to the design of error correction schemes. First, state registers usually have variable bit-width, which is determined by the number of states that need to be represented. Second, to ensure the correctness of the FSM operation, the encoding and decoding process should typically be completed within one clock cycle. Therefore, an error correction scheme that supports variable bit-widths and low delay is urgent.
In this paper, we propose an EDAC code based on Hsiao code and parity check code to protect state registers from data corruption. The proposed code has the following features: 1) It achieves single-error correction, double-error correction and triple-adjacent-error correction (SEC-DEC-TAEC) ability. 2) It can support variable bit-widths using one common encoder and decoder code block. Specifically, it can protect data with bit-width of 4n (n = 2, 3, 4, ...).
3) It has minimal encoding and decoding delay, which is appealing to state register protection. 4) It can correct errors in both data bits and check bits.
Extensive experiments are conducted to verify the effectiveness of the proposed code. The results show that the error correction ability of the proposed code is greatly improved compared with most existing MCU correction codes. In the case of 8-bit data (which is the commonly used instruction length), compared with OLS code, the hardware area occupied by the proposed code is reduced by 30% and the calculation delay is reduced by 15%. In addition, compared with the commonly used triple-mode redundancy technology in satellite communication systems, the proposed scheme has more obvious advantages in area, delay and reliability.
The rest of this paper is organized as follows. In Section II, the existing proposals for MCU correction are reviewed. Besides, a brief introduction to Hsiao code and parity check code is presented. In Section III, the design of the proposed SEC-DEC-TAEC code is elaborated and its error correction ability is analysed. In Section IV, the proposed code is evaluated in terms of error correction ability and implementation cost, including delay, power consumption and area occupation. Comparation with existing codes are conducted. Finally, the conclusion is drawn and further work is outlined in Section V.

II. RELATED WORK
In this section, we first present related work on MCU correction schemes. Then, we give a brief introduction to parity check code and Hsiao code, based on which the proposed code is designed.

A. MCU CORRECTION SCHEMES
There are many proposals in the literature to solve the MCU problem in order to detect and correct multiple bit errors. These proposals can be divided into three categories. The first category aims to complete encoding and decoding without adding additional check bits [10]- [12], but the generation time of the check matrix is long. For example, it takes nearly a week to generate the check matrix in [11]. The second category stores data in the form of a two-dimensional matrix, called matrix code [13]- [18], and adds error correction codes to the data in row and column to achieve correction of the bit flip situation. To improve the encoding and decoding efficiency, the One-Step Majority of Logic Decoding (OS-MLD) technique is proposed, including Euclidean Geometry codes (EG) [19], Difference Set codes (DS) [20] and Orthogonal Latin Square codes (OLS) [21], among others. However, these methods can only support specific application scenarios. For example, OLS codes can only be applied to codewords with length of m 2 (m is a positive integer). Besides, for different bit-widths, the size of the corresponding check matrix is different. Therefore, if the data to be protected has various bit-widths in an electronic system, multiple encoder and decoder code blocks are needed, complicating the overall system. At present, researchers are working on applying OLS to 32-bit codeword [22] and reducing check bits [23], [24]. The last category is triple-mode redundancy, which is commonly used in satellite communications. There has been a lot of research on FPGA-based implementation of triple-mode redundancy [25]- [27].
For protecting data in registers where low delay is required, some codes have been proposed [28]- [30]. In addition, more complex and precise error correction codes [31]- [40] are used in electronic systems for critical applications.

B. PARITY CHECK CODE
Parity check code is the colletive term of odd parity check code and even parity check code, which is one of the most basic error detection codes. By adding a redundant bit, the codeword is ensured to have an odd or even number of 1s. The limitation of parity check code is that it can only detect odd number of errors, but because of its simplicity, parity check code is still widely used for error control in data transmission.

C. HSIAO CODE
Hsiao code is a kind of SEC-DED code with odd weight column. For data bits of the same length, the number of check bits of Hsiao code and Extended Hamming code are the same, but Hsiao code has better performance [2]. Hsiao code reconstructs the check matrix to ensure that the number of 1s in each column is odd, and the number of 1s in each row is equal or as equal as possible (the difference does not exceed one). To minimize the number of 1s in the check matrix, the check matrix of Hsiao code must meet the following conditions: 1) Each column in the check matrix contains an odd number of 1s. 2) The total number of 1s is minimum.
3) The number of 1s in each row is equal as much as possible and the maximum difference is one. 4) There is no column with all 0s. 5) There are no two identical columns.
The first condition ensures that the code spacing is 4. The second and third conditions enable Hasio codes to have a high coding efficiency which reduces overhead. They also enable Hasio codes to have uniform timing, which outperforms extended Hamming codes. The fifth condition ensures that the code spacing is at least 3, and that each corrector is different because the columns in the check matrix represent standard correctors for error correction.

III. THE PROPOSED EDAC CODE
In this section, the design of the proposed EDAC code is elaborated. The encoding process and decoding process are described and the error correction ability is analysed. Fig. 1 depicts the block diagram of the encoder. The encoding process consists of three steps. First, the original word is divided into half-byte segments which are then arranged by row. Then, check bits are generated, which consist of two parts. For each segment, row check bits are computed using Hsiao code; for each column of the segments, a column check bit is generated by the parity check code. Finally, the data and check bits are interleaved to generate the final codeword.

B. THE ENCODING PROCESS
We now elaborate the first two steps of the encoding process, as shown in Algorithm 1. An 8-bit word is used as an example to illustrate the procedure. Firstly, the original word is divided into m half-byte segments. For example, the 8bit word can be divided as shown in Fig. 3 (a). The halfbyte segments are arranged by row to form the data matrix, denoted by D. Then, for each row of D, the row codeword is computed by multiplying the data bit vector and generator matrix as follows.
where cw m is the mth row codeword, d m represents the data bit vector of the mth segment and G = I 4 B T is the generator matrix. To reduce the complexity of calculation, B must meet the following restrictions: 1) every column in B contains an odd number of 1s; 2) the number of 1s in B is minimised; 3) the number of 1s in every row is as equal as possible and the difference is no larger than one; 4) there is no column with all 0s; 5) every column is distinct. We use the following generator matrix which meets the restrictions.
After calculation, all the row codewords are arranged by row to form the row codeword matrix, denoted by C, as shown in Fig. 3(b). Then, all bits in each column of D are XORed to generate a column check bit. All the column check bits form the column codeword vector, denoted by O, as shown in the last row of Fig. 3 (c).

C. THE DECODING PROCESS
Suppose that the codeword has been deinterleaved and the row codeword matrix C and the column codeword vector O are obtained. The syndrome matrix J of C is calculated using parity check matrix H. The mth row of J is: b) One error happens in O and the other error happens in C. Then, the error in C can be corrected, as in the case 2)b). c) Both errors happens in C but are in different rows.
Then there are two rows in J , say J m and J n , which are equal to column p and column r in H, respectively. This tells us that the bit in the mth row and pth column as well as the bit in the nth row and rth column of C are wrong. Therefore, the correct codeword can be generated by flipping the pth bit of cw m and the rth bit of cw n . d) Both errors happens in the same row of C. Suppose it is row m. Then J m is equal to the result of XOR of two different columns in H. This tells us that two errors happens in c m . Then, O can be used to correct these two errors because they happen in different columns of C, thereby ensuring that each column contains at most one error. Specifically, to get the correct data, the first four bits of cw m is XORed with O. Note that we do not care about error(s) in the last four bits of cw m , which are the check bits. Based on the above analysis, it can be seen that the proposed scheme can ensure the correct recovery of data when its storage content encounters a single or double random errors. Hardware implementation of the decoder for 8-bit data is illustrated in Fig. 4.

D. INTERLEAVING FOR TAEC ABILITY
As discussed above, with the first two encoding steps, the proposed scheme can ensure the correct recovery of data when it encounters single error bit or two error bits. We now further examine the decoding process to see if it is possible to correct triple bit errors. Consider the following conditions: Based on above analysis, we can see that if the three error bits fulfill some certain patterns, then they can be detected and corrected. Therefore, triple adjacency error correction ability can be achieved without adding additional check bits using interleaving technique. That is, if we can ensure that any triple adjacency error that happens after interleaving fulfills one of the above conditions after deinterleaving, then the triple adjacency error can be corrected. To achieve triple adjacency error correction, the data bits and check bits are interleaved according to the following rules.
1) Any triple adjacent bits cannot be composed of data bits and check bits in the same row of C. 2) Any triple adjacent bits cannot be composed of one column check bit (denoted by O i ), one data bit in the same column with O i (denoted by D i ), and another bit in the same row with D i . To fulfill the above rules, we propose the following interleaving scheme. Define I as the interleaving matrix, where the data and check bits are put into. I is a k by 4 matrix, where k = 2 × m + 1. Two cases are seperately considered, where m is even and odd, respectively.

1) m is even
Put O into the (m + 1)th column of I. For each row i with odd number (i.e., i = 1, 3, . . . ) in C, put the first four bits (data bits) into the ith of column I, put the last four bits (check bits) into the (m + 1 + i)th column of I. For each row j with even number (i.e., j = 2, 4, . . . ) in C, put the first four bits (data bits) into the (m + 1 + j)th column of I, put the last four bits (check bits) into the jth column of I. The interleaving process for a 16-bit data word is illustrated in Fig. 5.

2) m is odd
Put O into the (m + 2)th column of I. For each row i with odd number (i.e., i = 1, 3, . . . ) expect the mth row in C, put data word is illustrated in Fig. 6. After generating I, the rows of I are concatenated to form the final codeword. The deinterleaving process in the decoding phase is a reverse process of the interleaving process. With interleaving, the proposed code achieves SEC-DEC-TAEC ability.

IV. PERFORMANCE EVALUATION
In this section, we evaluate the error correction ability and implementation cost of the proposed code. The encoder and decoder are implemented in HDL according to given G and H. It should be noted that in actual chips, both data bits and check bits will have problems such as single particle flipping. Therefore, in the evaluation of the code's error correction ability, we treat the check bits and the data bits equally.

A. ERROR CORRECTION ABILITY
The first part of the evaluation focuses on evaluating the error correction ability of the proposed code. The circuit under test (CUT) is an FSM controlled waterfall light circuit implemented using Verilog, the code of which has been uploaded to Github [41]. To simulate the SEU and MBU failures occurring in the circuit, the bit flip is chosen as the basic fault injection model. Therefore, the FPGA platform is used to evaluate the code correction ability by flipping the bit/bits of specified register in the CUT. To better simulate different error scenarios, all registers in the CUT are replaced by the structure as shown in Fig. 7, where the EIE signal is the enable of bit fault injection. When the EIE signal is deactivated, the register is in normal operation since the normal signal is directly selected to the input of the register. On the contrary, when the EIE signal is activated, the reverse of the normal signal value will be selected to the input of the register and the single bit fault will be injected to the circuit.
According to the run state of the CUT, the result of error injection can be divided into three categories as follows. The new structure of register. The input of the register is the output of a multiplexer whose inputs are normal input and the xor result of normal input and "1". In addition, the select signal of the multiplexer is error inject enable (EIE), which controls whether the register is injected with fault.
• Silent State. For a given runtime, the output of the CUT and all register state in the CUT are normal. • Latent State. For a given runtime, the output of the CUT is normal, but the state of some registers in the CUT is different from that when the error is not injected. In this state, although the injected error has no effect on the circuit function, it may result in a functional error in the subsequent operation. • Failure State. For a given runtime, the output of the CUT is different from that when the error is not injected.
In this paper, to maximize the proper operation of the circuit, the error correction code is considered valid only when the circuit is in the silent state under error injection. The LFSR is used to generation all possible combinations of bit flip in the specified register according the injected error type such as single error, double error, double-adjacent error and so on. For example, for the case where the original data is 4-bit and the injected error type is double error, there will be 6 different combinations of two flip bits. We can generate the LFSR circuit as shown in Fig. 8. If the initial state of LSFR is "1000", the state sequence of it is 1000 → 1100 → 1110 → 0111 → 0011 → 0001 → 1000. Thus, all possible combinations of flip bits can be generated according to the different output states of the LFSR circuit. As our goal in this section is to measure the correction coverage, we have not injected errors according the error occurrence probability. We have injected single error, double errors, double-adjacent errors, triple errors and triple-adjacent errors in all bits of the data by the corresponding LFSR circuit. For each error type, 1,000,000 errors are injected. The

Error types
Code in [14] Code in [16] Code in [33] Code in [34] Code in [35]  The code proposed in this paper is compared with the codes proposed in [14], [16], [33], [34] and [35]. The results are shown in Table 1. Reference [14] combines Hamming codes and parity codes to achieve single-bit error correction, but cannot achieve 100% correction for double-bit errors. The codes in [16], [33], [34] and [35] can correct single error, double-adjacent errors, triple-adjacent errors, but cannot correct 100% of double-bit random errors. The decoding accuracy of the proposed code is 100% in the case of single, double and triple adjacent error(s) and 50.93% in the case of random triple errors. This demonstrates the superior error correction ability of the proposed code.

B. IMPLEMENTATION COST
In electronic systems, especially in space electronic systems, minimization of the implementation cost in terms of area, power, and delay is very important. This part of the evaluation focuses on evaluating the cost of the encoder and decoder of the error correction code. The length of state registers in electronic systems is generally 8-bit. Therefore, we focus on the case where the original data bit is 8. It has to remarked that the codes in [14], [16], [33], [34] and [35] do not support data with bit width of 8. Meanwhile, the Hamming code [1] and OLS code [23] support 8-bit data and have relatively simple encoder and decoder circuit. Therefore, the proposed code is compared with the Hamming code [1] and the OLS code [23] in this section. To estimate the cost, we have implemented the encoder and decoder circuit for the three codes in Verilog, and used the Synopsis Design Compiler (DC) configured to minimize the circuit area with the SMIC 180 nm library.
The results are summarized in Table 2. It can be seen that although the proposed code has larger power, area and delay compared with the Hamming code, it has much stronger error correction ability. In addition, compared with OLS code, the proposed code has better performance in power, area and delay. Specifically, the area occupation is reduced by 30% and delay is reduced by 15%.

C. THE IMPACT OF BIT-WIDTHS
The third part of the evaluation focuses on the impact of different bit-widths on the area, power and delay for the proposed code. To make the evaluation more representative, the most commonly used data bit widths in FPGA/ASIC are selected, including 8, 12, 16, 20, 32 and 64 bits. The encoder and decoder are mapped to the SMIC 180 nm device library with DC. The results are summarized in Table 3. It can be seen that as the bit-width to be protected increases, the power and area of the proposed code increase to a large extent, but the increase in delay is small, which demonstrates the lowdelay property of the code. In order to further evaluate the proposed code in actual environment, the encoder and decoder are mapped to the SMIC 180 nm device library with the Synopsys IC Compiler software (ICC). The results are summarized in Table 4. It can be seen that the delay increase is minimal. In addition, we compare the proposed code with the triple-mode redundancy (TMR) scheme in a practical project, and the results show that the occupied area using the proposed scheme is 43.5% of the TMR scheme.

V. CONCLUSION
In this paper, we present an EDAC code to achieve low-delay SEC-DEC-TAEC ability for state register protection. The proposed code is based on Hsiao code and parity check bit to achieve SEC-DEC, while the introduction of interleaving VOLUME 4, 2016 further provides TAEC ability. Besides, variable data bit widths are supported by the code. Compared with existing coding schemes, the proposed code has more advantages for state register protection with its low-delay property and enhanced error correction ability. In the future, we will focus on how to further reduce the check bits of the proposed code.