Doubly Fed Induction Generator Low Voltage Ride Through Improvement Through Modular Multilevel Converter

This paper proposes a novel fault current suppression method for doubly fed induction generator (DFIG) low voltage ride through (LVRT) improvement employing modular multilevel converter (MMC). It is based on the inherent MMC arm impedance and the number of levels to provide transient damping of DFIG rotor and stator currents under severe grid faults, contributing effectively to maintaining the DFIG connection while ensuring controllability by avoiding the protection activation. Neither additional hardware nor control loops are necessary. DFIG dynamic equations under LVRT, including the contribution of the MMC, are presented, and a model is derived for control design. Performance assessment, including symmetrical and asymmetrical fault scenarios for MMC with 3, 21, 51, and 101 levels and comparison with existing and proposed controllers, highlighted that arm impedance and increased MMC level number contributed to DFIG stator and rotor fault current suppression, providing DFIG LVRT improvement under severe grid fault conditions.


BESS
Equivalent arm impedance.

I. INTRODUCTION
O Ne of the main characteristics of DFIG-based WECS is their high sensitivity to electrical disturbances, particularly voltage sags, due to the direct connection of their stator to the grid [1]. In WECS, power electronics have a crucial role in generation compatibility with the grid, and traditionally the back-to-back VSC sharing a DC bus has been used [2]. However, to meet LVRT requirements, this converter topology requires control or hardware protection implementations to ensure that the DFIG-based WECS remains connected to the grid without damaging the system [3]. Device-based solutions have been used for improving DFIG LVRT supportability, such as crowbar, DC choppers, fault current limiters (FCLs), synchronous static compensators (STATCOMs), dynamic voltage restorers (DVRs), and BESS [4]- [10].
The crowbar, one of the widely used techniques for LVRT support, uses short-circuited shunt resistors in the rotor [1]. The common drawback of the crowbar refers to their temporary uncontrollability of the active and reactive power in DFIG, RSC disconnection, and rotor short-circuit [11]. An alternative to overcome these drawbacks is the coordinated use of a crowbar with a SBR [12], and a parallel RL crowbar with an RL series circuit [13]. Nevertheless, these approaches have the disadvantage of adding even more devices with low effectiveness to maintaining DFIG control. The DC chopper, another well-known DFIG solution in the literature against DC bus overvoltages, uses a shunt resistor to dissipate the energy excess [14]. However, the time to reestablish the control and connect the converter to operation is drastically increased compared to the crowbar [15].
One challenge to the DFIG is to operate under voltage sags and overcurrent in the stator and rotor during a fault. Thus, the use of FCL devices is a strategy that acts to limit the high currents under the fault and protect the DFIG converters placed at different points of the DFIG-based WECS structure, such as the stator, rotor, DC link, and CCP [7], [16]. [17] proposed a BTFCL. This scheme comprises coupling transformers connected to the DFIG stator, a diode bridge, and an FCLI. The FCLI is inserted in the stator terminals when the stator currents reach the threshold to limit the fault current. However, the FCLI causes voltage surges due to the RSC switching, leading to voltage distortions and electromagnetic torque oscillations.
Techniques based on BESS can also support DFIG LVRT [9]. The BESS comprises a converter denominated ESC, operating parallel coordinated with the RSC, to support the rotor in demagnetizing and injecting reactive current, as presented in [18]. Nevertheless, this approach requires an additional converter, and the batteries considerably increase the costs and control complexity. Another approach used to mitigate voltage sag in the DFIG stator terminals and improve LVRT supportability is a SGSC across the DC bus, as presented in [19]. This system is composed of a parallel grid side rectifier connected to DC bus terminals through a transformer. This structure provided an accurate control of the stator flux under normal and LVRT conditions. However, this method requires an additional converter with complex control coordination.
In [20], the STATCOM is employed to inject and control the reactive power based on the fault condition, but it has limitations to ensure system stability, requiring additional control loops to regulate the reactive power. The DVR is usually employed to provide LVRT grid voltage recovery, connected through a transformer between the CCP and DFIG, as presented in [21]. Nevertheless, this method requires an extensive energy storage system and an additional converter with control loops to regulate the series voltage compensation under LVRT conditions. On the other hand, [22] employed a MERS for DFIG LVRT capacity improvement, composed of four switches and a capacitor connected to the CCP. This scheme controls the grid injected voltage by the capacitor. However, it can suffer from harmonics in the line current that can be interacting with the system resonance frequency.
An alternative to overcome these drawbacks and avoid hardware-based approaches is the use of multilevel converters for DFIG-based WECS LVRT improvement. Assuredly, multilevel power converters have recently improved robustness to electrical disturbances, lower THD, and fault tolerance [23]. In particular, the half-bridge MMC has reached broad relevance due to its flexible modular structure, easy expandability, and capacity to operate at high power levels, such as HVDC systems, photovoltaic, and WECS [24]. Unlike other submodule topologies, the half-bridge MMC allows the current to flow in any operating mode through the freewheeling diodes of the submodule switches. This capability provides continuous operation even under fault conditions, ensuring controllability and damping fault currents, making it attractive for LVRT support applications [25]. In addition, the half-bridge MMC has been widely used due to the smaller submodule components and the cost of increasing the number of levels [26]. Nevertheless, with the best authors' knowledge, MMC has not been used in DFIG-based WECS LVRT due to the newfound MMC employment in variable-speed drives and its drawback of submodule capacitor voltage ripples under low-frequency operation. However, approaches such as [27] and [28] have already demonstrated that it is possible to allow MMC operation under low frequencies by employing additional control loops to provide reliable operation.
Overcoming these problems, this paper proposes a fault current suppression method by leveraging the MMC arm impedance and increasing the number of levels. It is crucial to ensure that the DFIG stator and rotor currents remain under controllable and safe levels to avoid loss of controllability and disconnection under grid fault scenarios. In addition, maintaining the controllability and connection of DFIG-based WECS is a requirement for operating wind farms to support the network [29]. Thus, this paper proposal deals with DFIG stator and rotor fault current limiting for symmetrical and asymmetrical faults by including the MMC arm impedance in cascade to the rotor and increasing the number of levels of the MMC to strengthen the inductive nature of this arm impedance. Therefore, it is expected that the proposed fault current suppression method enhances robustness and reliability and supports the reduction of DFIGbased WECS physical protection tripping. The proposed fault current suppression method is based on the half-bridge MMC to ensure DFIG controllability and continuous operation even under LVRT conditions. In this fashion, this work demonstrates through simulations the applicability of MMC with a higher number of levels, indicating the feasibility of its use in DFIG-based WECS. Unlike the approaches described in [11]- [14], [17]- [22] this proposal does not employ devicebased solutions since a back-to-back MMC topology is used instead of the traditional two-level converters (2LVSC's) with fault current suppression capability due to the arm impedance and the increased number of levels. In addition, this paper proposal provides an adjustment to the classical vector control approach described in [1] to consider the MMC-DFIG dynamics. Therefore, the proposed DFIG fault current suppression method provides the DFIG-based WECS LVRT enhanced supportability to severe grid voltage sags; neither additional hardware nor control loops are necessary.
The performance assessment of the proposed method has been accomplished with various symmetrical and asymmetrical faults. Furthermore, the MMC with 3, 21, 51, and 101 levels have been evaluated to demonstrate the DFIG-based WECS performance under several operating conditions. Simulated results have demonstrated the MMC capacity to ensure the DFIG LVRT improvement in all fault scenarios, indicating that the higher is the number of levels and the arm impedance, the lowest is the DFIG stator and rotor overcurrents. Fig. 1 depicts the three-phase MMC with half-bridge submodules, which is the most widely used topology configuration. In this case, the MMC is composed of 2(N -1) submodules, where N is the number of converter levels; each submodule is composed of two switches and a capacitor [26]. A series R-L (R arm and L arm ) impedance comprises the MMC arm, equally distributed among the converter phases. According to the state of the MMC submodule switches, the capacitor is inserted or bypassed. The voltage of each submodule V SM that synthesizes the output voltage levels is defined by a switching function as follows:

II. MODULAR MULTILEVEL CONVERTER DESCRIPTION
The average capacitor voltage, V cap , of each submodule, is given by: where N sm is the number of submodules per arm. Then, N sm + 1 is the number of output voltage levels; V bus is the DC bus voltage. Each arm in the MMC is equivalent to a controlled voltage source V arm with instantaneous voltage amplitude, given by: where SM active is the number of active submodules.The MMC voltage level is given as a function of the sum of the submodule voltages, V sm , and the voltage drop across R arm and L arm , as follows:  basic L-C voltage-current relation, and C sminst as the total active submodule instantaneous capacitance, (3) is rewritten as: where dt are state variables, which cannot vary instantaneously [3]. These characteristics indicate that the MMC circuit opposes to sudden current and voltage variations, avoiding instantaneous overcurrents and overvoltages.
The MMC has been considered the next generation of converters that will integrate the various power system applications. Then, wind energy conversion systems can be certainly benefited from the MMC due to their transformless structures, high efficiency, and modularity [28]. However, under low-frequency operation (<30 Hz), the MMC submodules present a current through the capacitors with high oscillation, leading to significant ripples in the capacitor voltages [27], [30]. This is a high limitation for the use of MMCs in DFIG-based WECS. Nevertheless, several works have been providing solutions for improving the MMC dynamic performance during challenging low-frequency operations. In [31], a common-mode voltage injection technique is proposed to reduce capacitor voltage oscillations. [28] proposes a capacitance selection algorithm for the MMC to keep the oscillations within acceptable limits. [27] proposes an improved circulating current injection scheme based on the trapezoidal waveform. Then, [27], [28], [31] successfully demonstrated that the operation of MMC submodule capacitors is feasible under extra low frequencies (<5 Hz) by minimizing the effects of voltage oscillations.
The fundamentals that govern the relationship between the MMC submodule capacitor voltage ripple and the output frequency are addressed in [27]. This analysis demonstrates the inverse relationship between the voltage ripple in submodule capacitors and the MMC operating frequency, i.e., the lower the output frequency, the higher the voltage ripple. [27] approximates the MMC upper and lower arm energy, w upA and w lowA , by: where ω is the output angular frequency, and P o is the converter output power, given by [27]: where V bus and I o are the DC bus voltage and the magnitude of the output current, respectively. Based on (5)-(6), the peakto-peak arm energy variation, ∆w upA = ∆w lowA = 2Po ω , should be damped by the N capacitors of the submodules. Therefore, writing the energy deviation in terms of N and the submodule capacitor energy, , one obtains [27]: where V cap,max = V cap + 1 2 ∆V cap,pp and V cap,min = V cap − 1 2 ∆V cap,pp are voltage deviations. Therefore, considering ∆V cap,pp to be the peak-to-peak voltage ripple of the submodule capacitor, C sm the submodule capacitance, and N V cap = V bus the total DC bus voltage, (8) can be simplified as follows [27]: which demonstrates that the voltage ripple is inversely proportional to the output frequency. Hence, rewriting (9) as a function of N , yields [27]: In (10), the product N V cap gives the total DC bus voltage. However, the increase in the number of levels provides the individual submodule capacitor voltage reduction to maintain the equality, i.e., N V cap = V bus . Therefore, each capacitor per submodule will be subjected to lower voltages, i.e., V cap decreases as N increases, which effectively impacts the MMC arm voltage oscillations improvement and reduces the total converter voltage ripple. Based on [27], the voltage ripple depends on the number of levels, i.e., with the highest number of levels, one can relieve the MMC submodule capacitor voltage ripples. Therefore, considering the challenging MMC operation conditions covered in [27], which was not in a DFIG application, this paper demonstrates the possibility to use a MMC in a DFIG with properly adaptations. For instance, Figs. 2 and 3 depict the back-toback MMC operation in a DFIG-based WECS under lowfrequency and low-voltage conditions.
To better describe the back-to-back MMC operation condition in a DFIG-based WECS (according to Table 2 parameters) under low-frequency and low-voltage, the wind speed VOLUME x, 2022 was set as the generator's synchronous speed (1500 rpm) in Fig. 2. In this condition, the DFIG operates with slip equal to zero, the rotor currents operate at nearly zero frequency, and the rotor voltages operate at near-zero voltages [1]. The wind speed for this condition can be determined through the curve of turbine speed in (m/s) as a function of generator speed (rpm) according to [1]. In addition, the generator uses a gearbox to perform speed regulation between the high-speed and low-speed shaft, making the high-speed shaft rotate about 50 times faster than the low-speed shaft. Thus, the high-speed shaft rotates at approximately 1500 rpm and drives the DFIG [3]. Hence, the rotor currents behave practically as DC currents (i.e., the worst situation). Therefore, the simulations in Fig. 2 considered 3L-and 101L-MMC RSC operating at the synchronous speed to demonstrate the submodule capacitor voltages under these challenging conditions. As expected, the MMC submodule capacitor voltages present oscillations, which were more significant for the RSC 3L-MMC. In this sense, the voltage distributed in the submodule capacitors is higher because there are fewer submodules in the MMC arm. Conversely, through the RSC 101L-MMC, a lower capacitor submodule voltage ripple is provided, indicating that many MMC levels can relieve the RSC voltage ripples. The voltage distribution across the MMC arm's submodule capacitors is lower due to the larger amount of submodules, which provides ripple reduction since the capacitors require less voltage amplitude during charge and discharge cycles to be equalized.
To highlight the lower voltage ripple in the MMC submodule capacitors under higher frequencies the DFIG-based WECS operating at subsynchronous speed was simulated as depicted in Fig. 3. In this condition, the DFIG operates with maximum slip, i.e., approximately 0.3. Thus the magnitude of the rotor voltages is larger, around 350 V, since they are proportional to the slip [1]. On the other hand, the rotor current frequencies operate at the slip frequency of approximately 15 Hz. This scenario describes the reduction of ∆V cap,pp as ω increases, which provides the MMC behavior according to (10). As expected, an increase in the converter output frequency decreased the capacitors' charge and discharge periods leading to a significant reduction in voltage ripples. In addition, the 3L-MMC presents higher capacitor voltage distortion and oscillation due to the lower amount of synthesized voltage levels and the capacitors being subjected to higher voltage levels. Conversely, the 101L-MMC presented the best performance due to the improved voltage distribution in the MMC submodules providing the capacitor voltage level reduction and relieving the distortions and ripples. Thus, the RSC operation was further validated through the proposed control scheme, since despite the capacitor's ripples in this particular operation condition, no voltage deviations occurred in the converter, allowing it to be reasonably used to obtain the results. In addition, based on these preliminary simulation results, there is evidence that the MMC employment in DFIG-based WECS with an increased number of levels can be adopted as an RSC while ensuring no impacts during its operation. Therefore, unlike the previous approaches under low-frequency and low-voltage operation, this paper employs the proposed control structure, addressed in the next section, to validate the DFIG-based WECS fault current suppression method.

III. THE PROPOSED MMC CONTRIBUTION FOR DFIG ROTOR CURRENT DAMPING UNDER FAULT CONDITIONS
The dynamic equations in [3] can represent the interaction between the MMC arm impedance with the DFIG rotor circuit. Fig. 4 depicts the DFIG rotor equivalent circuit with MMC, per phase average circuit, for developing dynamic equations [32], where ⃗ V r r0 is the electromotive force (EMF) induced by the stator flux λ s , σ = 1 − L 2 m LsLr , L r and R r are the rotor inductance and resistance, respectively. In the MMC diagram, i DC is the DC current, and DFIG per-phase circuit seen from the rotor terminals considering one phase of the MMC. Therefore, from Fig. 4, the equations that govern the interaction with the MMC arm impedance and the number of level increase are divided into two parts: firstly, consider the submodule capacitances association due to the switching to obtain the equivalent impedance. Thus, the equivalent arm capacitance C eq is given by: where gate sm is the submodule switching signals provided by the PWM technique. With the increasing number of MMC levels, the arm capacitive effect decreases as the amount of active submodules increases. Considering that the submodule capacitors are equalized and N is large enough, i.e., lim N →∞ N , the equivalent arm capacitance is given by: which makes the MMC arm closer to an R-L impedance. Thus, considering the resistance of the active and bypassed submodules as R sm,on and R sm,of f , respectively, the equiv-alent arm impedance is given by the sum of arm impedance and the series resistance of the MMC submodules, as follows: Considering the equivalent resistance of the submodules, R sm,eq = R sm,on + R sm,of f , the arm equivalent resistance is given by: The DFIG fault current expression is solved considering the MMC parameters. Thus, the worst case is considered to demonstrate the MMC contribution to DFIG overcurrent suppression, which is the three-phase fault (LLL) with the highest peak current value given by [33]: in which τ r = σLr Rr is the rotor time decay. Therefore, considering the MMC arm impedance, the maximum amplitude of the phase-A current, (15) is rewritten as: and, τ r , with MMC parameters is given by: where K s = Lm Ls ; e −t τs ≈ 1; τ ≈ τ r ; R arm,eq is given by (14); L arm is the MMC arm inductance; (t − 0 ) is the component before the fault; L s and L m are the stator and magnetizing inductances; R s is the stator resistance; ω r is the rotor angular speed; s = ωr ωs is the slip; ω s and sω s are synchronous and slip angular frequencies; τ s , and τ are the stator and combined time decay constants; V is the voltage amplitude, s and r are the stator and rotor subscript, respectively. The terms involving the maximum peak current value in DFIG are suppressed with the inclusion of L arm and R arm .
The inductance effectively contributes to damping and preventing the sudden rise of the fault current, while the resistance acts to suppress the fault current amplitude. This effect is obtained replacing (17) in (16). Thus, the analysis demonstrated in (16)- (17) indicates that the MMC arm impedance can relieve the DFIG overcurrents under LVRT conditions. Moreover, the higher the number of MMC levels, the arm becomes closer to an impedance R-L, which leads to the effective suppression of DFIG fault currents. The L arm and C SM parameters selection criterion used in this paper is based on the procedure presented in [34]. R arm was adopted using typical values based on the resistance per length of the wire in MMC arm reactor manufacturing.

IV. SYSTEM DESCRIPTION AND CONTROL
Fig. 5 depicts the implemented system, comprising the DFIG-based WECS with the back-to-back MMC and a grid line filter connected to the three-phase network under fault conditions. Furthermore, to consider the MMC-DFIG dynamics, the controller's design is presented considering the new transfer functions. Table 2 presents the system parameters.
The equations that govern the DFIG control loops consider the interaction with the MMC. Thus, this paper proposes a modification in the vector control structure to consider the new dynamics inserted by the converter through the transfer function composed by DFIG with MMC. All equations are based on the theoretical fundamentals presented in the previous sections adopted by [35]. Therefore, the controller's design was performed considering an approximation by a second-order equivalent system. The development was performed through Kirchhoff's Laws to obtain the expressions representing the DFIG and MMC. For the GSC, the Laplace transfer functions in the 0dq referential are given by: where i gd and i gq are output currents; V arm,d and V arm,q are arm voltages; L eq = L f + Larm 2 and R eq = R f + Rarm 2 , in which L f and R f are the inductance and resistance of the grid line filter, respectively. The equations (18) and (19) represent the MMC transfer function for control design. Therefore, the control system has as input the references i * d and i * q , and the MMC arm voltages V * arm,d and V * arm,q as outputs. Fig. 6 depicts the block diagram of the current loop before and after considering the MMC in the GSC control loop. Thus, considering a PI controller, the closed-loop transfer functions with second-order system characteristics are given by: where k p and k i are the PI controller gains. Therefore, considering the GSC gains k p = k p(GSC) and k i = k i(GSC) and based on (20)  by equaling the denominator of the transfer functions to a second-order system [35]: where ω n is the natural frequency and ξ is the damping coefficient. Thus: Adopting ξ = 1, yields: where ω n represents the closed-loop poles, which can be chosen as x times faster than the open loop poles Leq Req , i.e ξ = 1, ω n = x Leq Req [35]. The same procedure is adopted for the RSC considering the MMC per phase impedance Rarm , (29) in which A = σL r + Larm 2 , and B = R r + Rarm 2 . Approximating the transfer function denominators to a second-order system and adopting ξ = 1, yields: where the RSC the closed-loop poles ω n is given by: The general control purpose is described as follows: the GSC employs a vector control-based strategy in synchronous reference frame dq0, in which the DC bus voltage, V bus , is controlled by an outer PI regulator providing the desired active power reference, P gref , through i gdref . An inner regulator controls the reactive power, Q gref , through i gqref ; this reference is zero, which indicates that there is no reactive power delivered to the network [3]. The Clarke and Park transform was applied for the currents measured at the CCP and transformed to synchronous dq0 reference, thus generating the i gd and i gq used in the inner controllers; these regulators provide the desired grid reference voltages through V f dref and V f qref , used in the Park inverse transform to generate the trigger signals through the PWM. For the grid Manipulate (21) mathematically and rewrite in (22) form Match the coefficients of same order terms in both sizes in (22) Obtaining the terms k i(GSC) and k as (23) and (24) p(GSC) Define the damping coefficient (i.e. ξ=1) Calculate the closed-loop poles through (27) Obtaining the controller gains

No
The control responds appropriately?

Yes
Enter DFIG and MMC parameters Approximate the closed-loop transfer function denominator (19) with a second-order system (21) Run simulation

End
Fine-tune the parameters

FIGURE 8.
Step-by-step control tuning scheme. synchronization, a phase-locked loop (PLL) provides the angle, θ g , used in Park direct and inverse transforms. The RSC control employs the stator flux vector orientation, λ s , in dq0 reference frame for variable decoupling, where the daxis is aligned with the stator vector flux [3]. Thus, the d-axis is aligned with the stator flux referential, λ sd = λ s , to cancel the quadrature component of the stator vector flux λ sq = 0. The RSC controls the DFIG through an external reactive power control loop, in which the Park transform applied to the rotor currents i rabc , obtaining i rdq .
The reactive power, Q s , can be controlled by i rd , while the torque is controlled by i rq . Thus, Q sref = 0 is maintained,  for no reactive power consumption, the d-axis rotor current reference, i rdref , is determined by the output of the PI regulator. A PLL is used for stator voltage grid synchronization, providing the angle θ r . On the other hand, the reference torque T emref is obtained at the output of a PI regulator that has as input the difference between the mechanical and reference speeds (ω m − ω mref ), thus obtaining the q-axis rotor current reference, i rqref . Two internal PI regulators generate the d and q-axis reference voltages, V rdref and V rqref , which are employed in the inverse Park transform providing the S rA , S rB and S rB RSC trigger signals. The PDPWM technique gives the number of active submodules by comparing the reference voltages, V f Aref , V f Bref , and V f Cref , between two level-shifted triangular carriers in phase with each other.
The PWM employs a sorting algorithm for MMC submodules capacitor voltage equalization; the algorithm is based on the MMC upper and lower arms current direction. The PDPWM gives the number of active submodules; the sorting algorithm determines which submodule should be inserted or bypassed. If the arm current is positive, the N submodules with the lowest voltages must be activated; conversely, the N submodules with the highest voltages must be activated if the arm current is negative. Finally, after determining the active submodules, the trigger signals are sent to the converters. The controller's design was performed using the method described in [3]. An trial and error tuning technique was adopted, including R arm and L arm values to determine the proportional K p and integral K i gains. Fig.  8 depicts the schematic step-by-step control tuning diagram used for the proposed control. The diagram is based on the abovementioned equations and demonstrates the calculation procedure of the GSC controllers; analogous, this scheme was adopted to obtain the RSC controller's parameters. Based on the above-mentioned DFIG controller's design proposal, the synchronism loop, and the PWM technique, Fig. 9 depicts the complete control loops structure of the GSC and RSC. In addition, Table 1 presents the major contributions of this paper.

V. PERFORMANCE ASSESSMENT OF THE PROPOSED MMC-DFIG LVRT WITH EXISTING CONTROLLERS
To demonstrate the MMC current-limiting function and damping capability, both symmetrical and asymmetrical fault scenarios were considered: single line-to-ground (SLG), lineto-line (LL), double line-to-ground (DLG), and LLL with a 150 ms duration. Each fault was simulated with specific fault resistance to result in voltage sags with 20, 50, and 80%. The MMC were set with 3, 21, 51, and 101 levels. Matlab/Simulink platform was used for DFIG-based WECS simulations. The performance assessment presented in this section considers the conventional DFIG vector control as [1] employing the proposed DFIG-based WECS with back-toback MMC. Table 2 presents the system parameters. The normalized RMS value of DFIG rotor and stator currents for two cycles immediately after the fault was adopted to determine the overcurrent level. For the LL, DLG, and LLL fault, the overcurrent level was obtained through the normalized RMS mean value of the individual phases. At the fault moment, the GSC and RSC converters were not turned off. A heatmap presents the simulation results of the pre-fault normalized RMS current values in Tables 3, 4, and 5, for 20, 50, and 80% voltage sag, respectively, regarding the fault type, the increase in the number of MMC levels, and the normalized RMS values of the rotor and stator currents. For the LL fault, considering the line parameters, the most severe voltage sag obtained was 50%. Table 3 presents the obtained results considering the DFIGbased WECS employing the MMC with the conventional vector control loops. Thus, the MMC transfer function was not considered, and only the control design based on the DFIG parameters was adopted, as described by [3]. Despite the MMC plant not being considered for control design, a reduction of the DFIG rotor and stator currents is provided when the number of converter levels increases due to the submodules increment that leads to an increase of the MMC arm R-L characteristic. A summary of the data in Table 3 is as follows:   for the worst-case LLL fault scenario, with the lowest overcurrent values for both rotor and stator. In this case, the reduction for the rotor and stator currents, considering the 3L-MMC and 101L-MMC, were 5.45% and 21.59%, respectively. Considering a 20% voltage sag scenario, the DFIG rotor, and stator fault currents were effectively suppressed with the MMC arm impedance in all fault scenarios, relieving the overcurrents under fault period as the number of MMC levels increased.

B. 50% VOLTAGE SAG SCENARIO
The same comparison was performed considering a more severe voltage sag of 50%; with the same approach employing the MMC with conventional control, the rotor and stator fault currents of the DFIG were substantially relieved. A summary of the data in Table 4 is as follows:

C. 80% VOLTAGE SAG SCENARIO
Finally, the fault current suppression method was assessed for the worst case, considering a voltage sag of 80% at the DFIG stator terminals for all kinds of faults. As expected, in this scenario, the MMC provided a relief in the DFIG's overcurrents, demonstrating that even with the conventional control without including the MMC dynamics, the system could perform the fault current limiting function when the MMC number of levels increased. A summary of the data in Table 5  For the worst-case scenario with 80% voltage sag, the DFIG rotor and stator fault currents performed similarly to the 20, and 50% voltage sag scenarios, relieving the overcurrent level as the number of MMC levels increased. Despite using conventional control loops, the performance assessment with vector control demonstrates the effectiveness of the proposed DFIG-based WECS fault current suppression method due to the MMC arm impedance currentlimiting function capability and increased level. Then, it maintained controllability even under fault conditions, reducing or avoiding the physical protection activation and providing LVRT enhancement.

VI. PERFORMANCE ASSESSMENT OF THE PROPOSED MMC-DFIG LVRT WITH PROPOSED CONTROLLERS
To validate the proposed fault current suppression method, simulations considering the proposed control structure in DFIG-based WECS were carried out. In order to perform a proper comparison, the same scenarios of 20, 50, and 80% voltage sags were considered, and the normalized RMS value was also adopted to measure the DFIG fault currents suppression enhancement. Table 6 presents the results obtained considering the DFIGbased WECS and the MMC using the proposed control structure, in which the transfer function representing the MMC dynamics was taken into account for the controller's design. Thus, all the control parameters such as the system time constant, the damping, and the controller's gains were recalculated, also considering L arm and R arm . The results obtained for 20% voltage sags highlight the behavior of the MMC interaction in the control plant, which provides a better dynamic response in the suppression of fault currents compared to the same previous scenario employing conventional control. A summary of the data in Table 6 is as follows:

A. 20% VOLTAGE SAG SCENARIO
• SLG fault: The rotor currents were relieved around 11.83% considering the MMC with 3 and 101 levels. Compared to the same previous scenario employing the conventional control, there was a reduction of 3.64% and 0.55% for the rotor currents considering the 3L and 101L-MMC. On the other hand, the stator currents were suppressed around 8.65% between the worst and best case. • LL fault: In this scenario, the DFIG rotor and stator currents were relieved around 6.45% and 8.33%, considering the 3L and 101L-MMC, respectively. The fault currents were also lower than the structure with conventional control for all levels of the MMC. • DLG fault: For the worst and best case, the rotor and stator currents showed better performance with DFIG fault current suppression around 7.59% and 40.81% with the 3L and 101L-MMC. Similar to the previous cases, the fault currents obtained a reduction for all levels of the MMC. • LLL fault: For the worst-case scenario, the 3L and 101L-MMC in suppressing the rotor and stator fault currents was 6.28% and 22.43%, respectively, and all the results obtained for the fault currents were lower than the results employing the conventional control structure.

B. 50% VOLTAGE SAG SCENARIO
The fault current suppression method for DFIG employing the proposed control structure was tested considering a 50% voltage sag as presented in Table 7. The same previous scenario conditions obtained for Table 4 were ensured so that comparisons with the conventional control could be appropriate. A summary of the data in Table 7 is as follows: •

C. 80% VOLTAGE SAG SCENARIO
The last scenario for the performance assessment was performed under the same conditions as in the results obtained in Table 5, considering a voltage sag of 80%, using the proposed control structure, including the MMC dynamics. A summary of the data in Table 8 is as follows: • SLG fault: The DFIG rotor and stator fault currents through the 3L and101L-MMC were suppressed by 10.51% and 22.44%, respectively. In addition, a signifi-VOLUME x, 2022  The results with the proposed control loops considering the MMC dynamics in the DFIG transfer function improved substantially compared to the DFIG-based WECS with the conventional vector control in Section V. Since the conventional control considers a traditional 2L-VSC converter for control design, the improved results are due to the MMC parameter interaction in the GSC and RSC controllers. This reflects the DFIG-based WECS operation with the backto-back MMC, which corroborates the effectiveness of the proposed fault current suppression method. Tables 9, 10, and 11 present the comparison summary of the MMC-DFIG LVRT performance assessment with existing (CTRL I) and the proposed controllers (CTRL II).

VII. CONCLUSIONS
This paper presented a new fault current suppression method for the doubly fed induction generator low voltage ride through improvement through modular multilevel converter. Several low voltage ride-through conditions covered symmetrical and asymmetrical faults with 20, 50, and 80% voltage sags. Furthermore, the interaction between the modular multilevel converter impedance was demonstrated through the dynamic equations, corroborating the validation of the results. During the fault period, the back-to-back converters operated continuously, ensuring the low voltage ride-through of the doubly fed induction generator. The performance assessment demonstrated that both the modular multilevel converter arm impedance and increased levels effectively suppressed rotor and stator fault currents. Through an trial and error tuning technique, the conventional control was able to drive the doubly fed induction generator under several fault conditions. Furthermore, unlike other proposals in the literature, neither additional hardware nor control loops are necessary for overcurrent reduction during the fault period, contributing to cost and implementation complexity reduction. The proposed approach also contributes to the employment of modular multilevel converters at a wide range of power levels in wind energy conversion systems under low voltage ride through conditions due to its modular structure, easy expansiveness, support for higher voltage levels, power quality, and fault tolerance. Improvements under lowfrequency operation condition are encouraged for further research and analysis with this paper proposal.