An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator

This paper presents a digital low-dropout regulator (DLDO) with three-level switching (TLS) and analog-assisted (AA) structure formed by dynamic-biasing asynchronous comparator, capacitive-coupling RC network and auxiliary power switch. The proposed AA-DLDO is fabricated in a 65-nm CMOS process. The minimum load current is 18 μA. The maximum undershoot is 200 mV under load transient of 4.82-mA/1-ns. The recovery time is 8 ns. The figure-of-merit of proposed design is better than the other DLDOs by more than 14 times.


I. INTRODUCTION
Digital low-dropout regulator (DLDO) enables voltage regulation at ultra-low supply and possesses the potential performance enhancements from process scaling of integrated-circuit technology [1]- [12]. The prior research works of DLDO were predominantly focused on load transient response, which is partly determined by switching frequency (f sw ), on-chip output capacitance (C OUT ) and turnon/off strategy of power-switch array. Like the typical digital circuits and dc-dc converters, a higher f sw and a larger C OUT would result in better dynamic responses, but much larger quiescent current (I Q ) and chip area are the costs. To achieve low-power operation and small circuit size of DLDO, many researchers focused on the turn-on/off strategy of power-switch array. Methods such as binaryweighted strategy [1]- [4], coarse-fine switching [5]- [8] and multi-step switching scheme [9] were reported. In recent years, the concept of hybrid structure by introducing analog part to the DLDO shows the opportunity to further improve dynamic responses. Analog-assisted (AA)-DLDO, therefore, becomes a new research direction to enhance transient performance. A novel AA-LDOs reported in [10] utilizes capacitive-coupling effect to momentarily increase the gate drive of power switches through the gate drivers, such that a temporarily increase of drain current helps to reduce the transient errors of the output voltage (V OUT ) of DLDO during load transients. However, there are some critical issues with this design. For example, a simple coarse-fine strategy to turn on/off the power-switch array does not impact the load transient significantly. Improvement from the AA part cannot be achieved for transients starting with a very low initial load current (I LOAD ). Details of limitations of the DLDO in [10] will be presented and explained in Section II. This paper proposes an AA structure formed by a dynamic-biasing asynchronous comparator, a capacitivecoupling RC circuit and an auxiliary power switch to further improve the dynamic response, which are recovery time (T R ) and the undershoot magnitude of V OUT (ΔV OUT ), of the DLDO, even though the initial level of load transient is very low. The proposed DLDO and simulation results will be presented in Section III. Experimental results and a comparison with state-of-the-art DLDOs will be reported in Section IV. Finally, the conclusion of this paper is given.

II. PROPOSED HYBRID LDO
In this section, the DLDO reported in [10] is revisited. The critical issues with the design are introduced. The information is expected to be useful to explain the motivations of proposed circuit methods to be presented in Section III.

A. Coarse-fine Switching
Coarse-fine switching of power-switch array with nonlinear word control to the coarse loop is utilized to the DLDO in [10] to improve load transient responses. Fig. 1 shows the schematic of a DLDO with typical coarse-fine switching. The structure of fine loop is same as the other designs. The coarse loop is divided into two subsections, namely SUB1 and SUB2, where the unit size of the power switch in SUB2 is M times bigger than that in SUB1. These two subsections are controlled by carry-in signal CI_M2H and carry-out signal CO_M2H. The upper bounded voltage and lower bounded voltage for dead-zone control circuit to activate/deactivate coarse loop for faster load transient response are V DZ+ and V DZ-respectively. The control signal, C_EN is used to activate/deactivate fine and coarse loop to achieve accurate and fast speed voltage regulations. The UP signal is used to determine whether the bi-directional shift register in these two subsections of coarse loop shifts up or down. Upon receiving load transient by the DLDO, the coarse loop will be activated directly. Initially, the small switches in SUB1 are turned on one by one. When all switches in SUB1 are turned on but they are not sufficient to provide the required amount of load current, they will be reset and one more switch in SUB2 is then turned on. This mechanism repeats until enough power switches in both SUB1 and SUB2 are turned on to fulfill the load requirement. The fine loop is used to provide higher accuracy of voltage regulation at the output finally. Even non-linear word control to the coarse loop is applied, two clock cycles are still needed to turn on a power switch in SUB2. A simulation of a DLDO with coarse-fine switching has been carried out. The results are shown in Fig. 2. Two cases of load transients with current step of about 0.85 mA with two different I LOAD , where the blue one represents 18 µA while the red one is for the case of 0.61 mA, are applied to observe the differences of ΔV OUT . Edge times of both load transient are the same. From the results, the DLDO with coarse-fine switching has a larger ΔV OUT when the initial I LOAD is low. The reason is that the case with lower initial I LOAD has fewer power switches turned on initially. Thus, when the DLDO cannot respond, only a small momentary increment of source-to-drain voltage (V SD ) of the power switches due to the undershoot helps to the increase the drain current provided by the power switches themselves. This effect is effective only when many and large power switches are initially turned on which is the case that the initial I LOAD is not small. To explain this concept more clearly, a test bench for an analysis of transient current generated by large and small power switches is conducted. Fig. 3 shows the momentary change of source-to-drain current (I SD ) upon the change of V SD due to undershoot (i.e., ΔV OUT ) for a fixed source-to-gate voltage (V SG ). From this analysis, ΔI LOAD generated by the power switches themselves without adjusting V SG are 0.74 mA (for large switch) and 3.8 µA (for small switch), respectively. As a result, when the initial I LOAD is small and only small power switches are turned on, ΔV OUT is much larger since this small ΔI LOAD cannot compensate the drop of V OUT . Therefore, the load transient response with small initial I LOAD is a critical performance in DLDO design.

B. Analog-assisted Part
A simple high-pass RC network formed by R P and C P is connected between V OUT and the lower supply rail (i.e., V SS ) of gate driver in [10], as shown in Fig. 4(a) where only one power switch, M P , is shown to illustrate the concept. There are two possibilities of operation: (i) M P is initially off, shown in Fig. 4(b), and (ii) M P is initially on, shown in Fig.  4(c). When there is a load transient at t 1 , an undershoot occurs at V OUT between t 1 and t 2 because of insufficient current from the power-switch array. The transient error (i.e., ΔV OUT ) is coupled by R P and C P to pull down V SS momentarily. The gate voltages of the power switches are then momentarily increased. When M P is initially off, the momentary increase of V SG is not large enough to turn on M P to provide momentarily current (i.e., ΔI DLDO ) to reduce ΔV OUT . The structure is useful only when M P is initially on. Thus, when the load transient starts from a very low level, not many power switches are on initially and the structure in Fig. 4(a) is thus not effective to reduce ΔV OUT . The structure is useful only when there are enough turned-on power switches, which is the condition that the minimum load level of the transient is high. It is noted that the load transient range of the DLDO in [10] is 2-12 mA, according to measurement results. Although it is claimed that the minimum I LOAD is 0.2 mA, this number is obtained from the measurement results of the steady-state performances (i.e., load and line regulations) but not from the transient performance. In fact, there is no measurement data to show the transient response when I LOAD starts from 0.2 mA.

III. PROPOSED AA-DLDO WITH TLS
The proposed AA-DLDO is shown in Fig. 5. The DLDO part is formed by fine, coarse and super-coarse loops, which are responsible for different load transient step magnitudes, to achieve the three-level switching (TLS) [13]. The basic operation principle of the tri-loop is to supply current to the load based on the transient error magnitude which is defined by two dead-zones. The unit size of power switch in super-coarse loop enables a much higher driving current to load for every clock cycle such that ΔV OUT can be reduced significantly when comparing to the conventional coarse-fine design. The AA-part is formed by a dynamic-biasing asynchronous comparator, a capacitive-coupling RC high-pass network and an auxiliary power switch (APS). Three different sizes of power switches with size ratio of 1:8:64 are used in the fine, coarse and super-coarse loop, respectively. The shiftregister lengths of fine, coarse and super-coarse loops are eight. The overall size of power switches is the same as the coarse-fine counterpart in reported [10] under the same loading condition. The driving current from the supercoarse loop is eight times larger than that from the coarse loop. The super-coarse loop is activated directly in one cycle upon receiving a large load transient. Thus, when comparing with the coarse-fine switching used in [10], the TLS is more effective to reduce ΔV OUT and T R under the same f SW . As shown in Fig. 5, The dead-zones of the coarse and super-coarse loops are DZ1 and DZ2, respectively. DZ1 is bounded by V DZ+1 and V DZ-1 , and DZ2 is restricted by V DZ+2 and V DZ-2 . Two control signals, C_EN1 and C_EN2, are used to activate/deactivate DZ1 and DZ2 to enable/disable the operation of these three loops as shown in Table I. It is not surprising that the DLDO with TLS can further reduce ΔV OUT and T R with a much higher f sw . However, efficiency will be seriously degraded due to high switching loss of power switches. To maintain a reasonable f sw to retain high efficiency, the proposed AA structure, which is used to deal with transients, is added in parallel to the DLDO structure. It does not require a specific load requirement, such as the minimum load condition, to activate it for transient improvement. An asynchronous comparator is used to control the APS to deliver transient current to the load. Thus, dynamic biasing is applied to the comparator to temporarily boost the speed of comparator at the instant of load transient. This approach effectively reduces the static power consumption by the proposed AA structure. Fig. 6(a) shows the connections of the asynchronous comparator, buffer, APS and the capacitivecoupling RC network. From Fig. 6(b), upon receiving load transient to cause ΔV OUT , the comparator triggers its output V CMPOUT to turn on the APS momentary to deliver a temporary current I AUX to help to recover V OUT . Initially, V CMPOUT is set above the middle of supply to turn off the APS in the steady state. Moreover, V REF_AMP is set by 20 mV below V DZ-2 to ensure that voltage regulation is not affected by proposed AA part when V OUT is within the dead-zone. The current consumption of the AA part is 1.3 µA only. Fig. 7 shows asynchronous comparator (M 02 -M 11 ) and the dynamic-biasing circuit (M RC , C P and M 01 ). M RC is a pseudo active load by using a PMOS transistor with its gate voltage to the ground. C P , which is implemented by metal-insulator-metal capacitor, is 0.2 pF in the design. Fig.  8 presents the mechanism of the proposed AA-DLDO with TLS upon receiving load transient. When I LOAD increases, V OUT drops below V REF_AMP . The super-coarse loop and AA part are activated to supply load current to the load. When V OUT recovers and stay between V REF_AMP and V DZ-2 , only the super-coarse loop is operating. The AA part is disabled when the output voltage is above V REF_AMP. Therefore, the proposed AA loop does not affect the operation of digital control when V OUT is recovered back to DZ2, and it does not influence the closed-loop stability in the steady state. The coarse loop will then operate when V OUT stays between V DZ-1 and V DZ-2 . Finally, the fine loop operates when V OUT stays between V DZ+1 and V DZ-1 . The small oscillation in the steady state is due to limit-cycle oscillation, which is a common situation of all DLDO designs. To verify the TLS outperforming the coarse-fine switching, a simulation is conducted, and the result is shown in Fig. 9. It is noted that no AA part is included in this simulation. The waveforms of V OUT and I LOAD of the coarse-fine switching and TLS are colored in blue and red, respectively. The TLS is much more suitable for a larger transient step than the coarse-fine switching for the same transient error magnitude (i.e., ΔV OUT ). Moreover, T R of the TLS is much shorter than that of the coarse-fine switching.
Another simulation is to show the effectiveness of proposed AA part for the DLDO with TLS. Fig. 10 shows the two cases with I LOAD = 18 µA-4.84 mA. Fig. 10(a) and Fig. 10(b) show the cases with edge time of the load transients of 1 ns and 5 ns, respectively. The cases without the proposed AA part have larger undershoot when the edge time is shorter. However, the cases with the proposed AA part can maintain the undershoot (i.e., ΔV OUT ) to about 220 mV due to the quick response of the proposed AA structure. Fig. 10 shows the closed-loop stability of proposed DLDO is maintained after the transient improvement achieved by the additional AA loop.

IV. EXPERIMENTAL RESULTS
The proposed AA-DLDO is implemented in UMC 65nm CMOS process. The chip micrograph is shown in Fig.  11. The active chip area of the circuit is 0.008 mm 2 . The measurement conditions are V DD = 0.6-0.75 V, V OUT = 0.5-0.69 V, I LOAD = 18 µA-4.84 mA, C OUT = 120 pF and f sw =38 MHz. The measured I Q is 13.5 µA. The proposed AA-DLDO with I LOAD = 18 µA-4.84 mA is suitable for near/sub-threshold logic applications. Table II summarizes the performance of proposed AA-LDO.  Fig. 12(a)-(d). The small oscillation of V OUT in the steady state at I LOAD = 18 µA shown in Fig. 12(a) (full view) is due to limit-cycle oscillation, which is a common situation in all DLDO designs. The measured load and line regulations are shown in Fig. 13 and Fig. 14, respectively. The worst-case measured load regulation is 9 mV/mA, and the maximum error voltage at different V DD is 37 mV.
A comparison of proposed AA-LDO with other stateof-the-art DLDOs are shown in Table II. All DLDOs are fabricated in the 65-nm CMOS technology. The minimum and maximum I LOAD , as well as T R in Table II are extracted from the measured load transient responses of respective design. The proposed AA-DLDO has the smallest I LOAD(min) . However, the others such as the design in [10], [11] and [12] have much higher I LOAD(min) to achieve good load transient responses. Although I LOAD(min) of the design in [4] is as small as 0.04 mA, its I LOAD(max) is 1.1 mA only. Since the measured transient conditions of the designs in Table II are very different, two figure-of-merits (FoM1 and FoM2) in [14] and [15] are used to compare the transient performances, where FoM1 is used to compare LDOs with small minimum load current while FoM2 is used to compare LDOs without specific load conditions. The proposed AA-DLDO has FoM1 of 0.052 ns and FoM2 of 0.02 ns, which are much better than the others by more than 14 times and 2.5 times, respectively.

V. CONCLUSION
In this paper, an AA-DLDO has been presented. The proposed analog-assisted structure to further enhance the design in [10] has been discussed. Operations of the proposed circuit methods, simulation and experimental results have been reported to verify the effectiveness of proposed method. The transient performance is better than the state-of-the-art DLDO designs by as high as 14 times, based on a FoM comparison.