Reduced Voltage Stress Asymmetrical Multilevel Inverter with Optimal Components

The article presents a single phase asymmetrical multilevel inverter with a reduced components and low voltage stress which reduces the size and cost of the system. The structure provides a maximum output voltage of 23 levels with asymmetrical DC sources. There exists several reliability issues in lowering the total harmonic distortion (THD) by utilizing higher components in the design of MLI despite of its merits. Achieving reliability and lowering the THD is a challenging task for the researchers. The proposed 23-level MLI has been investigated with various performance parameters like total voltage standing (TSV), cost function (CF), power loss and efficiency analysis. The suggested MLI is compared with the existing topologies in the recent past and found that it has less voltage stress across the switches and cost-effective. The TSV calculations show that the proposed structure is more efficient in reducing the losses and increasing the efficiency. Hence, based on the evaluations and the comparisons made with the other topologies, it is found that the proposed MLI is well suited for the medium power applications such as FACTS, SVC, DSTATCOM and DVR. As the proposed architecture provides the 23 level output voltage values with asymmetrical DC sources, the configuration can be utilized for improving power quality in grid-connected renewable energy sources. The topology provides a less THD value which is under IEEE standards. The proposed architecture has been designed in MATLAB/Simulink and is implemented experimentally in hardware prototype in the laboratory environment.


I. INTRODUCTION
Multilevel inverters (MLI) have gained abundant interest in recent decades because of their benefits of reduced dv/dt stress, greater electromagnetic compatibility, lesser total harmonic distortion (THD), and superior output waveforms. As a result, these are preferred in high-voltage applications including AC drives, renewable energy, FACTS, and dynamic voltage restorer (DVR) etc., [1]. MLI was first developed in 1975 by Baker and Bannister [2]. Cascaded Hbridge type (CHB) MLI is a common name for the topology, which consists of multiple series-connected H-bridges. The flying capacitor (FC), cascaded H-bridge (CHB), and neutral point clamped (NPC) techniques are the three most common MLI topologies. CHB has captured the market's interest and is extensively utilized by sectors due to features such as simplicity and adaptability, however, have a drawback in that it is restricted by the need for separate sources [3]. Static compensators, motor drives, grid-connected RES, and photovoltaics are just a few of the many uses for MLIs [4]. Traditional MLI designs have a substantial restriction to achieve higher voltage levels because of number power switch requirements. A converter system with more semiconductor switches is bulky, expensive, and complex because of a protection unit, gate driving unit, and heat sink are generally integrated with each power switch. As a result, one of the fastest-growing study fields in MLIs is lowering the power switch count, and several topologies with fewer devices have recently been presented [5]. Seventeen level asymmetric MLI topology for medium voltage applications with less dc sources count, less power switches, and lower dv/dt stress on switches was proposed in [6].
Novel MLIs have been presented to optimize the number of dc voltage sources and power switches [5]- [20]. The Hbridge structure was utilized to provide an alternate output voltage in the architectures presented in [7]. H-bridge switches, on the other hand, must be able to withstand large output voltages before they can be used. This issue is solved with H-type [8] and square T-type (ST-type) [9] structures, which provide alternate output voltage levels without the need for H-bridge. A new switched capacitor with single DC source and reduced components for low voltage RES applications was presented in [10] and an extended MLI topology with reduced switch and low voltage stress was presented in [11]. The topology presented in [12] employs the fewest total power electronic components. By connecting IGBT switch and diode in series/parallel. Using two dc sources and bidirectional switches coupled cross-network style, a rudimentary unit was created in [13]. As long as a fullbridge converter is used, this design may provide a multilevel output voltage on the load side while also working in asymmetrical mode. In [14], a topology is developed to minimize the maximum blocking voltage (MBV) on switches. The total standing voltage (TSV) in [15] is lower, making it a better choice for high-power applications. A unique generalized MLI configuration with optimal components, lesser power losses, and less blocking voltage is presented in [16]. The topology in [17] presents a switched capacitor MLI configuration with a low device count that has the benefits of negative polarity voltage generation without the use of an auxiliary H-bridge, the efficient voltage balancing can be done across the floating capacitors, and minimum PIV across the switches. In order to decrease the DC sources count, MLI based on switched capacitors are presented in [18] which produces nine voltage levels per DC source and also has several advantages such as enhancing the input voltage, but it suffers from a non-modularity feature.
In this work, a new MLI circuit is designed that solves all limitations and uses fewer components than similar topologies. The proposed MLI can be used to integrate distributed energy resources into medium voltage grids. The inverter's high-quality output voltage reduces the need for huge filters. The inverter reduces the size and weight along with the cost of the filters. Hence, the developed topology could be a reasonable solution for connecting PV sources in case of many DC sources are available. The proposed configuration can be employed in single-phase medium voltage applications. According to a comparison analysis, the recommended circuit uses fewer components, has reduced power loss values and increases the inverter's efficiency.
However, in modern topologies, the TSV at the power switches is analyzed for the performance calculations. To test the suggested circuit's performance, both simulation and experimental conditions of the proposed 23 level inverter are examined. The following are the most important characteristics of the suggested topology:  Using only three sources and 12 switches, the suggested topology produces output voltage levels of 7 and 23 in both symmetrical as well as in asymmetrical configurations.  The suggested architecture eliminates the need for an additional H-bridge circuit to produce alternate voltage levels, resulting in a considerable decrease in TSV.  The majority of the switches have less voltage stress, allowing them to operate at medium voltages.
 The harmonic profile of proposed MLI is superior to traditional inverters, and adherence to the standard of IEEE 519. The article is organized as follows: Section 2 presents the proposed circuit analysis as well as its general structure and also includes the selection of component value for extended topology, as well as TSV computations. Section 3 discusses comparative assessments of the suggested and other existing topologies. The proposed topology's power losses and efficiency are calculated in section 4. Cost estimation of the proposed design for medium voltage applications is discussed in Section 5. Both simulation as well as prototype experimental results with control switching approaches are provided in Section 6, and the conclusion is provided in Section 7, preceded by the references cited.

II. PROPOSED 23 LEVEL MLI TOPOLOGY
The proposed configuration comprises three dc sources namely V 1 , V 2 , and V 3 , and twelve unidirectional switches S 1 to S 12 are depicted in Figure 1. There are three units in the proposed topology: a left unit (L-unit), a center unit (C-unit), and a right unit (R-unit). Each unit is powered by its dc power supply. V 1 , V 2 , and V 3 respectively. In R-unit the switches (S 1 , S 2 ) and (S 3 , S 4 ), in C-unit the switches (S 5 , S 6 ) and (S 7 , S 8 ), in L-unit the switches (S 9 , S 10 ), and (S 11 , S 12 ) are never switched ON at the same time. In this manner a short circuit between the DC sources are prevented. Both symmetric and asymmetric combinations may be operated using the proposed topology.
The number of switches 'N SW ' required may be mathematically related to the number of levels N Lev by using the equation: The suggested topology uses unidirectional power switches for all of the switches. As a result, the required gate driver circuits N GDK equals the number of IGBTs N SW , and is written as: = = 2( − 1) (4) The maximum voltage output produced V L, max is given by: In symmetric mode, the proposed configuration produces 7 levels of voltage output with magnitudes of zero, ±1V dc , ±2V dc , and ±3V dc .
The required DC sources N DC in asymmetric mode may be mathematically related to the number of levels N Lev used by the equation:   The suggested topology uses unidirectional power switches for all of the switches. As a result, the required gate driver circuits N GDK equals the number of IGBTs N SW , and is written as: The maximum voltage output produced V L, max is given by: In asymmetric mode, the proposed configuration produces 23 levels of voltage output with magnitudes of zero, positive (+1 V dc to +11 V dc ), and negative (-1 V dc to -11 V dc ). The proposed 23-level asymmetric MLI topology's switching states are tabulated in Table 1. In addition, Figure 2 shows the relevant connection diagrams for various voltage levels, while Figure  3 shows the expected output with varied switch states.

B. Analysis of TSV
Total maximum blocking voltage is one of the most important qualitative characteristics, which is referred to as the algebraic sum of the maximum voltage stress on the switches [21]. S 1 is expected to describe the TSV computation. Figure 2 is used to compute the MBV of S 1 (off-state). (+1V dc or +4V dc or +5V dc or +8V dc or +11V dc or -2V dc or -6V dc or -9V dc ) in which standing voltage on S 1 is created by using the R-unit dc source V S1 = 1V dc. The MBV of particular switches are calculated as follows: For R-unit: MBV S1 = MBV S4 = 1V dc. MBV S2 = MBV S3 = 1V dc For L-unit: MBV S9 = MBV S11 = 7V dc. MBV S10 = MBV S12 = 7V dc. For C-unit: MBV S5 = MBV S7 = 3V dc. MBV S6 = MBV S8 = 3V dc. The term "Normalized voltage stress (NV strs )" refers to the ratio of V strs across the switch to the maximum voltage V L,max [22], given by = Vstrs VL,max Where V strs is real voltage stress of the switch and corresponding values are tabulated in Table 2. Switches S l , S 2 , S 3 , and S 4 experience the lowest V strs and NV strs , i.e. V dc and 9.09% respectively, whereas switches S 5 , S 6 , S 7 , and S 8 experience three times the lowest V strs and NV strs , i.e. 3V dc and 27.27% respectively, and switches S 9 , S 10 , S 11 , and S 12 experience the highest V strs and NV strs , i.e. 7V dc and 63.36%.   by four H-bridge switches is equal to the algebraic sum of DC sources in the circuit, i.e. 7V dc [22]. The highest output voltage in the recommended MLI design is 11V dc , which creates a level of 23 at the output voltage, but the algebraic sum of DC sources is more than the MBV (7V dc ) encountered by the switch. Four switches S 9 , S 10 , S 11 , and S 12 in the proposed design are exposed to maximum voltage stress of 7V dc , even though the voltage stress across the switches in the proposed topology is spread unevenly. The minimum voltage stress is experienced by one-third of power switches, the highest voltage stress is experienced by 33.33 percent of total power switches, and the intermediate voltage stress is experienced by the remaining one-third of power switches. As a consequence, the recommended MLI topology optimizes the utilization of DC sources with minimum TSV and switches, hence the cost will be reduced.
The term TSV is stated as the algebraic sum of MBV across individual switches and is expressed in equation 11, equation 12 provides the TSV PU .

C. Extended structure for n levels.
At the output waveform, the proposed structure may generate 23 levels. An expanded architecture is developed for the higher voltage levels, as illustrated in Figure 5. The C-unit in extended topology is made up of 'n' number of subunits connected in sequence from C 1 , C 2 , C 3 , -------, and Cn. Each subunit has four IGBTs that are powered by DC sources V c1 , V c2 , V c3 , and V cn . The R-unit source magnitude is V R = 1V dc , the L-unit V L = 7V dc , and the C-subunit are V C1 = V C2 = ---------=V Cn = 3V dc .
The number of switches N SW required in extended structure may be mathematically related to the number of levels N Lev used by the equation: The suggested topology uses unidirectional power switches for all of the switches. As a result, the required gate driver circuits N GDK equals the number of IGBTs N SW , and is written as: The maximum voltage output produced V L, max is given by: MBV of individual switches are given as For R-unit: MBV S1 = MBV S4 = V R MBV S2 = MBV S3 = V R For L-unit: MBV S9 = MBV S11 = V L MBV S10 = MBV S12 = V L For C-unit: Therefore for the extended topology, TSVExtd is calculated as Extd = MBV R−unit + MBV C−unit + MBV L−unit

III. COMPARISONS
To evaluate the benefits and capabilities of the suggested topology, a comparison is made with other recent topologies. Quantitative and qualitative evaluations of similar and different asymmetrical MLI configurations are carried out to showcase the benefits of the suggested topology. For both the same number of output voltage level topologies [21][22][23][24][25][26][27][28] and different numbers of output voltage level topologies [6], [9], [16], [20], [29][30][31], a comparison has been made per level concerning the required driver circuits, dc sources, switches, the factor of the component count, maximum conducting devices, TSV PU , and cost factor are tabulated in Table 3. Several parameters, such as the switch count N SW , source count N DC , driver circuit count N GDK , diode count N D , capacitor count N C , and total standing voltage TSV can be used to calculate the cost factor (CF). The cost factor is calculated with the following formula: In practice, the value of 'α' should be larger than and less than unity, respectively. For the optimal assessment of the cost function, the respective values of 'α' are approximated as 0.5 (<1) and 1.5 (>1) in the designed MLI. The component count per level is calculated as. Figure 6 presents the display of several performance characteristics to assess the suggested topology. The suggested topology has a significantly higher performance in terms of required switches for producing the desired output  Figure 6a. However, the design in [25] requires fewer switches than the proposed MLI, but more DC sources. The topology in [25], [28] has better values than proposed, however, the demand for DC sources is considerable. As a result, as illustrated in Figure 6d, the total number of components per level is less as compared to other topologies. According to Figure 6e, the THD value is lower than the high TSV PU design [21], and the TSV PU of the suggested topology is lower than that of recent topologies, as shown in Figure 6f. Finally, from Figure 6g, the suggested topology has the lowest cost factor when compared to recent topologies.

IV. POWER LOSS AND EFFICIENCY CALCULATION
In multilevel inverters, there are two significant power losses. They are conduction power losses (P C ) and switching power losses (P Swi ). Overall conduction loss is calculated by adding the conduction losses of both IGBTs (PC SW ) and anti-parallel diodes (P C D ) in the current path and is expressed as: Where i m is the peak output current. V SW , V D is the power switch and diode threshold voltages, R SW , R D are the ON-state switch resistance and diode resistance, and β is a switch specification constant provided by datasheet.
If N SW and N D are the switches and diodes conducting at the same time (t) to produce each level then, the average conduction loss is = The power consumed at the instant of the switch turn ON and turn OFF is known as switching loss (P Swi ). For both the switch and the antiparallel diode, this loss is estimated. The following formula can be used to determine turn-on and turnoff energy loss (E on , E off ) Similarly, Where time to turn OFF and ON, and loss of the switch q are t off , t on and E off q , E on q respectively. I and I I are the switch current before turn OFF and after turn ON and V sw q is the OFF state switch voltage. Thus Where fundamental frequency is f, N on,q, and N off,q is the number of times q th switch turn ON or turn OFF in one fundamental cycle. Thus, total power losses are = + The total efficiency (η) can be calculated as The output and input powers are P out and P in . The output power can be calculated as = * (32) Table 4 summarizes the power losses and efficiency of the proposed 23-level MLI and the efficiency at different loads are shown in Figure 7.

V. COST EVALUATION
It is necessary to compute the proposed MLI's maximum working voltage in order to determine its greater cost-benefit when it is utilized for medium voltage applications. Considering that the maximum standard commercial voltage of a switch is V SW ccv , therefore the proposed multilevel inverter's maximum operating voltage is equal to √ .
⁄ and γ is a safe operating factor of the switch, which is generally assumed to be 1:7. As a result, the suggested topology's operation voltage may be determined by determining the maximum switch voltage. For medium voltage applications, the switch voltage is calculated by assuming the 3-phase operating RMS voltage as 2.3 kV, if the maximum switch voltage is 3.3kV. For 1-φ, the operating RMS voltage will be 1328V, with a maximum voltage of 1878V. As a result, the voltage magnitudes of 23-level MLI will be V 1 = 170.72V, V 2 = 512.18V, and V 3 = 1195.04V for an RMS voltage of 1328V. Thus the switch rated voltage for the recommended topology is determined using Table 2 and V SW ccv is considering from Table 5. Table 6 calculates and compares the costs of needed IGBTs and driver circuits for 1φ proposed 23-level MLIs and existing 13-level and 11-level MLIs [34], [33].   The MITSUBISHI Company produces a nominal current of 400A commercial IGBTs. As a role example [32], the costs of power diode (single pack, Mouser Electronics) and IGBTs (single pack), as well as the driver circuits (Semikron, dual pack), are in USD. From the price comparison the proposed MLI is less expensive.

A. Control scheme
The gate pulses are generated in MATLAB/Simulink using the round-robin condition (staircase modulation approach). Because of its primary advantages, such as less complexity and lower switching losses, the staircase Modulation technique is preferred over the classic PWM technique. This is true for both high-rated MLIs with higher voltage levels (N) and low-rated MLIs with lower voltage levels (N). This is the most frequent and well-known method for multilevel inverters going forward. In addition, with its lower losses for MLIs with higher ratings, this technique is the greatest alternative to the sine PWM switching technique. While symmetric MLIs are the most prevalent, using asymmetric MLIs with a cascaded H-Bridge reduces total harmonic distortion (THD) even further. half-step with a value of p 0/2 , appearing at the 0 th phase angle, which is 0 = 0. M = (N-1)/2 excluding 0 , is the total phase switching angles per quarter-wave which is related to N [34].
The generalized voltage of staircase modulation waveform can be represented as V(θ) = ∑ ( − ) + 0 =1 (33) where θ and is lies in between 0 to 90 degrees, unit step function ( − ) is zero if < whereas its value is unity if ≥ and the toggle function is zero for odd and 0.5 for even.
The normalized fundamental component of voltage at modulation index MI is given by The range of voltage is given by The expected staircase waveform for the proposed topology is shown in figure 9. The variation of modulation index (M) with respect to the number of levels (NL) is shown in TABLE VII.

B. Simulation results
The performance of the suggested configuration has been evaluated through simulation experiments using MATLAB/Simulink software. TABLE VIII lists the many parameters that were used in the analysis. A carrier frequency of 5 kHz is used to produce the pulses in simulation, and the design is evaluated with resistive and inductive loads of 100 ohms 187mH respectively. Figure 10(a) shows the simulated output voltage, while Figure 10(b) displays the simulation output voltage and current waveforms. The magnitude of source voltages in asymmetric source configuration is considered as V 1 =35V, V 2 =110V, and V 3 =255V. At 400V peak voltage and 4 A load current, the inverter can produce 23 levels of output. Figure 10

C. Experimental results
As illustrated in Figure 11, a single-phase prototype is built in the lab to evaluate the proposed MLI technology. The prototype is made up of 12 IGBT switches (CM75DU-12H) that are activated by optocouplers (MCT2E), and a dual dc supply provides input dc sources. The load parameters are 100 resistive load and 187mH inductive load. The real-time controller dSPACE1104 is used to build the switching control scheme and DSO is used to observe the voltage and current waveforms. Figures 12 and Figures 13 show the experimental results with resistive load at a steady-state output voltage V 0 = 400V (282.84 V rms ) and load current I 0 = 4A (2.82 I rms ) respectively. With motor load, the output voltage V 0 = 400V and the load current I 0 = 6.8A equivalent to 4.8A I rms are shown in Figure 14. As illustrated in Figures 15 and 16

Time (Sec)
dynamic response of the proposed MLI is accomplished by adding an inductive load parallel to resistive load or contrariwise. With a power analyzer, the total voltage harmonic spectrum of 3.23% is measured and is displayed in Figure 17. Due to the wide range of operation with the modulation index, the proposed reduced switch count MLI is an alternative to traditional MLIs in industrial requirements. Individual photovoltaic panels with varying ratings are fed into each of the three input sources of proposed MLI, which correspond to the ratings of the DC sources [35]. To accomplish this, several control objectives must be met, including the inverter maintaining optimal power quality within grid constraints, minimizing harmonic distortions in the output ac voltage waveform, and extracting the maximum amount of energy possible from solar panels under varying irradiance conditions in order to provide an efficient and stable output throughout its operation. Additionally, to ensure reliability, the extracted power has been transferred to the output with a power factor of unity. Due to the fact that different solar panel ratings are used for different DC sources, an efficient maximum power extraction method is used to harvest energy in a variety of irradiance conditions. In this regard Power factor control is critical to transferring solar power to the grid, which is closer to a power factor of 0.95. Because the inverter rating is low according to IEC 929-2000 and IEC 62109-2 standards, reactive power consideration is not required in these systems. Furthermore, the suggested MLI is more suitable for solar PV applications in terms of fault ride-through capability and power balance because it has redundant switching states[36].

VII. CONCLUSION
An asymmetrical reduced component 23 level singlephase multilevel inverter configuration was proposed for medium voltage applications. Twelve switches and three DC sources are used in the proposed topology to produce eleven positive voltage levels and can be expanded to produce n voltage levels by adding a few devices. According to the findings of the proposed MLI and the comparisons with existing MLIs, the suggested MLI requires a lower component count per level to generate more output voltage levels. For 23-level MLI, several characteristics are examined, including cost function (CF), total standing voltage (TSV), and total harmonic distortion (THD) which is under IEEE standards. The proposed MLI is compared with other existing topologies and found to be superior among various parameters and found that it is cost-effective and compatible with the TSV and component count per level factor. As the proposed MLI has an asymmetrical sources, it can be widely utilized in hybridized energy sources where the various types of sources are interfaced. Hence the proposed MLI is well suited for medium-power and gridconnected FACTS devices such as DSTATCOM, and DVR.