Hierarchical Single-Objective Model Predictive Control with Reduced Computational Burden in Cascaded H-Bridge Converter based on 3-level Flying Capacitor Unit Cell

This paper presents a control algorithm to reduce the computational burden of model predictive control in a grid-connected single-phase N-cell cascaded flying capacitor H-bridge (CFCHB) multilevel converter of a solid-state transformer. The proposed control algorithm is a finite-control-set model predictive control (FCS-MPC) that is based on a hierarchical structure controlling the grid current, DC-link voltage, and flying capacitor voltage, using each cost function through three layers. Unlike the conventional multi objective cost function that evaluates and compares all candidates to determine the optimal state, the proposed method uses a single-objective cost function by separating the control variables to determine the optimal state through calculation without comparison. Therefore, the amount of computation is significantly reduced compared with that of the conventional method, and the execution time is shortened. Thus, the sampling period can be shortened and the switching frequency can be increased. Further, it can lead to using a smaller inductor to produce a high-quality grid current, which can help reduce the system size and cost. The execution time is not large, even if the voltage level increases and the effect of time reduction is large compared to the existing method, because the computational burden of the proposed method is linearly proportional to the number of cells. The voltage level expansion is easy and suitable for digital system implementation, and the control performance is not affected. The effectiveness of the proposed method is verified through the simulation of a single-phase 250 kW 9-cell CFCHB multilevel converter using PSIM and an experiment with a single-phase 2 kW 3-cell CFCHB multilevel converter at the laboratory scale.

The number of remaining cells nor Remaining AC-side terminal voltage levels noj,max Upper limit bound of voltage level noj,min Lower limit bound of voltage level Kpj Difference between the two switching states Ts Sampling period

I. INTRODUCTION
Global interest in low-carbon emissions has grown recently, and the transition to eco-friendly vehicles, especially electric vehicles (EVs), has witnessed rapid progress [1]. EVs convert electricity to power; no pollutants are emitted during this process, and the power conversion efficiency is superior to that of internal combustion engine vehicles. However, EVs are faced with challenges such as insufficient charging infrastructure and an excessively long charging time compared with gasoline. A DC extreme fast charging (XFC) station that connects a solid-state transformer (SST) to the MV line for fast charging has been studied to compensate for these shortcomings [2]- [3]. The low-frequency transformer (LFT) can be replaced by a high-frequency transformer (HFT) because of the SST structure, thereby reducing the system size. Thus, it is possible to install more charging ports in the same area, and faster charging can be achieved owing to the higher power capacity of the charger. Further, the number of power converters is reduced compared to the existing charging stations because there is no need for an AC/DC converter per charger, which increases efficiency and reduces installation costs [4]. The SST structure in the XFC Station consists of two stages. Stage 1 converts AC to DC as an active rectifier and performs power factor correction (PFC) through active power control; it also enables bidirectional power transmission. Stage 1 is composed of a multilevel converter using a high-voltage power device because it is connected to an MVAC. A modular isolation architecture, which is a structure with several independent DC sources, can be easily replaced in the case of failure and provides scalability in terms of voltage and current compared to a single isolation architecture structured with a common DC source; this is because the unit cell is connected in cascade in the form of a module. The cascaded H-bridge (CHB), which is a representative topology among modular isolation architectures, has been widely used because it can employ the control method applied to the two-level converter [5]- [6]. However, there is a disadvantage in that the number of HFTs increases with an increase in the number of DC sources, i.e., the system size and weight increase with an increase in the number of unit cells. The number of cells and HFTs can be reduced compared to CHB by cascading the unit cell structure using a three-level topology instead of a two-level full bridge to compensate for this drawback [7]- [8]. Among the three-level topologies, a flying-capacitor converter (FCC) is superior in terms of efficiency because there is no diode, unlike a neutral-point clamped converter (NPC); further, it is relatively easy to control the FCC because its structure is not complicated [9]. It is difficult to control the flying capacitor (FC) voltage because the switching frequency is limited to achieve high efficiency in high-voltage applications. However, with the recent advent of wide-bandgap power devices, it is now possible to increase the switching frequency by applying SiC MOSFETs to SST [10]- [12]; thus, the FC voltage control performance can be improved. A cascaded flying capacitor H-bridge (CFCHB), which is a cascade structure with a three-level FCC full bridge as a unit cell, can be considered a good alternative in terms of easy voltage level expansion, size, and price.
Finite-control-set model predictive control (FCS-MPC) can be easily applied to nonlinear systems based on its intuitive characteristics; it does not require pulse-width modulation. Therefore, they have recently attracted considerable attention in the field of power electronics with a limited number of switchings [13]- [15]. However, FCS-MPC requires a large number of calculations because it is an online optimization problem. Furthermore, it should be completed within a short sampling period, which limits its implementation on hardware platforms. A multilevel converter with a large number of redundant states to be compared because of a large number of power devices suffers from the problem of limiting the switching frequency. This is attributed to a long sampling period when applied in a real-time hardware platform because of the large amount of calculation, which lowers the current quality. Thus, research has been conducted to reduce the calculation time by efficiently reducing the number of calculations.
FCS-MPC can be implemented with the fieldprogrammable gate array (FPGA) that can reduce the execution time by using parallel operation [16]- [18]. However, this benefit can only be achieved using an FPGA. The most important approach for reducing the computational burden is to decrease the number of comparisons. The number of comparisons can be reduced by targeting only adjacent voltage levels [19]- [21] and by applying FCS-MPC to each unit cell in a two-cell CFCHB [22]. Algorithms based on FCS-MPC using dynamic programming [23], a pipeline scheme for one cell by one cell [24], and a simplified branch and bound [25] for CHB are presented. However, the cost function comprises multiple control objectives that include current and voltage control, and therefore, laborious tuning and trade-offs are inevitable because of the weighting factor. A method for separating the cost function for current and voltage control using stratification has been studied to eliminate weighting factors [26]- [28]. The weighting factors disappear because the  control variables are separated, which eliminates the need for tuning; consequently, the trade-off between the current and voltage control disappears. Kim et al. [28] presented a control method for reducing the number of states to be considered using a hierarchical structure in a CFCHB. However, the cost function still comprises multi objective variables; therefore, the number of comparisons increases exponentially when the voltage level increases, significantly increasing the computational burden. This paper proposes a single-objective model predictive control based on a hierarchical structure for a single-phase Ncell CFCHB for the active rectifier of SST to overcome the above problems. Unlike the conventional control method based on a hierarchical structure, in the proposed method, the cost function is configured as a single objective and the optimal value is determined only by calculation without comparison. Therefore, the number of comparisons in the conventional method increases exponentially when the voltage level is expanded, and the execution time increases significantly. However, the execution time of the proposed method does not increase significantly because the number of calculations increases linearly. Thus, the proposed method is easy to generalize and implement in real-time digital systems. Also, there is no degradation of the voltage control performance, and the sampling period can be reduced because of the reduction in the calculation time; thus, the switching frequency can be increased to improve the current quality.
The remainder of this paper is organized as follows. In Section II, the characteristics and mathematical modeling of a single-phase CFCHB multilevel converter are presented. Section Ⅲ introduces the proposed control method. The effectiveness of the proposed control method is verified through simulations and experiments in Section IV. Finally, the conclusions are presented in Section V. Fig. 2 shows a schematic of a generalized single-phase CFCHB composed of N unit cells. The grid voltage vg is connected to the active rectifier through the grid reactor Lg and grid line parasitic resistance Rg. The unit cell comprises two legs with the same structure; each leg has four power devices and an FC. Both legs share a DC-link capacitor. A rectifier is constructed using cascaded cells with a symmetric topology without a common DC bus. The leg is represented by p, i.e., leg A is represented by p = a and leg B is represented by p = b; p { ∈ a, b}. The number of unit cells is represented by j; j ∈ {1, 2, …, N}.

II. MATHEMATICAL MODELING OF CFCHB
The switching states of power devices are indicated by Tpij and expressed as 1 for the case of turn-on and 0 for turn-off; i {1, ∈ 2}. If dead time is not considered, the lower switching state operates complementarily to the upper switching state Tpij. Therefore, the pole voltage of leg vopj is determined according to the state of the two upper switches, and it is output as three-level.
The dynamic characteristics equation of the grid current ig can be expressed using Kirchhoff's voltage law as Assuming that the input and output powers of each cell have no loss in the converter, the input and output powers are the same according to the law of the conservation of energy. Therefore, the dynamic characteristics equation of Vdcj can be expressed as where Cdc represents the DC-link capacitance and RLj represents the load of the j-th unit cell.
The current flowing through the power device is determined using Tpij and ig. The current flowing through the power device in leg A iaij can be expressed by (5). The current flowing through the power device in leg B ibij can be expressed by (6) Tb1j because the direction of the grid current flowing through the power device in leg B is opposite to that of leg A.
According to Kirchhoff's current law, the current flowing through an FC ifpj is obtained by the switching states of the two upper power devices adjacent to the FC, as indicated in (7)- (8). Therefore, it is essential to select appropriate switching states that satisfy the charge balance to control the FC voltage because the direction of the current flowing through the FC is determined according to the two upper switching states connected to the FC.
The current flowing through the FC can be expressed as the dynamic characteristics equation of the FC voltage as where Cf denotes the FC capacitance. Fig. 3 shows a block diagram of the proposed algorithm. The proposed block diagram shows an analog-to-digital (A/D) conversion block, a power control block, and a hierarchical FCS-MPC block. In the A/D block, ig, vg, Vdcj, and Vfpj are converted to digital values represented by ig k , vg k , Vdcj k , and Vfpj k , respectively; here, k represents the time at the instant of sampling. In the power control block, the error between the average of all DC-link voltages and the command voltage of the DC-link voltage Vdc * generates the d-axis grid current command Id * through the PI controller. The phase angle of the grid voltage θ k is estimated using vg k and the phase-locked loop (PLL). The grid current command ig * is created by synchronizing θ k with Id * .

III. PROPOSED ALGORITHM BASED ON FCS-MPC
The hierarchical structure of the FCS-MPC block comprises three layers. Layer I determines the optimized total AC-side terminal voltage level noT to control the grid current. Layer II determines the optimized AC-side terminal voltage level of the j-th cell noj for regulating Vdcj. The cell priority Pc is evaluated using a sorting algorithm to determine the voltage level for one cell. Finally, Layer III determines the switching states suitable for maintaining the FC voltage balance by separating noj into each leg.

A. LAYER :
Ⅰ GRID CURRENT CONTROL The differential term of (3) is transformed into a discrete-time model using the forward Euler method (10) to control the grid current using the FCS-MPC. A discrete-time model for ig is  (10) into (3), and the grid current after one sampling period ig k+1 can be predicted as where Ts denotes the sampling period.
As voT represents the sum of voj, ig k+1 is predicted by replacing voT with (2).
It is necessary to use a predicted value after two sampling periods to compensate for the computational delay that occurs in digital hardware platforms [29]. The grid current after two sampling periods ig k+2 can be expressed as The error between Vdcj and Vdc * is assumed to be small; therefore, Vdcj is equal to the average of all Vdcj values. The sum of the output voltage levels of all cells is noT, and therefore, by substituting (14) into (13), ig k+2 can be expressed by (15).
Like ig k+1 , a discrete-time model of Vdcj can be predicted using the forward Euler method (16). Vdc k+1 can be predicted using (17) by substituting (16) θ k is estimated using PLL. vg is expressed in the form of the cosine of the grid peak voltage Vg and θ k as The grid frequency is fixed at 60 Hz, and therefore, the phase angle of the grid voltage after one sampling period is equal to θ k plus ωTs; therefore, Vg k+1 is expressed as According to (15), ig k+2 can be predicted using ig k+1 , Vdc, avg k+1 , vg k+1 , and noT k+1 . Substituting (12), (18), and (20) into (15), ig k+2 is determined only by noT k+1 . A single-objective cost function Jg that shows the error between ig * and ig k+2 is defined in (21) to control the grid current and to determine noT k+1 that minimizes the error.
Jg is a quadratic function of noT k+1 because ig k+2 has only one variable, i.e., noT k+1 . Therefore, the global minimum of Jg is at the critical point at which the partial derivative becomes zero. The optimized noT can be obtained as an integer value close to the critical point using the ceiling function because noT is an integer type. To prevent out-of-range errors, noT is limited to the feasible region: -2N ≤ noT ≤ 2N. min ( ) s.t. [ 2 , 2 ] g oT oT J n n N N   ⌈x⌉ represents the ceiling function and is the smallest integer greater than or equal to the real number x; ⌈x⌉ = min{x1 Z: ∈ x1 ≥ x}.

B. LAYER Ⅱ: DC-LINK VOLTAGE CONTROL
In the proposed algorithm, Layer II consists of two steps to select noj using the greedy algorithm.

1) SORTING TO SET THE PRIORITY OF CELLS
The priority of the cells is determined by the DC-link voltage error to control Vdcj. The sum of noj k+1 should be noT k+1 , which was determined in Layer I, and therefore, the probability that there is no best option in terms of DC-link voltage control increases as the priority order returns. Therefore, the larger the DC-link voltage error, the higher is the priority order. The priority order is determined by sorting the DC-link voltage error of the cells in descending order using quick sort with divide and conquer.

2) DETERMINING THE OUTPUT VOLTAGE LEVEL FOR EACH CELL
The DC-link voltage after two sampling periods Vdcj k+2 is predicted to determine noj using (17) as Substituting ig k+1 and Vdcj k+1 obtained from (12) and (17) into (24), Vdcj k+2 is determined by noj k+1 . A single-objective cost function Jdcj that shows the error between the average DClink voltage and Vdcj k+2 is defined in (25); it is used to determine noj k+1 that minimizes the error.
Similar to Jg, Jdcj is a quadratic function of noj k+1 because Vdcj k+2 has only one variable, i.e., noj k+1 . Therefore, the critical point at which the partial derivative becomes zero is the global minimum. noj can be obtained using (27) However, noj should be limited to make the sum of all noj equal to noT: The limit range is determined by the number of remaining cells Nr for which noj should be selected and the remaining AC-side terminal voltage levels nor. In the case of the m-th order (Pc = m), Nr is expressed using the total number of cells N as (28), and the AC-side terminal voltage level determined in the m-th order is expressed as no k+1 |Pc=m. nor can be obtained (29) as the subtraction between noT and the sum of the AC-side terminal voltage levels obtained up to the previous order.
The minimum and maximum output voltage levels for each cell are determined by Nr and nor, as summarized in Table I. For example, for Nr = 2 and nor = 4, the sum of the output voltage levels of the two cells should be 4. Since the range of noj is [−2, 2], the output voltage level of both cells should be 2. Therefore, in this case, the maximum and minimum levels of noj are determined to be same value 2. When nor = 3, the maximum level noj,max is set to 2 and the minimum level noj,min is set to 1 because the output voltage level of both cells is composed of 1 and 2. For Nr = 1, the output voltage level of the last remaining cell is nor. Therefore, in this method, the higher the priority, the wider is the output voltage level selection range; thus, the level that is more suitable for regulating Vdcj can be selected. The range of the optimized noj obtained using (27) can be limited to [noj,min, noj,max] using the minimum and maximum levels obtained in this manner.

C. LAYER Ⅲ: FLYING CAPACITOR VOLTAGE CONTROL
In this layer, the switching states suitable for FC voltage control are identified while determining noj k+1 in Layer II. However, unlike the conventional FCS-MPC method, cells are divided into two legs and the switching state of each leg is sequentially determined to reduce the number of switching state combinations to be compared; the starting order of the legs is alternated. If the k sampling instant starts from leg A, the next k+1 sampling instant starts from leg B. The two-leg output voltage levels must be set according to the noj determined in Layer Ⅱ because noj is determined by noaj and nobj as in (30).
It is necessary to predict the FC voltages to select suitable switching states for the FC voltage control. The current flowing through the FC is expressed by the differential term of the FC voltage. After substituting (7) or (8) into (9), it is transformed into a discrete time model (32)-(33) using the forward Euler method (31).
According to (32)-(33), Vfpj k+1 can be predicted with Vfpj k and ig k sensed by A/D conversion and the switching state Tpij k . For time-delay compensation, the FC voltage after two sampling periods Vfpj k+2 is predicted as (34) and (35).
Vfpj k+2 is determined using Tpij k+1 because ig k+1 and Vfpj k+1 are obtained using (11), (32), and (33). The magnitude of the voltage error between the command of the FC voltage, which is half of Vdc, avg k+1 and Vfpj k+2 is defined as the cost function Jfpj.
Assuming that the difference between the two switching states Kpj is expressed as (37)-(38), Jfpj is a positive quadratic function of Kpj k+1 . Therefore, the global minimum is the critical point at which the partial derivative becomes zero. However, Kpj has the value −1, 0, or 1 because the switching state can be selected as 0 or 1. Therefore, Kpj is determined as an integer adjacent to the critical point, and it is limited to −1 ≤ Kpj ≤ 1.  For example, in the case where leg A has priority and noj is 2, the possible noaj is 1; therefore, there is only one possible combination of switching states: {Ta1j, Ta2j} Table III shows how to determine the combination of the switching states of leg B when leg A has a priority. nobj is obtained using (30) and the switching state combinations that make nobj are listed as possible candidates to determine the switching states of the remaining leg. Using Kbj (39), an appropriate switching state combination was selected among the possible candidates. The case where leg B has priority is conducted in the same manner; however, it is skipped for the sake of brevity. Fig. 4 shows a flowchart of Layer I and Layer II in the proposed FCS-MPC. Fig. 4 (a) is a flowchart of Layer I, and it identifies noT k+1 that causes the error in the grid current to be small without comparison and only by calculation using pre-diction. In Layer II of Fig. 4 (b), the order of cells is determined through the sorting algorithm, and noj k+1 , which causes the error of the DC-link voltage to be small, the sequence for each cell can be obtained through calculation without comparison. Fig. 5 shows the flowchart of Layer Ⅲ in the proposed FCS-MPC; like other layers, Layer Ⅲ determines the switching state combination of the cell that  to the Layer Ⅲ Setting the Limitation Range noj,min, noj,max by   causes the error of the FC voltage to be small without comparison and only by calculation using prediction. Table IV lists the maximum number of calculations for the cost function based on the number of cells. In addition, the cost function is expressed as a directed weighted graph for a visual comparison of the maximum number of comparisons between the two methods. Figs. 6, 7, and 8 show each layer of the hierarchical FCS-MPC as a graphical structure. The nodes are represented as selectable candidates of noT, and the number of nodes is equal to the number of noT candidates. The weight is expressed as the cost function of the corresponding node. The direction proceeds from the start node S to the end node E, and the node with the smallest weight among the candidate nodes is selected using greedy selection when moving from node to node. Fig. 6 shows Layer I of FCS-MPC based on a hierarchical structure as a graph structure. Fig. 6 (a) shows a conventional FCS-MPC, which evaluates all candidates to find the optimized noT that minimizes the cost function gi defined in [28]. The number of evaluations of the cost function is (4N + 1) because the range of noT is [-2N, 2N]. However, the proposed method obtains the optimized noT using only one calculation (23), without comparison. Therefore, even if the number of unit cells increases, there is no significant difference in the execution time required for Layer I. Fig. 7 shows Layer II of the hierarchical FCS-MPC as a graph structure. The number of cases in which the sum of noj becomes zero (i.e., noT = 0) is the largest. Fig. 7 (a) shows that the noj combinations of all cells that result in noT = 0 in the conventional method. One combination that minimizes the cost function gVdc, which is defined in [28], is selected by comparing all combinations, and therefore, the number of noj combinations causes noT to increase exponentially with an increase in the number of cells. For example, the number of noj combinations is 19 for 3 cells; however, it increased to 381 for 5 cells and 8135 for 7 cells. Thus, it is not easy to expand the voltage because the number of calculations for the cost function increases exponentially during the voltage expansion. However, the proposed method determines the optimized noj for Vdcj control for one cell while making the sum of noj for all cells equal to noT. This is determined through calculations using a single-objective cost function. Therefore, it does not affect the performance of ig control, and only the (N-1) number of cost functions are evaluated without comparison. Therefore, the execution time does not increase dramatically because the number of calculations for the cost function increases linearly with the number of cells, regardless of the voltage expansion. Fig. 8 shows Layer III in the hierarchical FCS-MPC as a directed weighted graph. The maximum number of combinations of switching states is in the case of noj = 0. Fig.  8 (a) shows the conventional method, where a node is a combination of the four upper switching states of the j-th unit cell that results in noj = 0. In this case, all six candidate nodes are compared because there are six combinations, and the node that causes the cost function gVfcj, which is defined in [28], to become small is selected. Therefore, the total maximum number of calculations for the cost function is 6N because a maximum of six switching-state combinations are compared to determine the switching state of one cell. However, each node consists of two upper switching states because the proposed FCS-MPC in Fig. 8 (b) separates one cell into legs.  Finally, two calculations for the cost function are required for the switching state combination of one cell because one cost function is calculated for each leg. Thus, the total number of comparisons is 2N. Table IV shows that the maximum number of calculations for the cost function in the proposed FCS-MPC has a linear relationship with the number of cells, unlike the conventional exponential characteristics, and therefore, it is easy to expand the voltage level. Furthermore, the larger the voltage level, the greater is the effect of reducing the execution time compared with the conventional method.

A. SIMULATION RESULTS
A single-phase 9-cell CFCHB was simulated using PSIM to verify the proposed algorithm. The simulation parameters are the same as those listed in Table V. The grid frequency is 60 Hz, and the AC grid voltage is 13.2 kV using a single-phase in a three-phase 22.9 kV system. The DC-link voltage and FC voltage of each cell are controlled to 2.2 kV and 1.1 kV respectively. Fig. 9 shows the simulation waveform of the proposed algorithm in a steady state. Fig. 9 (a) shows vg and ig, and they coincide at same frequency so that the power factor can be controlled to 1. Fig. 9 (b)-(d) show the DC-link voltages of each cell. Vdcj are regulated by the command voltage of 2.2 kV, and the magnitude of voltage ripple is regulated within 5%. Fig. 9 (e) shows voT, and it is output by stacking the 1.1 kV unit voltage to 37 levels. Fig. 9 (f)-(h) show the FC voltages of each cell. Vfpj are controlled at 1.1 kV, which is half of Vdcj.

B. EXPERIMENTAL RESULTS
A 2 kW laboratory-scale single-phase 3-cell CFCHB prototype is shown in Fig. 10. The experimental stack is reduced to perform experiments in the laboratory, with a focus on verifying the effectiveness of the proposed algorithm. For the power semiconductor, a 1200 V, 10 A rated ROHM SCT2450KE SiC MOSFET was used, and the control algorithm is tested by programming the CPU 1 core of the TMS320F28377D. The turn-off signal of the power device is transferred from TMS320F28377D to the gate driver using a fiber-optic cable. The waveform is observed using a LeCroy Wavesurfer-4034HD oscilloscope. The experiment is conducted at the same sampling time of 100 μs and dead-time of 1 μs to compare the conventional and proposed methods. The parameters used in the experiment are listed in Table Ⅴ.   9. Simulation waveforms of the proposed algorithm in a steady state Fig. 11 shows the steady-state experimental waveform when the proposed FCS-MPC is applied. ig is synchronized to the frequency of vg and controlled with a power factor of 1. The DC-link voltages are controlled to 120 V, which is the command voltage; the flying capacitor voltages are controlled to half of that at 60 V, and therefore, the voT is output at 13 levels. Fig. 12 shows the steady-state waveforms obtained using the conventional and proposed methods. There is no significant difference in the DC-link voltage ripple or grid current when compared to that of the conventional method. Fig. 13 shows the experimental waveform under load variation from 160 Ω to 80 Ω. Fig. 13 (a) shows the waveform when the conventional method is applied, and Fig. 13 (b) shows the waveform when the proposed method is applied. When the load is changed, the DC-link voltages momentarily decrease and then return to the command voltage of 120 V and are regulated. Fig. 14 shows the experimental waveform change from 80 Ω to 160 Ω. When the load is changed, the DC -link voltages increase momentarily and then return to the command voltage of 120 V and are regulated. The proposed algorithm has a good control performance like that of the conventional method. Table VI and Fig. 15 show the maximum execution times of the hierarchical FCS-MPC measured by TMS320F28377D in the 3-cell CFCHB. The existing method takes 4.46 μs for comparing all 13 states; however, the proposed method requires only one calculation without a comparison computation, taking 0.96 μs. This is a reduction of 78.4%. Layer Ⅱ compares 19 states and takes 11.90 μs when using the conventional method; because the proposed method calculates sequentially after sorting, the cost function is calculated twice, which reduces the times by 38.8% to 7.28 μs. For the conventional method, Layer Ⅲ requires 12.80 μs because a maximum of 18 states are compared by comparing six of each of the three-unit cells. However, since the proposed method requires only two cost function calculations per unit cell, it takes 7.06 μs, which is a reduction of 44.8%. The proposed algorithm reduces the total execution time of hierarchical FCS-MPC by 47.5% compared to that of the conventional method; thus, the sampling frequency can be increased. In addition, Table Ⅳ indicates that, in the proposed method, the amount of computation increases linearly even when the number of cells increases; therefore, the effect of reducing the amount of computation is dramatically increased. To compare the current harmonics, THD was measured using a power analyzer PPA5530 from N4L, and is represented in Table Ⅶ. At the same sampling period of 100 μs, the THD was measured to be 2.63 % in the conventional method, and it was measured to be 2.64 % in the proposed method. Since the grid current THD is similar, it can be seen that the performance of the current control is not significantly different. Furthermore, since the proposed method can shorten the sampling period due to shorter execution time, the THD at the sampling period of 66 μs was measured to be 2.24%. Therefore, the proposed method can improve the grid current THD compared to the conventional method.

V. CONCLUSION
This study proposes a control method to reduce the amount of computation based on FCS-MPC in a grid-connected singlephase N-cell CFCHB. The prediction models of the grid current, DC-link voltage, and FC voltage are derived through the mathematical modeling of the CFCHB to predict the values at a future sampling instance. The control algorithm is designed with a three-layer hierarchical structure of the FCS-MPC, and the optimal objectives for regulating the grid current, DC-link voltage of each cell, and FC voltage are determined in each step without comparison computation. The optimal value is determined only by calculation and without a comparison operation by composing the cost function of each step as a single objective. Therefore, the computational burden is significantly reduced compared to the conventional method without affecting the control performance; thus, the calculation time can be shortened and the sampling frequency can be increased. Compared to the conventional method, the computational burden is significantly reduced, the execution time can be shortened, and the sampling frequency can be increased. It is easy to apply the proposed method to highvoltage applications and digital systems because the computational burden increases linearly even when the number of cells increases. The effectiveness of the proposed algorithm is verified through a 9-cell CFCHB simulation and a 3-cell CFCHB experiment.