Hybrid Three-Phase Transformer-Based Multilevel Inverter with Reduced Component Count

This paper proposes a novel three-phase transformer-based multilevel inverter (MLI) topology to maximize the output voltage levels for high-power high-voltage applications while reducing component counts as compared to its transformer-based counterparts. The proposed hybrid topology is formed by connecting a three-level T-type module with full H-bridge cells through single-phase transformers. The T-type module is fixed while the full H-bridge cell can be repeated for enlarging the output voltage levels without increasing the voltage stress on switches. Key features of the proposed topology include low part count, capacitor-free, diode-free, voltage boosting, simple control, and modularity. Within the framework, a simple low-frequency pulse width modulation (LFPWM) switching scheme is used to control the output voltage, and the working principle is detailed for seven-, nine-, and N-level operation. The operability and performance of the proposed topology are numerically verified and experimentally validated at different loads. Moreover, its conversion efficiency is experimentally examined. Finally, a comparative study with existing transformer-based MLI circuits is conducted to prove its key merits.


I. INTRODUCTION
Multilevel inverters (MLIs) concept has become a mature technology, being deployed in medium-and high-power DC-AC conversions. The MLIs have gained popularity due to their unique merits of producing high voltages at high quality, namely low THD value, low dv/dt, low electromagnetic interference (EMI), high conversion efficiency, voltage scalability, and reliability while using low-voltage semiconductor devices and low switching frequency [1][2][3][4][5]. The conventional MLIs include three topologies, being known as cascaded H-bridge (CHB) [6], neutral point clamped (NPC) [7,8], and flying capacitor (FC) [9,10]. The CHB, NPC, and FC MLIs can produce output voltages with N levels, requiring huge counts of DC sources, clamping diodes, and capacitors, respectively. For example, producing nine-level three-phase voltages requires 48 switches, twelve DC sources in CHB inverters, 168 clamping diodes in NPC inverters, and 92 capacitors in FC inverters, increasing inverter size, cost, losses, failure rate, and complexity. As argued in [11], increasing the number of voltage levels is a desirable necessity to enhance the MLI performance. Therefore, many MLIs are intensively developed to increase the output voltage levels with reduced component counts [11][12][13][14][15][16][17][18][19][20][21][22]. Among them, transformer-based MLIs have received great attention with key features of reducing DC source count and maximizing the output voltage [18][19][20][21][22]. Their structure, merits and demerits are briefly discussed hereafter.
The cascaded-transformer multilevel inverter (CTMI) in [18] comprises two stages: voltage generator stage (VGS) and polarity changer stage (PCS). Half-bridge modules are the building block in the VGS, thus adding more half-bridge modules enlarges the voltage level count. The PCS employs full H-bridges to bipolarize the generated unipolar multilevel voltages from the VGS stage. Producing three-phase voltages requires three single-phase transformers to couple the PCS outputs with the load. This CTMI requires three power transformers, 3N+9 switches, and 0.5N-0.5 DC voltage sources for generating N voltage levels. It can eliminate flying capacitors, clamping diodes and reduce the DC source count as compared to FC, NPC, and CHB inverters, respectively. However, using three H-bridge cells to produce bipolar voltages is a conspicuous drawback because of linking the switch blocking voltage to the output voltage level count. For example, the total standing voltage of PCS switches is 6VDC (N-1), where VDC is the voltage rating of each DC source in the DC-link, limiting the modularity of this CTMI and other associated features such as THD and dv/dt.
To tackle the drawbacks of the CTMI in [18], a hybrid ninelevel inverter (H9LI) is proposed in [19], which can produce bipolar voltages without a polarity changer with a lower part count. It employs twenty-four switches, nine capacitors, six power diodes, one DC source, and three single-phase transformers. It saves twelve switches and three DC sources as compared to the CTMI when producing nine-level voltages. However, the reduction of DC sources and switches requires higher numbers of power diodes and capacitors, decreasing the inverter efficiency, reliability, and life span. Further, during startup, the H9LI requires pre-charging circuits for three capacitors, as suggested by the authors in [19].
To reduce or eliminate capacitors in the H9LI, two transformer-based topologies were presented in [21,22]. The modified active-neutral point-clamped (MANPC) topology in [21] uses thirty switches, five capacitors, three single-phase transformers, and one DC source to produce nine voltage levels. The MANPC topology has a lower part count than H9LI in [19]. Both circuits use the same count of transformers and DC sources, but MANPC topology eliminates the six power diodes in H9LI. Further, it uses only five capacitors instead of nine in H9LI, simplifying control algorithms and improving inverter reliability. However, using additional six switches is a disadvantage of the MANPC as compared to the H9LI. A transformer-based cascaded H-bridge (TB-CHB) topology in [22] can reduce the switch count to only twentyfour, being the same switch count as H9LI, and lower than MANPC by six switches. Furthermore, it can remove all capacitors in MANPC and H9LI inverters. For constructing each inverter leg in the TB-CHB topology, several full Hbridge cells sharing a single DC-link are cascaded through single-phase transformers. For a nine-level operation, it requires one DC source, twenty-four switches, and six singlephase transformers. Modularity, capacitor-free, diode-free, and reduced switch count are its key merits. However, using six transformers is the main drawback, increasing the size and cost of the inverter.
To address the disadvantages of the aforementioned transformer-based inverters, namely high counts of DC sources in CTMI [18], power diodes and capacitors in H9LI [19], switches in MANPC [21], or transformers in TB-CHB [22], this study proposes a novel three-phase transformerbased MLI topology, which can reduce the total part count while preserving the key features of being capacitors-, diode-free, and low counts of DC sources, switches, and transformers. Further, the proposed circuit allows for increasing the voltage level count without increasing the voltage stress across the switches, being a good option for high-power high-voltage applications. This MLI topology is proposed as part of work carried out for the research in [23]. Section II details the working principle, symmetrical and asymmetrical operation modes, generalized configuration of the proposed topology, and suggests its applications. A switching modulation scheme based on low-frequency pulse width modulation (LFPWM) is given in Section III. Section IV presents and discusses the simulation and experimental verification of the proposed inverter. A comparative assessment between the proposed topology and recently developed transformer-based inverters is drawn in Section V. Finally, Section VI concludes the finding of this paper.

A. CIRCUIT CONFIGURATION
The circuit configuration of the proposed transformer-based inverter is shown in Fig. 1. It is a hybrid three-phase topology, being formed by connecting three T-type legs to three Hbridge inverters through three single-phase transformers. The proposed topology consists of two DC sources (E1 and E2), three transformers (TA, TB, and TC), and twenty-four switches (S1-S24). The twenty-four switches are used to implement eighteen unidirectional switches and three bidirectional switches. The proposed topology does not require any clamping diodes or flying capacitors in its operation. It can produce different voltage level counts N, according to the selected transformer turns ratio β. For example, it produces seven voltage levels and nine voltage levels when selecting β to be 1 and 1.5, respectively. The proposed topology configuration keeps the maximum blocking voltage of the switches either below or equal to E, where E is the input DClink voltage. The switches S3, S4, S11, S12, S19, and S20 have a voltage stress of 0.5E. Alternatively, the switches S1, S2, S5-S10, S13-S18, and S21-S24 withstand a voltage stress of E.

B. OPERATING CONCEPT
The operating concept can be explained based on the pole voltage generation. The pole voltages are the voltage differences between the three load points (A, B, and C) and the reference point 0, being labelled as VA0, VB0, and VC0, respectively. Considering VA0 as an example, it is synthesized by adding two voltage components: V0 and V1, as shown in (1) and Fig. 2. The V0 is the voltage between the midpoint of the T-type leg and the reference point 0, and V1 is the secondary voltage of transformer TA. Both two voltage components can have three different voltage levels, V0 has 0.5E, 0, and -0.5E, and V1 has three levels of βE, 0, and -βE.
The transformer turns ratio β can have different values: A) Case A, β =1, producing three voltage levels of E, 0, and -E in the voltage component V1. B) Case B, β =1.5, producing three voltage levels of 1.5E, 0, and -1.5E in V1. Although both cases keep producing the same number of voltage levels, the maximum reachable voltage in the case B is higher than that in the case A. Accordingly, the pole voltage can have different voltage level counts: seven levels in the case A (i.e., 1.5E, E, 0.5E, 0, -0.5E, -E, and -1.5E) and nine levels for the case B (i.e., 2E, 1.5E, E, 0.5E, 0, -0.5E, -E, -1.5E, and -2E). Fig. 3 shows seven different operating modes of the proposed topology to produce seven voltage levels in the pole voltage VA0 when β is equal to 1. For instance, in Fig. 3 (a), mode I describes the required ON/OFF switches for producing 1.5E in VA0, in which the switches S1, S4, S5, and S8 must be ON while S2, S3, S6, and S7 are OFF. The remaining six voltage levels can be achieved by following the operating modes II to VII, as shown in Figs. 3(b) to (g), respectively. It is worth noting that the mentioned operating modes are selected to produce the targeted voltage level without causing a shortcircuit across the input DC sources. Therefore, some combination of switches cannot be set ON. For example, in phase leg A, the following combinations are not used in the modulation control of the proposed topology: (S1, S2), (S1, S3, S4), (S2, S3, S4), (S5, S6), and (S7, S8).

C. N-LEVEL CONFIGURATION
The proposed topology can be extended to produce N voltage levels by adding more H-bridge cells in each phase leg, being connected through transformers, as shown in Fig. 4. The blocking voltage of the switches is not a function of the voltage levels count, so increasing the voltage level count does not increase the voltage stress across the switches. All H-bridge cells contribute to the pole voltage. For example, the pole voltage VA0 is synthesised by adding all the cell voltages V1, V2, …, and Vn to the base voltage V0 as expressed in (2).

III. MODULATION STRATEGY
The low-frequency pulse width modulation (LFPWM) scheme is selected to control the proposed topology output voltage due to its simplicity. However, other modulation schemes can be used as well, and selecting the best modulation is outside the scope of this study. Table I lists the switching states when β is 1, generating seven voltage levels in the pole voltage. Alternatively, nine voltage levels are generated when β is 1.5, as described in Table II. The LFPWM scheme is based on these two tables. Moreover, Tables I and II list the switching states of leg-A switches (S1-S8) and the corresponding output voltages V0, V1, and VA0. Fig. 5 shows the generation of the switching signals for the leg-A switches when β is 1. To produce the seven-level pole voltage as shown in the last trace of Fig. 5, a sinusoidal reference signal VrefA and six offset signals (±R1, ±R2, and ±R3) are required. The reference signal can be varied from 0 to the maximum of VP, while the offset signals can be expressed as in (9) [16].
where θ1-θ3 are the transition angles between voltage levels as marked in the pole voltage waveform in Fig. 5. These transition angles can be calculated using (10) [16]. Further, equation (10) can be used for computing the transition angles of any number of voltage level produced by the N-level configuration in Fig. 4. In other words, Fig. 5 can be extended for producing the required switching pulses for N voltage levels by using (10) to determine N-1 offset signals (±R1, ±R2, ±R3, ….and ±R(N-1)/2).
Six primary signals (X1-X6) are derived when comparing the reference signal VrefA with six offset signals. These six primary signals are the inputs for the Boolean operators in (11)-(14), being used to achieve the switching states in Table I. 1 3     , S S X = (14) The required switching signals for producing nine voltage levels in the pole voltages can be generated by using the same procedures as described in Fig. 5. In this case, eight offset signals are used instead of six. Comparing the eight offset signals and the modulation signals produces eight primary signals Y1-Y8. The adequate switching signals are derived by applying the Boolean operations in (15)-(18) on Y1-Y8 signals. In (11)-(18), symbols ''+'' and ''X'' correspond to the logical operators ''OR'' and ''AND'', respectively.

IV. SIMULATION AND EXPERIMENTAL VALIDATION
This section presents a numerical verification and experimental validation of the proposed topology. The circuit configuration in Fig. 1 is used to evaluate the circuit operation, and Table III lists the used system parameters in simulation and experimental tests. Fig. 6 shows the experimental setup, consisting of two programmable DC voltage sources (Chroma, 62024P-100-50), one DC source for control circuits (Rohde & Schwarz, HMP4040), three single-phase transformers (Triad Magnetics, VPM240-20800), dSPACE MicroLabBox controller, current and voltage probes, digital oscilloscope (Yokogawa, DL850EV), resistive-inductive loads, and the inverter prototype. The inverter prototype is constructed using twenty-four IGBT modules (SEMIKRON, SKM300GA12E4) associated with gate-driver boards (SEMIKRON, SKHI 10/12 R).

A. SIMULATION RESULTS
The transformer turns ratio (β) affects the output voltage level count. The proposed inverter can produce seven and nine voltage levels at β of 1 and 1.     (a) pole voltage VA0 synthesizing. (b) pole voltages VA0, VB0, and VC0. (c) line voltages VAB, VBC, and VCA. show the waveforms of VAB, VAN, and IAN when feeding power to a resistive-inductive (R-L) load (R= 50 Ω and L= 100 mH).

B. EXPERIMENTAL RESULTS
The simulation findings are experimentally validated by the in-house inverter porotype in Fig. 6. The proposed topology is tested with one case of β (β =1) since we do not have transformers with a turn ratio of 1.5. All the remaining parameters are kept as same as in the simulation verifications. Fig. 11(a) presents the leg-A pole voltage VA0 and its two voltage components V0 and V1. By setting 100 V as the input voltage of the inverter (E), the waveforms of V0 and V1 have voltages of (0 and ±50 V) and (0 and ±100 V), respectively, resulting in a seven-level pole voltage as shown in the first trace of Fig. 11(a). Further, Fig. 11(b) shows the seven-level pole voltages of the three inverter legs VA0, VB0, and VC0. These pole voltages having phase shifts of 120° produce three balanced line voltages of thirteen levels, as depicted in Fig.  11(c). Figs. 12(a) and (b) provide the obtained results when connecting resistive and resistive-inductive loads to the inverter outputs, respectively. The experimental results well validate and confirm the simulations and theoretical analysis of the proposed topology.
The efficiency of the proposed topology is measured experimentally. Fig. 13 shows the obtained values at different output powers while keeping all other system parameters constant. The efficiency increases from 92.69% to 97.76% when increasing the load power from 0.2 KW to 1.5 KW in a step of 0.1 KW. Using low frequencies (≤ 150 Hz) in the employed switching scheme reduces switching losses and increases the overall efficiency.

V. COMPARATIVE ASSESSMENT OF THE PROPOSED TOPOLOGY
The proposed topology is compared to recent developed transformer-based MLIs at nine-level operation in this section. The proposed topology aims to maximize the output voltage level count while reducing the required components. Therefore, a quantitative comparison is carried out between the transformer-based counterparts and the proposed topology based on component counts: namely DC voltage source count (NDC), transformer count (NTrf), switch count (NSW), power diode count (ND), and capacitor count (NCap). For a fair comparison, the following aspects are considered: A) generating nine levels in the three pole voltages. B) [    Efficiency at different output powers adopting the three-phase configurations. C) equalizing the total voltage of a single DC-link to E volt, e.g., if a topology TX has a shared DC-link among its three-phase legs, the whole voltage of the DC-link is assumed to be E. D) counting each part based on its primary unit structure, e.g., a unidirectional switch is the counting unit for bidirectional switching devices, and a single-phase transformer is the counting unit for threephase transformers. The proposed inverter and topologies T1-T4 use the same transformer count, but the proposed inverter has some salient advantages: lowering twelve switches and two DC sources as compared to T1, eliminating six power diodes and nine capacitors as compared to T2, removing six switches and nine capacitors as compared to T3, reducing six switches and five capacitors as compared to T4. Both T5 and the proposed topology are capacitor-and diode-free circuits, but T5 require one DC source while the proposed topology requires two DC sources. However, the proposed topology can save three transformers as compared to the topology T5. It is worth mentioning that the two DC sources in the proposed topology have a 0.5E voltage rating, while the DC source in the topology T5 has a voltage rating of E volt. Table IV confirms that the proposed topology employs the lowest component count among the compared transformer-based MLI topologies [23].

VI. CONCLUSION
This paper proposes a novel three-phase transformer-based nine-level inverter with a reduced component count, having the key features of being capacitor-, diode-free, and low counts of DC sources, switches, and transformers. The proposed circuit can increase the voltage level count to N levels without increasing the voltage stress across the switches, being a promising candidate for high-power highvoltage applications. Further, it has beneficial features of modularity, voltage boosting and simple structure. The working principle of the proposed topology was theoretically demonstrated, numerically verified, and experimentally validated through the in-house setup. Finally, the advantages of the proposed topology, in terms of component counts, are highlighted by a comparative study.