Multiphase Interleaved Converter Based on Cascaded Non-Inverting Buck-Boost Converter

This paper introduces an interleaved buck-boost converter with reduced power electronics devices count in comparison with the conventional topology. The proposed converter consists of a single buck converter followed by $n$ parallel interleaved boost converters. The buck switch is gated only if any of the boost switches is gated. In addition to the reduced switches count, the proposed converter offers the following advantages, soft start-up and shutdown capabilities. In addition, the buck stage gives the ability to protect the power electronic devices and to isolate the supply during load failure or overload. Moreover, the proposed converter performs as an interleaved boost converter for high voltage gain requirements with the same switching scheme. Furthermore, it offers fast dynamic performance with smooth transition from the buck mode to the boost mode. This paper investigates the eight different operating zones of the proposed three-phase interleaved buck-boost converter for non-overlapping gate signals operation. The detailed analysis and zones of operation are presented and experimentally validated. In addition, a simple control system is presented to operate the proposed converter as dc-dc converter or ac-dc converter. More study cases are carried out to evaluate the different capabilities of the proposed converter.


I. INTRODUCTION
Dc-dc power electronics converters are widely used in many applications such as renewable energy sources, electric vehicles, uninterruptible power supplies, and microgrids. The buck-boost converter can increase or decrease the magnitude of the input voltage with simple circuit and control loops [1]- [4]. However, it has a limited voltage gain with inverted output voltage [5]. To increase the voltage gain, the buck-boost converter was proposed to operate under discontinues conduction mode (DCM) [6], [7]. The operation under DCM reduces the size of converter passive elements and improves the dynamic performance, but on the account of increased current stress of power electronics devices. In [8], two different topologies to reduce current stress are presented. In the first topology, two buck-boost converters inductors are charged in series and connected in parallel The associate editor coordinating the review of this manuscript and approving it for publication was Tariq Masood . during the discharging in contrast to the second topology, where the inductors are connected in parallel during charging and discharging. It was concluded that the second topology succeeded to reduce the current stress on power electronics devices to half.
In the interleaving converters, two or more converters are connected in parallel, which can increase the converter rated output power as well as the output voltage. In addition, current ripple is reduced since the inductors currents, of different phases of the interleaved converter, charge a shared capacitor. Moreover, the current stress is distributed on power electronics devices of different phases that tend to reduction on the interleaved converter power losses [9]- [11]. Another advantage of interleaved converters is the reduction of the size and weight of passive components due to increase in the ripple frequency [12], [13]. For two-phase interleaved converter, the ripple frequency is double the switching frequency [14]. To increase the power density, an interphase transformer is used with a common inductor to double the VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ ripple frequency [9]. The coupled inductor based interleaving converter can operates in continues conduction mode (CCM) [15], [16]. However, the operation under CCM increases the weight of the converter. In [17], [18], an interleaved converter with zero voltage switching (ZVS) capability is presented. One main disadvantage of this topology is that it requires an additional inductor to achieve ZVS which operates at CCM that leads to increase the weight and footprint size of the converter. For the electric vehicles and PV application the size and the weight of the converter is considered. Therefore, it is preferred to operate at DCM [19]. When the interleaved converter operates under DCM, it has a higher number of operating modes during one switching cycle in comparison with CCM operation. A comprehensive analysis of the interleaved boost converter including modes of operation, voltage gain, and inductor current ripple are presented in [20], [21]. The dual interleaved buck-boost converter, which operates under DCM, was presented in [22]. However, increased number of magnetics is the main disadvantages of this topology.
The conventional interleaved buck-boost converter has a simple circuit structure, but the voltage stress on the power electronics devices is high [23], [24]. The cascaded noninverting buck-boost converter (CNIBBC) has the following advantages: reduced voltage stress and non-inverted output voltage polarity [25]. In [6], [26], three CNIBBC are connected in parallel and was operating under DCM. However, the three converters are not operating under interleaved manner since the gate signals of each CNIBBC were not phase-shifted. In turn, the blocking diode of the boost units inherits high current stress since it carries all the discharging current. Two interleaved CNIBBC are connected in parallel to boost the PV input voltage for the grid-connected inverter [27]. This paper proposed reduced switches count non-inverting interleaved buck-boost converter shown in Fig 1. The proposed topology consists of a single buck converter cascaded with n parallel-interleaved boost converters. The proposed converter has a reduced switches count compared to the interleaved parallel CNIBBC topology presented in [28], [29]. One of the main advantages of the CNIBBC topology is that the voltage stress on the power electronics switches is splitted where the buck switch faces the supply voltage stress and the boost switches face the load voltage stress [1]. In [30]- [33], the proposed interleaved buck-boost converters are based on single-switch buck-boost topology, where the voltage stress on the power electronics switches equals to the supply voltage plus the load voltage. This disadvantage limits the maximum output voltage that can be reached by the converter. Unlike the interleaved converters shown in [33], [34], that are based on coupled inductors which decrease the flexibility in extending the number of phases, the proposed interleaved converter has a simple design, easy to increase or decrease the number of the phase, and the number of phases can be odd or even. The above comparison is summarized in the Table 1.
The paper is organized as follows. Section II introduces the proposed interleaved buck-boost converter. The detailed analysis and zones of operation are presented are presented in Sections III. Section IV presents a control system to operate the proposed interleaved buck-boost converter as dc-dc converter or ac-dc converter. The experimental evaluation of the proposed system is demonstrated in section V. Finally, the article is concluded in Section VI. Fig. 1(a) shows the proposed three-phase interleaved buckboost converter. It consists of a single buck converter (S 0 and D 0 ) and three interleaved parallel connected boost converters (L 1 to L 3 , S 1 to S 3 , and D 1 to D 3 ). The three boost converter 42498 VOLUME 10, 2022 switches (S 1 to S 3 ) operates with the same duty cycle, but each gate signal is shifted by 120 • from its preceding, as shown in Fig. 1(b). The switch S 0 is turned-on simultaneously with any of S 1 to S 3 . Therefore, the gate signal of the buck converter switch S 0 is obtained through OR logicgate with input signals S 1 to S 3 . As a result, the switching frequency of the buck converter is triple that of the boost converters. If the modulation index is higher than 1/n, the proposed buck switch is turned-on continuously and the proposed interleaved converter will operate as a conventional interleaved boost converter without any adaptation in the control loop or switching pattern. This feature makes the converter has a high voltage gain with continuous input current. Moreover, the single buck switch adds soft startup and shutdown capabilities to the proposed interleaved topology.

II. PROPOSED INTERLEAVED CONVERTER
For non-overlapping gate signals operation, the duty cycle k must be lower than 1/3 as indicated in Fig. 1(b). If the duty cycle exceeds 1/3, S 0 becomes continuously conducting and the proposed converter operates as interleaved boost converter. This action is suitable for applications that require a high dc-voltage gain. Therefore, the proposed interleaved buck-boost converter has the capabilities of soft start-up and soft shutdown. As a result, the performance of the proposed interleaved buck-boost converter outdoes the conventional interleaved boost converter.

III. OPERATION ZONES
There are many zones of operations for the proposed interleaved converter. In this paper, the non-overlapping gate signals operation is considered. The phase inductors are assumed having the same inductance. For three-phase interleaved buck-boost converter, Fig. 2 illustrates the eight zones of operation which are determined by the converter parameters such as inductance (L), switching frequency (f), duty ratio (k), and the load resistance (R), where x = R/Lf. The following subsections present the gain equation for each operating zone and the boundaries equations with the other zones. The windings resistances are neglected and the switches are assumed ideal. These assumptions are accepted for non-overlapping gating signal operation as each inductor is energized only for one-third of the switching period.

A. ZONE 1
The on-mode and off-mode circuits for zones 1, 2, 3, and 4 are shown in Fig. 3(a) and Fig. 3(b), respectively. For zone 1, the current of the phase 1 inductor, i 1 , is traced in Fig. 3(c). The differential equations describing the on-mode circuit can be solved to obtain the peak currents, I 1 and I x , as follows: where V s and V o are the supply and output voltages, respectively, and I 1 is the global peak current for DCMs. During this zone, the proposed interleaved converter behaves as a buck converter since the inductors are always charging during on-mode. This action can be revealed from (2), as I x is a positive value. Solving the off-mode circuit, the intervals δ 1,1 and δ 2,1 are estimated from, where G 1 = V o / V s is the voltage gain of the converter for zone 1.
Considering the on-mode circuit, the voltage gain can be estimated by calculating the average supply current using (1) and (2), If the current increases, δ 1,1 increases until it reaches (1−k)/3f , and operation in Zone 2, Fig. 3(d), is initiated. The boundary condition between zones 1 and 2 in the k-x plane shown in Fig. 2, K 12 , is obtained by substituting (5) in (3) at δ 1,1 = (1 − k) 3f as follows: The phase 1 inductor current waveform of zone 2 is shown in Fig. 3(d). Solving the on-mode and off-mode circuits, the different peak currents and time intervals are calculated as follows: Similar to zone 1, the proposed converter works in buck mode during zone 2 as (9) reveals.
Referring to the on-mode circuit and calculating the average supply current using (1) and (7) to (9), the voltage gain is expressed by: If the current increases, δ 1,2 increases until it reaches (1k)/3f , and operation in zone 3, Figs. 3(e) and (f), is initiated. At this condition, the boundary between zones 2 and 3, K 23 , shown in Fig. 2, is derived by substituting (12) in (10), Analyzing the on-mode and off-mode circuits, the different peak currents and time interval δ 1,3 are formulated as follows: The voltage gain is given by, Inspecting (17), the condition for buck operation, in zone 3, is given by the following inequality, Continuous Current Mode (CCM) is initiated if the load is further increased, which is indicated by zone 4 in Fig. 3(g). The boundary condition between zones 3 and 4, K 34 , is obtained by substituting δ 1,3 = (1 − k)/3f in (16), It is worth mentioned that (20) gives the value of critical inductance L C which is the minimum inductance that results in in CCM operation, D. ZONE 4 As mentioned in the previous subsection, zone 4 represents the CCM of the proposed interleaved converter as illustrated in Fig. 3(g). The peak current and the voltage gain are formulated as follows: E. ZONE 5 Fig. 4(a) and (b) illustrates the on-mode and off-mode circuits of the proposed interleaved converter during operation in zone 5. The inductor current of phase 1 is traced in Fig. 4(c). It can be noticed that the slope of the current waveform is negative during the off-mode. This action indicates that V s < V o which reveals boost operation. The differential peak currents and the time interval δ 5 can be obtained as follows: With the aid of the above equations and the on mode circuit, the voltage gain can be expressed by: It can be noticed that if δ 5 = k/3f , operation in zone 3 is commenced and the boundary condition between zones 3 and 5, K 35 , is obtained by solving (24) and (25), F. ZONE 6 It the factor x is increased due to increase in load resistance, for example, the operation of the proposed interleaved converter is transferred from zone 5 to zone 6, as indicated in Fig. 2. For zone 6, the on-mode and off-mode circuits of the converter and the inductor current of phase 1 are shown in Fig. 4(d), (e), and (f), respectively. Similar to zone 5, boost operation is continued in zone 6. The peak currents and the time interval δ 6 are given by:  As a result, the voltage gain can be obtained, If the current is increased until δ 6 = (1 − k)/3f , operation in zone 5 is started and the boundary condition between zones 5 and 6, K 56 , is formulated by substituting (27) in (26), By inspecting the inductor current of zones 2 and 6, the boundary condition K 26 can be derived by nulling (9), I 4,2 = 0. Another way to find K 26 is by equating the voltage gain of zone 2 (buck) or zone 6 (boost) to unity. Both methods give the following expression, G. ZONE 7 It the factor x is further increased, the operation of the proposed converter is transferred from zone 6 to zone 7, as demonstrated in Fig. 2. The on-mode and off-mode circuits of the converter during operation in zone 7 are shown in Fig. 5(a) and (b), respectively, while the inductor current of phase 1 is traced in Fig. 5(c). Boost operation can be observed as the slope of the current waveform is negative during the off-mode. The peak currents and the time interval δ 7 are calculated as follows: Accordingly, the voltage gain is given by, If δ 7 = k/3f , operation in zone 6 is initiated and the boundary condition between zones 6 and 7, K 67 , is obtained by solving (30) and (31),

H. ZONE 8
Zone 8 is the last zone for the non-overlapping gate signals operation of the proposed interleaved converter. At light loads, transfer from either zone 7 or zone 1 to zone 8 takes place as indicated in Fig. 2. The on-mode and off-mode circuits of the converter and the inductor current of phase 1 during operation in zone 8 are shown in Fig. 5(d), (e), and (f), respectively. Similar to zones 4, 5, 6, and 7, boost operation is continued in zone 8. The time interval δ 8 is given by: As a result, the voltage gain is obtained from: , operation in zone 7 is underway. Substituting (34) in (33), the boundary condition between zones 7 and 8, K 78 , is obtained, Finally, the boundary condition K 18 can be estimated by equating the voltage gain of zone 1 (buck) or zone 8 (boost) to unity which results in, At no load, x → ∞. According to (35) and (36), K 78 = 1 and K 18 = 0, respectively. This action reveals that the proposed interleaved converter operates at zone 8 when light load is connected. VOLUME 10, 2022   Referring to (1) and (21), the ratio between peak current and average load current, I p , can be expressed as follows: Considering the equations of voltage gain and boundary limits for each zone, Fig. 6 shows the voltage gain surface against the load factor and duty ratio. As expected, the behavior becomes highly nonlinear when the load factor increases. The surface of the peak current ratio, given by (37), is portrayed in Fig. 7. It is obvious that the maximum value of the peak current ratio occurs at k = 0.5. For heavy loads, the maximum value of the peak current ratio shifts toward k → 0.

IV. PROPOSED CONTROL SYSTEM
In Fig. 8(a), a rectifier with LC filter is added to the proposed interleaved dc/dc converter to work as an ac/dc converter. A cascade control system is illustrated in Fig. 8(b) which is suitable for dc/dc or ac/dc operation of the proposed converter. The outer loop regulates the output dc voltage utilizing a proportional-integral (PI) controller by setting the reference current for the inner loop. For ac/dc operation, the selector is switched to position A where the reference current is multiplied by the absolute value of a unity sinusoidal waveform in-phase with the supply voltage to guarantee unity power factor operation. For dc/dc operation, the selector is switched to position B. A current limiter is implemented to prevent overloading the converter. A PI controller is used for the inner loop to control the supply current, i s , by setting the duty cycle for the boost switches, S 1 , S 2 , and S 3 . Consequently, the gating signals for the boost switches are obtained by comparing the duty cycle with three carrier signals shifted by 120 • . Finally, the gating signal for the buck switch, S 0 , is determined as described in section II.
A digital low pass filter (LPF) is implemented to gradually increase the reference signal of the output voltage from zero to the set value to allow the proposed interleaved converter to start at buck mode, zone 1, 2, or 3 under the condition of (18). This action prevents inrush current at starting which results due to the initial charging the output capacitor. This inherent soft-stating capability is one of the advantages 42502 VOLUME 10, 2022 of the proposed interleaved buck-boost converter over the interleaved boost converter.

V. EXPERIMENTAL RESULTS
The experimental section is divided into three subsections. The first subsection is dedicated to evaluate the analyses and the different operation zones of the proposed interleaved buck-boost converter. The second subsection investigates dynamic performance of the proposed converter when works as a dc-dc converter connected to either dc-load or dc-bus. The third subsection illustrates the performance of the proposed converter for ac-dc conversion. Fig. 9 shows the laboratory prototype and the parameters are given in Table 2.

A. OPEN LOOP PERFORMANCE
The currents of the buck switch and three phase coils during operations in different zones of the proposed interleaved converter are demonstrated in Fig. 10. The eight zones of operations, which are analyzed in Section III, are recognized. For zone 3, the buck operation is illustrated in Fig. 10(c), while the unity gain operation is shown in Fig. 10(d) where the duty ratio is set according to (18). The theoretical and experimental values of the output voltage for each case of Fig. 10 are presented in Table 3. The negligible errors between theoretical and experimental values are due to the internal coil resistance per phase. As expected, the effect of the internal coil resistance on the voltage gain can be ignored for non-overlap gate signal operation of the proposed interleaved converter. These results verify the analysis of the proposed interleaved converter. Fig. 11 illustrates the dynamic performance of the proposed interleaved buck-boost converter when it is operated as a dc-dc converter. Initially, the reference output voltage is set at 150V. Fig. 11(a) demonstrates the soft start-up VOLUME 10, 2022   Fig. 10.

B. DC-DC CONVERTER PERFORMANCE
capability of the proposed converter where the output voltage is gradually increasing from zero to 150V without inrush current, as discussed in section IV. In addition, the load is increased in four steps from 100 to 60 where the first three steps last for 100ms. Tight voltage regulation with negligible oscillations even during step load changes is demonstrated in Fig. 11(a). Fig. 11(b) shows the three coils currents and the input supply current at 100 load where the duty cycle is higher than unity. Since the required voltage gain, 150V/48V, is higher than the surface given in Fig. 6, the duty cycle is expected to be higher than unity and the overlap gate signals operation is triggered. As a result, the buck-switch is turned-on and the input supply current becomes continues as indicated in Fig. 11(b). This result shows one of the features of the proposed converter, which is the operation as interleaved boost-converter for high voltage gain. To illustrate the behavior of the proposed converter under overload or load failure, Fig 11(c) shows the output current and voltage when the load is suddenly changed from 100 to 10 . It can be observed that the current limiter succeeds to limit the converter output current to it rated value, 2.5A, and protects the converter from damage. It is worth mentioning that the current spike at the overload instant results from discharging the output capacitor from the reference value, 150V, to 25V, which is corresponding to the overload resistance and current limiter setting. The efficiency of the proposed converter at different output power levels is calculated and shown in Fig. 12. It can be observed that the proposed converter has a high operating efficiency. However, the efficiency starts to drop when the output power exceeds 310W, since the  inductors current becomes greater than its rated value and saturation is initiated. Fig. 13 investigates the performance of the proposed converter when it is connected to a dc-bus of 150V to emulate the microgrids applications. During this test, the outer voltage control loop has been disabled. The reference current delivered to the dc-bus is suddenly increased from 0 to 1A and then to 2.4A. It can be observed that the proposed controller succeeds to follow the demand signal.

C. AC-DC CONVERTER PERFORMANCE
In this subsection, the proposed interleaved converter operates as an ac-dc converter. The LC filter used is 3mH and 10uF, respectively and the ac supply voltage is 50V. The supply and output voltages and currents are illustrated in Fig. 14(a). At the start-up, the reference output voltage is gradually increased, as explained in section IV, from 0 to the set point 150V. It is obvious that the proposed converter succeeds to perform a soft start-up while the supply current 42504 VOLUME 10, 2022 is sinusoidal and in-phase with the supply voltage. During start-up, the output voltage increases in different steps, which are governed by the gain characteristics of different zones. Successful smooth transitions between different zones are illustrated. Fig. 14(b) depicts the dynamic performance when the load resistance is suddenly changed from 150 to 75 . It can be concluded that the proposed system succeeds to overcome the load dynamics with minimum oscillation and keeps the supply current at sinusoidal shape with unity power factor.

VI. CONCLUSION
This paper presents a reduced switch count interleaved buckboost topology for dc-dc and ac-dc conversion systems. The buck stage offers many capabilities for the proposed converter such as soft start-up without inrush current even during overload or load failure conditions. The paper investigates the characteristics of the proposed buck-boost interleaved converter during non-overlapping gate signals operation. It has been found that the proposed converter works in boost mode during five zones, in buck mode during two zones, and buck-boost mode in one zone, Z3. For each zone, the voltage gain and peak current are derived and traced against duty cycle, converter parameters, and load resistance. Moreover, the boundary conditions between different zones are found. An experimental prototype is developed to verify the analysis and capabilities of the proposed interleaved buckboost converter. The results validate the currents waveforms for each operating zone and the gain equations. It was found that the efficiency of the proposed converter reaches 98.5%. In addition, the soft start-up capability of the proposed converter is demonstrated for dc-dc and ac-dc operations. Moreover, the dynamic performance of the converter during load failure and dc-bus interconnection is examined. Furthermore, the results demonstrate tight voltage tracking and sinusoidal supply current with unity power factor of the proposed interleaved converter during ac-dc conversion.