A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse

True Random Number Generator (TRNG) is used in many applications, generally for generating random cryptography keys. In this way, the trust of the cryptography system depends on the quality of the random numbers generated. However, the entropy fluctuations produced by external perturbations generate some false positives in the random sequence. These false positives can generate a disastrous scenario, depending on the application. This work presents the results of different tests to demonstrate the robustness and health of the TRNG based on frequency collapse. The TRNG passed all entropy tests provided for NIST SP800-90B and AIS31. The entropy test denotes a 0.9789 minimum normalized entropy and 7.998 Shannon entropy. In addition, the TRNG passes the health tests provided for NIST SP800-90B. The health test shows a number of identical values <inline-formula> <tex-math notation="LaTeX">$I_{v}=0\%$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$I_{v-1} < 0.004\%$ </tex-math></inline-formula> and a maximum cutoff value <inline-formula> <tex-math notation="LaTeX">$MC_{v}=10$ </tex-math></inline-formula> with <inline-formula> <tex-math notation="LaTeX">$LMC_{v}=13$ </tex-math></inline-formula> in the repetition count and adaptive proportion tests, respectively. The implementation passed all the statistical tests provided for NIST SP800-22 and AIS20. Besides, the implementation passes the different tests with Process, Voltage, and Temperature (PVT) variations. The TRNG is implemented in a <inline-formula> <tex-math notation="LaTeX">$0.18~\mu m$ </tex-math></inline-formula> General Purpose (GP) CMOS technology, occupying <inline-formula> <tex-math notation="LaTeX">$25600~\mu m^{2}$ </tex-math></inline-formula> with four entropy sources. Finally, the implementation presents a 7.3 until 9.2-Mb/s of bit rate, 0.56 until 1.88-mW of power consumption, and 77.2 until 204.3-pJ/bit of energy per bit using an entropy source with 16 and 2 delay stages, respectively.


I. INTRODUCTION
Random Number Generator (RNG) is vital for cryptography systems. The specifications of the RNG need high throughput or energy efficiency, depending on the application in the system. However, the RNG must provide a minimum level of trust independent of the application. The level of trust in RNG circuits is usually measured using a statistical test. For example, the National Institute of Standards and Technology (NIST) and the German Federal Office for The associate editor coordinating the review of this manuscript and approving it for publication was Chien-Ming Chen . Information Security (BSI) provide the SP800-22 [1], and AIS20 [2] test, respectively. Nevertheless, the statistical tests are not enough to provide a good level of trust. The external perturbations create a variance of the minimum entropy, generating a false positive in the random sequences. The NIST SP800-90B provides an entropy test to determine the robustness of the entropy source [3]. The entropy test evaluates the minimum entropy in the entropy source, depending on the Independent and Identically Distributed (IID) assumption. Besides, the AIS31 presents an entropy test to verify and extract the Shannon entropy, using an additional stochastic model [4]. In another way, the health test controls the quality of the TRNG to prevent disastrous scenarios in the random sequence. Typically, the health test measures only the entropy or the statistical results on random numbers generated into the chip [5]- [7]. However, a disastrous scenario can be generated only with a false positive in a small part of the sequence. The NIST 800-90B also provides tests for verifying the health of the entropy source, detecting fixed and repetition number generation scenarios in the entropy source [8]. The health of the entropy source is quantified using the number of identical and cutoff values in the repetition count and adaptive proportion tests.
The physical phenomenons in the entropy source and the different forms to digitize the entropy determine the affectation of the external perturbations. For example, some TRNG uses an external entropy source [9]- [12]. However, external sources can be affected by external perturbation. Also, the difficulty of external attacks is reduced. The analog-TRNG uses an entropy source based on the noise presented in some analog circuits [13]- [16]. However, an analog/time to digital converter is necessary to digitize the entropy, increasing the area of the TRNG. The different kinds of Random Access Memory (RAM) are used to generate a random number, using the time response or leakage current [17]- [22]. Nevertheless, these entropy sources present the problem of characterizing the time response to obtain good digitization, and temperature variations affect the leakage current in RAM-TRNG or the additional mask for the resistive RAM. The architectures of TRNG based on metastability present a high bit rate, digitizing by flip-flops or latches [7], [23]- [26]. Nonetheless, the metastability sources can be affected for PVT variations, resulting in low minimum entropy [23]. In this way, the TRNG based on metastability solves the problem of the minimum entropy using a pulse generator [7] or a multi-entropy source [25] to improve the quality of the entropy source. Finally, the jitter is used in some architectures of TRNG, digitizing the entropy with two forms. First, the entropy is digitized by a flip-flop, using two clocks with low and high frequency, respectively [27]- [30] or the self-timed in Chaotic Cellular Automata [31]. Second, the jitter is measured using a physical phenomenon caused for the jitter accumulation in a multi-modal Ring Oscillator (RO). The entropy is digitized using the time of a frequency collapse [32]- [36]. However, the mismatch can affect the frequency collapse, generating dependencies used for Physical Unclonable Function (PUF) applications [37].
This work is a continuation of the work presented in [32], when the problems and solutions to implement the TRNG based on frequency collapse in Field Programmable Gate Array (FPGA) is shown. The main contribution of the current work is the demonstration of the robustness and healthy of the TRNG based on the same physical phenomena in an ASIC implementation. In addition, we extend an analytical model for ASIC implementation of three-edges multi-modal RO used in the entropy source, based on the model presented for FPGA implementation. A suggestion for the layout of the TRNG is proposed based on the analytical model, reducing the mismatch in the entropy source. Besides, the relations between power and minimum entropy with the number of stages in the multi-modal RO are presented. The implementation passes the NIST SP800-22 and AIS20 statistical tests. The entropy source passed the NIST 800-90B, and the AIS31 test with 0.9789 of minimum normalized entropy and 7.998 of Shannon entropy, using 16-stages multi-modal RO. Besides, the entropy source passes the repetition count and the adaptive tests with I v = 0%, I v−1 < 0.004% and a MC v = 10 with LMC v = 13, respectively. The statistical, entropy and health tests are applied with PVT variations. The ASIC implementation occupies a 25600µm 2 in a 0.18µm GP CMOS technology with four different entropy sources implemented. Also, the TRNG reports a 7.3 until 9.2-Mb/s of bit rate, 0.56 until 1.88-mW of power consumption, and 77.2 until 204.3-pJ/bit of energy per bit, using an entropy source with 16 and 2 delays stages, respectively.
The remainder of this paper is organized as follows. Section II describes the analytical model of the entropy source and the architecture of the TRNG implemented. Section III shows the results of the entropy test described in NIST SP800-90B and AIS31. Section IV describes the health test applied in the entropy source. Section V shows the results of the NIST SP800-22 and AIS20 statistical tests. Section VI illustrates the area, power, and bit rate of the TRNG implemented. In addition, the relations between power and minimum entropy with the number of stages in the multimodal RO. Finally, section VII concludes the paper.

II. TRUE RANDOM NUMBER GENERATOR (TRNG) A. TRNG CORE
This section relates the different parts of the TRNG implemented. The TRNG used a physical phenomenon denominated frequency collapse to obtain the random numbers. The frequency collapse occurs for the jitter accumulation in a Multi-modal RO. The random number generated represents the time necessary for the frequency collapse. Fig. 1. shows the block diagram of the architecture of the TRNG. The architecture is divided into three parts. First, the Entropy Stage highlighted in gray is the part when the frequency collapse occurs. In addition, the oscillation signal is used in the Capture Stage. Second, the Compare Stage highlighted in red compares the oscillation signal generated in the Entropy Stage with a reference signal, using a Phase and Frequency Detector (PFD). Finally, the Capture Stage highlighted in blue generates the random number, using an 8-bit counter with the clock provided for the Entropy Stage. The fourth bit of the counter is used to prevent a false trigger in the PFD. Fig. 2 depicts the block diagram of the entropy source and the clock reference used in the TRNG implemented. The entropy source (RO RNG) consists of three edges multi-modal RO, and each edge has an N-stages of inverters with the respective delay (t 0 ). In another way, the clock reference is implemented using a conventional RO (RO REF). The stages define the initial frequency in the RO RNG and the length  However, a Glitch Removal highlighted in red is implemented to mitigate the false events generating for the small frequency differences between the entropy source and the clock reference before the frequency collapse. In addition, a False Event Detector highlighted in blue is implemented to eliminate the false positives generated in the start-up in the RO RNG and RO REF.

B. ANALYTICAL MODEL
In the odd edges multi-modal RO, the pulse generated in the odd edges changes the path in each oscillation, reducing the relation of rising and falling delays compared to an entropy source with even edges multi-modal RO [35]. An odd edges multi-modal RO analytical model is proposed for FPGA implementation [32], associating the frequency collapse between the noise and systematic mismatch. However, in ASIC implementation is possible to apply other  strategies to reduce the mismatch, increasing the relationship between noise-mismatch. The time of any pulse generated by the edges arrives at the output (T p ) in the multi-modal (1). (1) where k and n represent the numbers of edges and cycles, respectively. In addition, t 0 exhibits the typical delay, and δ m(n,j) is the delay generated for the mismatch in the inverter cell in the multi-modal RO. However, the mismatch after ASIC fabrication is a random constant. In this way, the delay generated for the mismatch is δ m(n,j) = C. Consequently, this constant is possibly reduced using different techniques.
In another way, δ e(n,i) and δ e(n,j) are the noise in the even and odd delay cells that originated for the external signals. The inference can be approximate δ e (n, j) = δ e (n, i) ∼ N (0, ρ 2 ). When ρ represents the variance of the random occurrences of the external signals. Finally, the δ n(n,i) and δ n(n,j) are the jitter introduced in the delay cells. The quality of the numbers increases when the jitter is the majority of T p . In conclusion, the three edges model (2) demonstrates the variance increase linearly with the number of cycles, when δ(n, j) = δ(n, i) ∼ N (0, σ 2 ) [33]. Fig. 4 illustrates the ASIC recommendations for reducing the undesirable effects related to the analytical model (2). The δ m is reduced using the fixed placement of the cells in the same row of the grid in the multimodal and conventional RO. The purpose is to obtain the same variations in each edge in the entropy source. In addition, a routing blockage highlighted in gray is applied in the multimodal and conventional RO, reducing significantly the (δ e ) introduced for the external signals. The compare and capture stages of the TRNG are placement and routing using the conventional digital flow.

III. ENTROPY TESTS
This section presents the entropy source results provided for the NIST SP800-90B and the AIS31 entropy test. The entropy results are presented with a non-IID assumption in the NIST SP800-90B. The NIST and AIS31 results are applied with PVT variations. The minimum and Shannon entropy are presented in the TRNG with 16 delay stages in the entropy source. Table 1 shows the NIST 800-90B test results with process variations.The data is recollected without a conditional component in nominal conditions (VDD = 1.8[V] and 25[ • C]). The first step to determine the quality of the entropy sources is to classify the random number generated in IID or non-IID. The entropy source used in the TRNG depends on the jitter generated by the thermal noise. In addition, the systematic mismatch influences the random numbers generated, according to the analytical model. However, an overestimation of the minimum entropy (H min ) is generated for false positives in the IID assumption [38], [39]. In this way, the entropy source is classified with a non-IID assumption for the systematic mismatch in the collapse time. The minimum value of the estimators determines the initial minimum entropy (H I ) in the non-IID test. The entropy source implemented present a H I = 0.9890 * 8 = 7.9120. However, the H I is determined with a long sequence, generating possible correlations. Table 2 shows the results of the SP800-90B restart test. The restart test measures the data when the entropy source is restarted 1000 times. One thousand samples are collected directly in the entropy source at each restart time. The entropy VOLUME 10, 2022 results of the restart test are divided into a row (H R ) and column (H C ), respectively. The minimum entropy of the entropy source is determined with H min = min(H I , H R , H C ). Table 3 shows the results of the AIS31 test. The AIS31 test is applied with 5MB of data. The sequence generated for the entropy source is divided into (b 1 , b 2 , . . . , b 10000 ) sub-sequences. The Uniform and Multinomial distribution sub-test determine the correlation with distributions in the sequence. In the worst case, the entropy test denotes a 7.998 of Shannon entropy, applying PVT variations.

IV. HEALTH TEST
The NIST 800-90B proposes a health test to detect the deviations of the sequence generated for the entropy source. The Repetition Count (RC) and Adaptive Proportion (AP) tests are explained and applied with PVT variations in this section.
The health tests are applied in a System on a Chip (SoC) described in section VI.

A. REPETITION COUNT TEST
The RC test detects disastrous failures caused when the entropy source is stuck in a single value for a long time. The number of identical values (I v ) in the RC test is defined based on the H min in the entropy source and the level of acceptance (α H ). Besides, the I v is the smallest integer satisfying the inequality α H ≥ 2 −H (I v −1) . The equation for defining the number of identical values is as follows: Algorithm 1 describes the RC test implemented. Where (L) represents the length of the data-set used for the RC test. The entropy source implemented with PVT variations presents a H min = 7.8312 of minimum entropy. The NIST 800-90B recommends a α H = 2 −20 . In this way, the entropy source implemented denotes I v = 3 for the RC test. The entropy source presents a percentage of occurrences I v = 0%, applying the PVT variations. In this way, the entropy source passed the RC test. However, a false positive in the RC test can be generated for the length of the sequence generated. In this way, the estimator I v−1 is necessary to obtain an estimation when the length of the sequence tends to be infinite. Fig. 6 shows the percentage of the occurrences of I v−1 with PVT variations. Each scenario is measured in five different chips, recollecting an 8MB per scenario to apply to the RC test. The data illustrated in each voltage and temperature scenario is the worst case in the five chips. The percentage of occurrences in I v−1 is less than 0.004%. In view of the percentage in I v < I v−1 , the entropy source implemented demonstrates a robust fixed values generation with PVT variations.

B. ADAPTIVE PROPORTION TEST
The AP test exposes the missing of entropy in the time for some physical failure or external disturbance. The test measures the occurrences of a sample in the sequence generated in the entropy source. Algorithm 2 describes the AP test. The occurrences are measured in a window time (W ). The size of W depends on the number of output bits in the entropy source. When the generation of the entropy source is binary, the size is 1024-bits. In the other case, when the generation is non-binary, the size is 512-bits. The size of W in the entropy source implemented is the second option. The Limit of the Maximum Cutoff Value (LMC v ) is 13 with H min = 7.8312, W = 512 and α H = 2 −20 . Fig. 7 illustrates the cutoff value occurrences in the entropy source. The cutoff values are measured with PVT variations. Two thousand window samples are measured per case in five different chips. The mean of all cutoff values is 2. However, the entropy source presents a high atypical value in some cases. The maximum cutoff value (MC V ) is 10. Nevertheless, the LMC v > MC v passed the AP test with PVT variations.

V. STATISTICAL TEST
This section shows the statistical results of the TRNG implemented. The NIST AIS20 and SP800-22 results are presented with PVT variations.  A. AIS20 Table 4 shows the results of AIS20 of the TRNG implementation. For the AIS20 the sequence is divided in (b 1 , b 2 , . . . , b 20000 ) sub-sequences. The AIS20 test does not standardize the acceptance of the sub-test compared to the NIST SP800-22. For example, the disjointness (T 0 ) test determines the coincidence of non-overlapping patterns in the sequence. The sequence passes only if all sub-sequences are disunity. The monobit test evaluates one and zeros bias in the sequence generated in the TRNG. The estimator (T 1 ) counts the number of ones into the sequence. When the value obtained in the monobit belongs to (9654 < T 1 < 10346) rank, the sequence passes the monobit sub-test. The poker test examines the pattern occurrences in the sequence. The T 2 estimator is defined as follows in (4).
Ther denoted the observed numbers in the λ-runs. The run test passes when the result of the estimator is into the rank per each λ-runs. The rank in each λ-runs is ( 20000 1)). In addition, the long run test is a run test with (λ > 34). The autocorrelation test checks the similarity of the sub-sequence in the time. However, the estimator T 5 is obtained with 10000 sub-sequence, depending on the values of the parameter τ ∈ (1, 2, . . . , 5000). The autocorrelation test follows an N(0,1) distribution. In this way, the test needs to be two-sided in the length of the sequence. The TRNG passed all AIS20 tests with PVT variations.
B. NIST SP800-22 Table 5 shows the results of NIST SP800-22, applying the PVT variations. The level of significance (α) applied in the test is α = 0.01. In this way, one sequence of 100 sequences is to be rejected. In addition, the test needs a P-value ≥ 0.01, indicating the sequence generated is 99% confidence. The TRNG is proved in the different chips with low, typical, and high voltage and temperature values. The TRNG passes all tests NIST SP800-22.

VI. RESULTS
This section presents the TRNG implemented in 0.18 µm GP CMOS technology. First, a comparison of the minimum entropy is present with entropy sources based on different physical phenomenons. Second, the results of the TRNG of power, area, and the bit rate. Fig. 8 shows a block diagram of the microcontroller used for measuring the TRNG implemented. The SoC is based on a RISC-V ISA processor [40] with AHB-Lite for the system bus and APB for the peripheral bus [41]. In addition, the system has a 1-KB of RAM, a Timer, a JTAG-based debug module, a UART, a QSPI for external flash memory, a General-Purpose In-Outs (GPIO), and the TRNG.  Table 6 depicts a comparison of the minimum normalized entropy with entropy sources based on different phenomena. The minimum entropy is obtained with the NIST SP800-90B test with PVT variations in the worst result. The TRNG implemented presents a competitive minimum entropy compared to entropy sources based on leakage and resistance variations. However, the entropy sources with different physical phenomena show better results with an IID assumption, generating the possibility of overestimation in the minimum entropy. In addition, the implementation passes the health test provided by NIST SP800-90B, demonstrating the health of the TRNG. Fig. 9 shows the micrograph of the TRNG in 0.18 µm GP CMOS technology. The micrograph contains an SoC with the TRNG. The TRNG occupies 25600µm 2 with four entropy sources. Each entropy source with the RO REF represents  12.5% of the area. The compare and capture stages represent 50% of the resources. The suggestions implemented in the entropy source present a 1.5× of area overhead. Fig. 10 illustrates the power consumption of the TRNG implementation in nominal conditions, using the different entropy sources. The four entropy sources area implemented with 2, 4, 8, and 16 delay stages. The power consumption of the TRNG is determined in major with the number of the delay stages into the multi-modal RO. The TRNG presents a 564.21-µW until 1.88-mW with 16 and 2 delay stages in the entropy sources, respectively.   Table 7 shows a comparison of the TRNG implementation with the related works. The statistical and entropy tests are tested using a 16 delay cell in each edge. The bit rate of the TRNG depends on the random time per collapse. In this way, the time of the collapse frequency is measured 10Mtimes, reporting a 7.3 and 9.2-Mb/s of bit rate, using 16 and 2 delay stages in the entropy source. In addition, the implementation reports a 493.82-10 3 F 2 of normalized area. Fig. 11 plots the minimum entropy of the TRNG using the different entropy sources. The TRNG denotes a 0.9890 until 0.9972 of minimum entropy in the 16 and 2 delay stages in multi-modal RO. The results show an increase in the minimum entropy when the number of stages is reduced. However, the uses of a reduced number of delay stages increase the power consumption and the energy per bit of the TRNG implemented.

VII. CONCLUSION
This work presents a robust and healthy TRNG in ASIC based on collapse frequency. The TRNG is implemented using a suggestion based on an analytical model, reducing the undesirable effects in the random number generation. The implementation passed the NIST SP800-90B and AIS31 entropy tests. The NIST SP800-90B is applied using a non-IID assumption based on the ASIC analytical model. The entropy sources implemented present a 0.9789 minimum normalized entropy and 7.998 of Shannon entropy, using 16 delay stages in the entropy source. Besides, the TRNG implementation passed the NIST SP800-22 and AIS20 statistical test. In addition, the implementation passed the two health tests provided for the NIST SP800-90B. The RC test presents 0% and 0.004% of occurrences in the I v and I v−1 estimator, respectively. The AP test reports a MC v = 10 with LMC v = 13. The TRNG passed the entropy, health, and statistical tests with PVT variations, demonstrating the robustness and health of the implementation. The data used for the tests are recollected using a RISC-V microcontroller. The TRNG occupies 25600µm 2 using four entropy sources. Each entropy source represents 12.5% of the area in the implementation. The suggestions applied in the entropy source present 1.5× of area overhead. Finally, the TRNG denotes a 0.56 until 1.88-mW of power consumption, 7.3 until 9.2-Mb/s of bit rate, and 77.2 until 204.3 pJ/bit of energy per bit using 16 and 2 delay stages in the entropy source, respectively.

ACKNOWLEDGMENT
The VLSI chip in this study has been fabricated in the chip fabrication program of through the activities of VDEC, the University of Tokyo in collaboration with Rohm Corporation and Toppan Printing Corporation.