0.5 V Differential Difference Transconductance Amplifier and Its Application in Voltage-Mode Universal Filter

This paper presents an innovative CMOS structure for Differential Difference Transconductance Amplifiers (DDTA). While the circuit operates under extremely low voltage supply 0.5 V, the circuit’s performance is improved thanks to using the multiple-input MOS transistor (MI-MOST), the bulk-driven, self-cascode and partial positive feedback (PPF) techniques. As a result, the DDTA structure is less complex, with high gain of 93 dB, wide input voltage range nearly rail-to-rail, and wide transconductance tunability. As an example of application, a second-order voltage-mode universal filter using three DDTAs and two 6 pF integrated capacitors is presented. The filter is designed such that no matching conditions are required for the input and passive components, and the input signals need not be inverted. The natural frequency and the quality factor can be set orthogonally while the natural frequency can be electronically controlled. The circuit was designed and simulated in Cadence environment using $0.18 \mu \text{m}$ TSMC technology. The simulation results including intensive Monte-Carlo (MC) and process, temperature, voltage (PVT) analysis confirm the stability and the robustness of the design to process, mismatch variation and PVT corners.


I. INTRODUCTION
In modern portable electronics, wireless sensors, biomedical and energy harvesting applications the reduction of the voltage supply and the power consumption is a continuing demand that leads to prolong the operation period of the applications. Therefore, CMOS designers still have to innovate techniques that permit improving the performance of the analogue circuits operating under extremely low-voltage supply (≤0.5 V). Circuits operating in subthreshold region along with non-conventional techniques such as bulk-driven (BD) [1]- [15], floating-gate (FG), quasi-floating-gate (QFG) [16]- [19] and multiple-input MOS transistor (MI-MOST) [13], [20]- [28] are promising solutions for low-voltage The associate editor coordinating the review of this manuscript and approving it for publication was Xi Zhu . supply and low frequency applications. The MI-MOST can further lead to decrease the complexity of the CMOS structure by reducing the number of transistors and current branches. This results in optimized chip area and reduced power consumption of the applications. The symbol and the realization of the bulk-driven MI-MOST are shown in Fig. 1.
This BD MI-MOST can be realized in any standard CMOS technology; hence, no extra fabrication steps are needed. From a conventional MOS transistor, multiple-inputs (V 1 , . . . , V n ) are created by a set of parallel connection of input capacitor C B and high-resistance R MOS that are implemented by two transistors M R operating in cut-off region.
In this paper, the BD MI-MOST has been used to design the Differential Difference Transconductance Amplifiers (DDTA). The DDTA comprises the advantage of the Differential Difference Amplifier (DDA) such as high input impedance and arithmetic operation capability, and of the Transconductance Amplifier (TA) such as electronic tunability. Unlike the previous standard structures of the DDTA [29]- [32], the proposed structure is compact, innovative and optimized to work under extremely low voltage supply 0.5 V with enhanced performance. While the input stage of a standard DDTA (i.e. DDA) uses two differential pairs, the proposed structure uses one differential pair based on bulkdriven multiple-input MOS transistor technique. This leads to reduced design complexity from one side and to increased range of the input voltage nearly rail-to-rail from other side. In addition, and to the best of the authors' knowledge, the input stage comprises, for the first time, two partial positive feedbacks (PPF) to achieve high performance like high gain around 93 dB with lower sensitivity to transistor mismatch. The second stage of the proposed DDTA (i.e. TA) is based on the BD technique and self-cascode transistors that increase the output resistance and the gain of the TA. This paper is organized as follows: in Sec. 2 the innovative CMOS structure of the DDTA is presented, Sec. 3 presents the filter application of the voltage-mode universal filter, Sec. 4 presents the simulation results and finally Sec. 5 concludes the paper.

II. CMOS STRUCTURE OF DDTA
The symbol of the DDTA is shown in Fig. 2. Internally it consists of the DDA, followed by the TA. In ideal case, the DDTA is described by the following set of equations: The CMOS structure of the proposed DDTA is shown in Fig. 3. As mentioned above, the circuit consists of two main blocks. The first one is the differential-difference amplifier stage DDA operating in a unity-gain configuration, thus realizing a low-impedance output W. The second block is the transconductance stage TA, based on a classical BD differential pair with DC voltage gain enhanced thanks to the use of self-cascode composite transistors.
The DDA block consists of two stages, the input differential stage operating in a current mirror configuration M 1 -M 15 and the output stage M 13 -M 16 with the frequency compensation capacitance C C . Similar structure has previously been applied in [10], [11]. The input differential stage consists of the non-tailed differential pair M 1 -M 2 , biased with the current sinks M 3 -M 4 , and the partial positive feedback (PPF) circuit, M 5,6 , M 9,10 , applied as a load of the input pair. The crosscoupled transistors M 9 -M 10 generate the negative resistances −g m9 and −g m10 , which partially compensate the positive conductances of the diode-connected transistors M 5 and M 6 (g m5 and g m6 ). This way the load resistance is increasing and the overall voltage gain is improved [10]. However, two modifications have been made as compared to the original design. First, the input BD transistors M 1 -M 2 have been replaced by BD MI-MOS transistors that allowed simplification of the overall structure, namely removing one differential stage, since summation of signals is realized by the passive capacitances C Bi . The second modification is the addition of the second PPF circuit M 7 -M 8 , applied directly to the input non-tailed differential pair, in the same configuration as previously described in [33], [34]. To the best of the authors' knowledge, the application of two PPF circuits instead of one is the original solution proposed in this DDA structure. As it is widely known, the sensitivity of the circuits with PPF to transistor mismatch increase with the amount of positive feedback that can even lead to instability. This effect limits the maximum amount of feedback and consequently the voltage gain enhancement factor. As will be shown below, application of two PPF circuits with a weaker feedback instead of one with stronger feedback allows achieving the same voltage (transconductance) gain enhancement, with lower sensitivity to transistor mismatch. This is the main advantage of the proposed approach.
The low-frequency voltage gain of the DDA, from one differential input, with the second input grounded for AC signals, in open-loop configuration, can be expressed as follows: where A o is the DC open-loop voltage gain of the DDA, without PPF circuits, calculated directly from the bulk terminals of M 1 , and given as: The coefficient β is the AC gain of the input capacitive divider, composed of the capacitances C Bi in MI-BD MOS transistors, assuming equal capacitances C Bi and neglecting the impact of the input capacitance of a MOS transistor seen from its bulk terminal is equal to 1/2. The factors m 1 and m 2 can be expressed as: Thus, the factors m 1 and m 2 can be considered as the ratios of the absolute values of the negative to positive conductances in ''bottom'' PPF 1 and ''upper'' PPF 2 . The factors can range from zero (lack of positive feedback) to unity (100% positive feedback). Note that, the overall voltage gain A vo increases from βA o to infinity, as m 1 , m 2 increase from 0 to 1. The maximum values of the factors are however limited by two effects. First, the circuit sensitivity to transistor mismatch increase, as m 1 , m 2 tend to unity, which limits the maximum reliable voltage gain, and increases also the variations of the transconductance of the first stage of the DDA. This entails increased variations of the phase margin of the overall structure, thus affecting the circuit instability, even if the circuit is not yet overcompensated, i.e. when the absolute values of the negative conductances in PPF are not larger than the positive ones. The sensitivities of the voltage gain A vo to the values of the coefficients m 1 and m 2 are given as: thus, both sensitivities are nonlinear functions of m 1 (m 2 ), and their values tend to infinity, as m 1 (m 2 ) tend to unity. Note that, considering linear approximation, the relative variation of the voltage gain A vo , caused by the relative variations of m 1 and m 2 in a two PPF circuit can be expressed as: It can be concluded from (6)-(8) and (2) that using two PPF with lower values of m can provide the same voltage gain with lower overall sensitivity than using only one PPF circuit with larger value of m. For instance, assuming m 1 = m 2 = 0.5 (as in the proposed design), according to (2) the voltage gain is improved by 12 dB, compared to the version without PPF, (8), and assuming 1% variations of m 1 and m 2 , results in 2% variation of A vo . In order to obtain the same enhancement of the voltage gain with one PPF circuit, say PPF1, we should chose m 1 = 0.75, which, according to (6), gives the sensitivity equal to 3, namely 1% variation of m 1 results in 3% variation of A vo . This improvement would even be more apparent when assuming larger values of m 1 , m 2 .
The second important factor, limiting the maximum values of m 1 , m 2 , is the location of the parasitic poles, associated with PPF 1 and PPF 2 . Neglecting the second-order effects, the poles can be respectively expressed as: where C O1 and C O2 are the total capacitances associated with the drain/gate nodes of M 2 and M 5,6 , respectively. As it can be noticed, the frequencies of the poles decrease with increasing m 1 and m 2 . In order to mitigate their impact on the phase margin of the DDA, the poles should be located well above the gain-bandwidth product (GBW) of the DDA. This limits the maximum values of m 1 and m 2 and consequently the achievable voltage gain. The phase shift associated with these poles for the cutoff frequency ω GBW can be expressed as: where: Note that for ω pPPF1 and ω pPPF2 ω GBW we can apply the linear approximation arctg(x) = x. Consequently, the phase shift can be approximated as: Assuming for simplicity that ω pPPF1 = ω pPPF2 = ω pPPF1,2 , and m 1 = m 2 , the corresponding pole for a circuit with one VOLUME 10, 2022 PPF, providing the same A vo , can be calculated as: Using (13) and (14) we can conclude that the phase shift for a system with one PPF is lower for m 1,2 < 0.5 and larger for m 1,2 > 0.5, compared to its counterpart with two PPFs.
In the proposed design we chose m 1,2 = 0.5, that provides the same phase shift in both cases. Finally, since DDA operates with a 100% negative feedback, the voltage at the W terminal for low frequencies can be expressed as: while the output resistance at the W terminal is: Thus, since PPF allows improving the voltage gain A vo , then both the accuracy of the basic function given by (1) as well as the output resistance at W terminal are improved. At the same time, applying two PPFs instead of one allows decreasing the circuit sensitivity to mismatch, compared to the circuit with one PPF and the same A vo . The second block of the proposed DDTA circuit, namely the transconductance amplifier TA, operates in the so-called current mirror configuration, with the input BD differential pair. The self-cascode composite transistors M 3 -M 9 are used to improve its DC voltage gain. The biasing current I set can be adjusted independently, that allows regulating the circuit transconductance g m . Assuming unity-gain current mirrors, its DC transfer characteristic in a weak inversion in given by: where η = g mb /g m is the bulk to gate transconductance ratio, n p is the subthreshold slope factor and U T is the thermal potential. The small-signal transconductance of the OTA is: while its DC voltage gain: Thus, as mentioned previously, the voltage gain is enhanced due to the application of self-cascode connections, improving the output resistance of the TA stage.

III. APPLICATION OF THE DDTA
The proposed universal filter using three DDTAs and two integrated capacitors is shown in Fig. 4. The input voltages V in1 , V in2 , V in3 , V in4 are applied to high impedance terminals while the output voltages V o1 , V o2 , V o4 possess low impedance terminals. Using (1) and nodal analysis, the output voltages of Fig. 4 can be expressed by: From (20)- (24), it is evident that various filtering functions such as low-pass filter (LPF), band-pass filter (BPF), highpass filter (HPF), band-stop filter (BSF), and all-pass filter (APF) can be obtained by appropriately applying the input signals as well as appropriately choosing the output signals. The unused input terminal should be connected to ground. The input and output conditions and various filtering functions realized can be shown in Table 1. It should be noted from Table 1 that no inversion of input signal is necessary to obtain all filtering transfer functions, and additional buffers are therefore not required. The natural frequency (ω o ) and the quality factor (Q) can be expressed by: Eqs. (25) and (26) show that the natural frequency can be controlled by g m (g m = g m1 = g m2 ) and the quality factor can be given by C 1 /C 2 while keeping g m1 = g m2 . Thanks to electronic tuning ability, the natural frequency can be retuned if the ratio C 1 /C 2 deviates the natural frequency.

IV. NON-IDEALITIES ANALYSIS
Considering non-idealities of the DDTA, its characteristics can be rewritten as: where β j1 = 1 − ε j1v and ε j1v ( ε j1v 1) denotes the voltage tracking error from V y1 to V w of j-th DDTA, β j2 = 1 − ε j2v and ε j2v ( ε j2v 1) denotes the voltage tracking error from V y2 to V w of j-th DDTA, and β j3 = 1 − ε j3v and ε j3v ( ε j3v 1) denotes the voltage tracking error from V y2 to V w of j-th DDTA. The non-ideal transconductance gain g mnj is given by: (28) where ω gmj denotes the first-order pole frequency that includes parasitic elements such as C oj and R oj at o-terminal of j-th DDTA, and g mj denotes the open-loop transconductance gain of j-th DDTA.
In the frequency range of interest of this paper, g mnj can be approximated as: where µ j = 1 ω gmj . Using (27), the denominator of the transfer function can be expressed as: Using (29), (30) becomes: g m1 g m2 β 12 β 21 µ 1 + g m1 g m2 β 12 β 21 µ 2 C 2 g m1 β 11 β 32 + g m1 g m2 β 12 β 21 (31) From (31), the non-idealities of the DDTAs affect the circuit characteristics, which depart from ideal values. The parasitic effects from the DDTA can be made negligible by satisfying the following conditions: C 2 g m1 µ 1 β 11 β 32 − g m1 g m2 β 12 β 21 µ 1 µ 2 C 1 C 2 1 (32) g m1 g m2 β 12 β 21 µ 1 + g m1 g m2 β 12 β 21 µ 2 C 2 g m1 β 11 β 32 1 (33) Therefore, the non-ideal natural frequency (ω on ) and the nonideal quality factor (Q n ) can be obtained respectively by: The sensitivity of ω on and Q n with respect to circuit components and non-ideal parameters are given as follows: It can be concluded from (36)- (38) that all the sensitivities are within unity in magnitude. Thus, the proposed filter enjoys good active and passive sensitivities. The filter behavior may be affected at low frequencies by parasitic resistances R 1 and R 2 acting in parallel to integrating capacitors C 1 and C 2 . The error analysis reveals finite parasitic DC attenuation Att 0 in high-pass and particularly in band-pass outputs. For the band-pass filter in V in2 and V o1 configuration, this attenuation is: It is obvious that the g m × R product must be kept as high as possible to maintain high attenuation, and that this issue is critical for the parasitic resistance R 2 near DDTA 2 . Note that for the attenuation of at least 40 dB, the g m × R should be approximately 99. For low transconductances, typically below 100nS, this condition imposes challenging demands on high resistances acting at TA output.

V. SIMULATION RESULTS
The proposed DDTA circuit and the filter application were designed and simulated in Cadence environment using 0.18 µm CMOS technology from TSMC. The voltage supply was 0.5V (±0.25V). The bias current I B was set to 40 nA and the I set is adjustable. For I set = 1 nA, the total power consumption of the DDTA is 205.5 nW (DDA = 203 nW and TA = 2.5 nW). The transistor's aspect ratio of the DDTA are shown in Table 2.
The high performance linear metal-insulator-metal (MIM) capacitor that is available in TSMC technology has been used in the DDTA design.   The DDA was simulated in the open-loop configuration, with load capacitance 20 pF, to confirm the impact of the used techniques, mainly the two PPFs, on the performance of the proposed structure. As it is evident from Fig. 5 that shows the frequency and the phase characteristics of the DDA, the proposed DDA offers the highest gain around 93 dB, while the lowest gain is for the DDA structure without PPF, where the gain is around 77.81 dB. The detailed results of the gain, phase margin and gain bandwidth product (GBW) of the proposed DDA, DDA without PPF, with NMOS PPF and with PMOS PPF is shown in Table 3, that confirm our expectation.
To confirm the robustness of the design with process and mismatch variation, the Monte-Carlo (MC) analysis with 2000 runs was performed. The histogram of the DDA gain, phase margin, common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), voltage offset and GBW is shown in Fig. 6. The DDA enjoys small deviations for most of these parameters. For instance, the mean value of the phase margin is 53.43 • and standard deviation is only 1.12 • .  Larger variations were observed only for CMRR and PSRR, which were significantly lower than their nominal values (67.2 dB, 81.5 dB, respectively) shown in Table 4. The impact VOLUME 10, 2022   of mismatch could be mitigated employing larger transistor channel sizes. Fig. 7 shows the output voltage V W versus the input voltage V y1 of the DDA connected in unity gain configuration. It can be observed that the circuit enjoys nearly rail-to-rail operation under 0.5V supply voltage. The TA was simulated for different set current I set = 1, 2, 4, 8, 16 nA. The DC characteristic of the output current I o versus differential input voltage V in (V in = V + − V − ) is shown in Fig. 8(a) while the transconductance G m is shown in Fig. 8 (b). The transconductance has 10% variation from the nominal value in the range of ±75 mV.
The PVT corners analysis for the DDA and TA are depicted in Tables 4 and 5. The MOS transistor corners were slowslow (SS), slow-fast (SF), fast-slow (FS) and fast-fast (FF), the voltage corners were V DD ± 10% and the temperature corners were −20 • C and 80 • C. Since the MIM capacitors are used in the design, their corners (SS) and (FF) have been also performed. As it is shown from these tables, the performance of the DDTA is still acceptable with all PVT corners. For onchip integration, the filter with small capacitors is preferred. Therefore, for the filter application in Fig. 4, the value of capacitors for integration was selected low C 1 = C 2 = 6 pF. For I set1,2,3 = 1 nA, the transfer characteristics of the LPF, HPF, BPF and BSF are shown in Fig. 9 (a). The simulated natural frequency (f o ) is 254 Hz. Fig. 9 (b) shows the magnitude and phase characteristics of the APF. It can be confirmed that the proposed filter can provide five standard filtering responses within a single topology. This confirms that the proposed filter enjoys electronic tuning ability. Fig. 11 (a) and (b) show the magnitude characteristics of the LPF, HPF, BPF and BSF with process corners and MC analysis, respectively, obtained for the same bias condition as for Fig. 9 (a), this way confirming the robustness of the filter. The transient response of the LPF for I set1,2,3 = 1 nA is shown in Fig. 12. A sine-wave signal with 100 mV pp @ 10 Hz has been applied to the input of the filter as shown in Fig. 12 (a). The output signal is shown in Fig. 12 (b). The nominal total harmonic distortion (THD) was 0.62%. The THD simulation was repeated using the MC analysis with 200 runs. The result of the histogram is shown in Fig. 13. The mean value of the THD was 1.37% while the standard deviation was 0.98%. The THD of the LPF with different input voltage and different frequencies 10 Hz and 100 Hz is shown in Fig. 14. The LPF shows THD below 1.2% for 120 mV pp .
The output noise characteristic of the LPF is shown in Fig. 15. The RMS value of the integrated noise was 116 µV, which results in the dynamic range (DR) around 49.7 dB. The mean value of the DR stays around 47.4 dB with worst case of MC and process corner analysis.
Finally, Table 6 compares the proposed filter with some previous filters. The versatile universal filters in [35], [36], biquad-based high-frequency high-order filters in [37], [38], biquad-based low-power high-order filters in [39], and  low-voltage low-power universal filters in [23], [40] have been used for a comparison. It is evident that the proposed filter offers the highest number of filtering functions (i.e. 23),   resistorless topology, electronic control of ω o , and, with one exception from [23], the lowest voltage supply and power consumption. The figure-of-merit (FOM), dynamic range and low-voltage (LV) capability of the filters have been also considered in Table 6. It is notable that the proposed filter and the one in [23] are the only filters that offer 100% LV operation capability (V TH /V DD ). Although the filter in [38] shows better DR and FOM, this filter along with those in [37], [39] offer only low-pass function. Furthermore, the filters in [37], [38] use power-hungry structures with much higher voltage supply, making them inappropriate for extremely low-voltage low-power applications. Compared with the low-voltage low-power filters in [23], [39], [40], the proposed filter has better LV operation capability than the filters in [39], [40] and better FOM than the filter in [23].

VI. CONCLUSION
This paper presents an innovative structure for DDTA based on bulk-driven multiple-input DDA followed by bulk-driven transconductance amplifier capable to work under 0.5 V supply voltage. The DDA structure employs two PPFs, which results in high performance parameters. Bulk-driven techniques along with MI-MOST increase the input voltage range of the circuit. The universal filter application employs 3 DDTAs and two grounded capacitors with low value for circuit integration. The simulated results confirm the futures of the design.