Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics

For the first time, device design guidelines for a 3-nm node complementary field-effect transistor (CFET), which vertically stacks n-type and p-type nanosheet MOSFETs with a shared gate, are investigated using calibrated 3-D technology computer-aided design (TCAD). Here, the optimal device dimensions of the CFETs for better inverter performance and thermal characteristics are studied. The electrothermal performance are investigated for various vertical dimension parameters of CFET, such as the number of stacked channels, vertical distance between nanosheet channels (D<sub>nsh</sub>), distance of n/pMOS separation (D<sub>n/p</sub>), and channel thicknesses (T<sub>nsh</sub>). The results show that, unlike conventional CMOS, the reduction of D<sub>nsh</sub> and D<sub>n/p</sub> of CFET can effectively improve inverter performance without severe thermal degradation, although other dimensional parameters trigger a severe trade-off between different electrothermal parameters. The reduction of D<sub>nsh</sub> and D<sub>n/p</sub> decreases C<sub>eff</sub> with a lower metal via the height and gate fringing effect. However, the reduction in D<sub>nsh</sub> and D<sub>n/p</sub> does not change R<sub>eff</sub>; therefore, both the operation frequency (<inline-formula> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula>) and power-product delay (PDP) can be improved. In the case of thermal characteristics, the reduction of D<sub>nsh</sub> and D<sub>n/p</sub> slightly increases both T<sub>max</sub> and R<sub>th</sub> because of thermal coupling but is negligible. Therefore, the reduction of D<sub>nsh</sub> and D<sub>n/p</sub> will be a key technique for the development of sub-3-nm CFET.


I. INTRODUCTION
Conventional FinFETs, which have recently been scaled down to 5-nm nodes, have almost reached physical limits in reducing fin thickness [1]. Thus, to improve gate controllability, nanosheet FETs (NSHFETs) with gate-allaround (GAA) structures have been actively developed for sub-3-nm nodes [1]- [3]. However, they will continue to face these down-scaling limitations in the future. Therefore, to reduce the number of tracks and layout area to reduce the device footprint, the International Roadmap for Devices and Systems (IRDS) expects that a 3-dimensional structure which stacks multiple NSHFETs vertically can be a strong candidate for future technology nodes [4]- [11]. Thus, one of the most promising devices with a 3-dimensional structure, The associate editor coordinating the review of this manuscript and approving it for publication was Paolo Crippa . the complementary field-effect transistor (CFET), which stacks n-NSHFET and p-NSHFET vertically with a shared gate for CMOS inverter operation in one device, has recently been suggested by Intel, Applied Materials, IMEC, and NARLab [4]- [9]. In addition, in a recent study on CFET, it was demonstrated that CFET with NSHFET shows better inverter performance than CFET with FinFET [8].
Recently, NSHFET have been replacing FinFETs for logic devices because of higher inverter operation frequency (f ). This is owed to the lower effective resistance (R eff ) of NSHFETs due to better current drivability and gate controllability in the same footprint [1]. However, the large effective capacitance (C eff ) of NSHFETs disturbs additional improvement of f or power-product delay (PDP). Therefore, a decrement of C eff is an important factor for improving inverter performances. Furthermore, the CFET, which stacks vertically stacked NSHFETs also faces performance degradation by high C eff because of the additional height of metal via of the vertically stacked structure. Recent studies demonstrated that CFET shows the possibility for better C eff compared with conventional CMOS with NSHFETs because of fringe electric field overlap triggered by the reduced distance between nMOS and pMOS with the vertically stacked structure [4], [10]. In addition, recent fabrication processes demonstrated by Intel reduced number of metal via by connecting the drain of the nMOS and pMOS with one piece of metal via. This could additionally decrease C eff . However, CFET has a much higher height of metal via compared with conventional CMOS because of the stacked structure of the nMOS and pMOS. Therefore, there is still a risk of the degradation of C eff , and the careful design of CFET is required. Therefore, analyzing C eff and R eff of the CFET by varying dimensions is required to evaluate f and PDP [3].
In addition, it has been reported that multi-gate transistors such as NSHFETs are vulnerable to the self-heating effect (SHE) because of their confined geometry, which triggers thermal reliability issues [12]- [19]. In particular, it is expected that the high height of CFET makes it difficult for heat to dissipate to the thermal ground. Thus, finding a way to alleviate the SHE in CFET by stacking nNSHFETs and pNSHFETs is important. However, there has been no qualitative analysis of the optimal design of CFETs based on both thermal characteristics and CMOS inverter performances for different dimensions.
For the first time, the device design guideline of the 3-nm node CFET is investigated from the perspective of thermal characteristics and CMOS inverter performance with carefully calibrated 3-D TCAD. First, the CMOS inverter performances of C eff , R eff , f , and PDP in the 3-nm node CFET are analyzed by varying the dimensions of the number of stacked channels (N nMOS , N pMOS ), distance between the nanosheets (D nsh ), n/pMOS separation distances (D n/p ), nanosheet channel thickness (T nsh ), and nanosheet width (W nsh ). Moreover, the maximum lattice temperature (T max ) and thermal resistance (R th ) is evaluated in terms of different dimensions. Finally, the impact of the device design on the inverter performance and thermal characteristics is analyzed from the perspective of down-scaling.

II. MODELING METHODOLOGY
The 3-nm node CFET was designed for the front-end-ofline (FEOL) based on the IRDS 2020 high-performance specification in Sentaurus 3-D TCAD vQ 2019. The structure of CFET was based on the experimental reference of Intel [9]. Fig. 1 shows the schematics of the 3-nm node CFET. Fig. 1 (a) shows a 3-D bird's eye view of the CFET. Fig. 1 (b), (c), (d), and (e) show the cross-sectional view of the 3-nm node CFET and schematics with structural parameters. Table 1 shows the structural parameters used in TCAD, and the reference values of each parameter are underlined. For CFET, nMOS-on-pMOS structure is assumed based on [9]. The physical gate length (L g ) was set as 16 nm. For the gate oxide, 2-nm thick HfO 2 was used. In addition, gate metal, which has a work function of 4.54 eV and 4.8 eV, is used for nMOS and pMOS of CFET respectively. Fig. 2 shows schematics of the thermal parameters used in TCAD. Thermal modeling is based on the simulation setup of the conventional model suggested by [12]- [19]. As shown in Fig. 2 (a), the CFET locates on a wide silicon substrate and is surrounded by SiO 2 . Thermal boundaries are then set on the top and bottom surfaces for realistic heat dissipation modeling [12]. The thermal parameters used in the simulation VOLUME 10, 2022  are listed in Table 2. Fig. 2 (b) shows the device regions where the thermal parameters are used. Fig. 3 shows the method of calibration of the TCAD to reference for realistic simulation. The calibration of TCAD is performed for the transfer characteristic and voltage transfer characteristic (VTC) of CFET ( Fig. 3 (a) and (c)) from the experimental reference with a gate length of 75 nm [7]. This is the only fabricated CFET with vertically stacked NSHFETs that can operate as inverters with a high onstate current and low SS. Then, a 3-nm node CFET is designed using the IRDS specifications, as shown in Table 1, and the DC performances and inverter performances were calculated as shown in Fig. 3 (b) and (d) [11], [20], [21]. For device physics, models of density gradient quantum correction and inversion accumulation mobility are used to consider quantum confinement in nanoscale devices. In addition, bandgap narrowing, electric-field-dependent mobility, doping-dependent mobility, high field saturation, Shockley-Read-Hall doping dependence and band-to-band tunneling (Hurkx) were used. Parameters for respective physics are used from default value provided Sentaurus TCAD. The thermodynamic model was also applied to simulate realistic electrothermal carrier transportation with the parameters listed in Table 2 [12]- [19].  power supply voltage (V dd ) is set to 0.7 V by IRDS 2020. For the transient response, the inverter performance is calculated based on the fan-out of the 3 (FO3) logic inverter circuit, as shown in Fig. 4 (a) [20], [21]. Here, C eff is calculated from the general equation C eff = total gate capacitance (C gg ) + total drain capacitance (C dd ) + 3 (number of fanout devices) × fan-out capacitance (C fo ) [20], [21]. C fo is assumed to be the same as C gg ; therefore, C eff can be 4 × C gg + C dd . C gg and C dd are extracted from a single CFET device. Here, C gg includes the gate-to-drain capacitance (C gd ), gate-to-source capacitance of nMOS (C gsn ), and gateto-source capacitance of pMOS (C gsp ). For the performance parameters, f is extracted using the equation shown in Fig. 4 (b). Power is calculated using C eff × f × V 2 dd , PDP is calculated as power/f, and R eff is calculated as 1 / (C eff × f ) [20], [21].

III. RESULTS AND DISCUSSIONS A. INVERTER PERFORMANCE CHARACTERISTICS OF CFET FOR DIFFERENT DIMENSION PARAMETERS
To investigate the inverter performance characteristics, f , power, C eff , and R eff of the 3-nm node CFET were compared for different structures and dimensions, as shown in Figs. 5 and 6. In Fig. 5, f , PDP, C eff , and R eff for different numbers of stacked channels of nMOS and pMOS (N nMOS , N pMOS ) are compared. For N nMOS and N pMOS , N nMOS /N pMOS of 1/2, 2/3, 3/4, and 4/5 were used to compare inverter performances of the 3-nm node CFET for different N nMOS and N pMOS . For each device with N nMOS /N pMOS , the transfer characteristics of the nMOS and pMOS were calibrated to obtain the same VTC characteristics. N pMOS was chosen for a higher number than N nMOS to match the drain current, because the mobility of nMOS is much lower than that of pMOS. Fig. 5 (a) shows an optimal point that  allows the highest f to exist. This is because C eff and R eff have a trade-off relationship, as shown in Fig. 5 (b), where f is calculated as 1 / (R eff × C eff ). The increment of N nMOS and N pMOS induces a higher drive current (I drive ) because of the large effective width and reduces R eff ; however, C eff increases as the gate area and height of the metal via increase. Thus, in Fig. 5 (a), the device with N nMOS of 2 and N pMOS of 3 shows the highest f . PDP is calculated as C eff × V 2 dd in general; therefore, PDP is proportional to C eff [20], [21]. Thus, the increment in N nMOS and N pMOS triggers an increment in C eff , so PDP increases, as shown in Fig. 5 (b).
In Fig. 6, f , PDP, C eff , and R eff are compared for different values of D nsh , D n/p , T nsh , and W nsh . For D nsh and D n/p , ranges of 7-11 nm and 20-70 nm were used, respectively. In addition, W nsh and T nsh , ranging from 15 to 25 nm and 6 to 10 nm, respectively, were used. For D nsh and D n/p in Fig. 6 (a) and (c), an increase in D nsh and D n/p can reduce f and increase PDP. The changes in D nsh and D n/p rarely cause a change in R eff as the effective width is constant and I drive does not change. Therefore, C eff dominantly determines f for the changes in D nsh and D n/p . Here, the reduction of both D nsh and D n/p triggers a low C eff , as shown in Fig. 6 (b) and (d). This is because the gate fringe electric field overlap is triggered between nMOS and pMOS of the CFET with a vertically stacked structure [4], [10]. In addition, the reduced height of the metal via decreases C eff [10]. Thus, f increases with a reduction in D nsh and D n/p . Since PDP is proportional to C eff , the reduction in D nsh and D n/p can decrease PDP with lower C eff . On the other hand, in Fig. 6 (e) and (g), the device with the optimum values for T nsh of 8 nm in Fig. 6 (e) and W nsh of 20 nm in Fig. 6 (g) is required for the highest f . This is because C eff and R eff have a trade-off relationship, as shown in Fig. 6 (f) and (h). Both T nsh and W nsh are related to the effective width of the channel; thus, their increase increases the current and the gate area. Thus, a higher effective width decreases R eff , and a larger gate area increases C eff with increasing T nsh and W nsh . In addition, because of the increase in C eff , PDP increases with increasing T nsh and W nsh , as shown in Fig. 6 (f) and (h).
Furthermore, in Fig. 5 and 6, C eff changes linearly by different dimensions, but R eff changes non-linearly. The reason of R eff 's non-linearity is the impact of thermodynamic physics. Increment of current with increment of dimensions increases device temperature. The increased temperature degrades current and increases R eff . For generated heat, electron joule heat and hole joule heat are calculated by equation as follow [19]: where J n and J p are current density of electron and hole, q is charge, n and p are doping concentration, µ n and µ p are mobility of electron and hole. The ∅ n and ∅ p are the electron and hole quasi-Fermi potentials. The P n and P p are the absolute thermoelectric powers, and ∇T is lattice temperature.
In equation (2), J n and J p which considers lattice temperature affects by lattice temperature (T) which is proportional to J n 2 and J p 2 in equation (3). Therefore, non-linearity of R eff occurs by different dimensions.

B. THERMAL CHARACTERISTICS OF CFET FOR DIFFERENT DIMENSION PARAMETERS
To investigate the electrothermal characteristics, T max and R th of the CFET with different dimensions were compared. T max is the absolute value of the maximum heat generation during device operation. R th is a general parameter used to compare the heat dissipation ability from the device to the thermal ground between different devices, assuming that they have the same power [12]- [19]. Fig. 7 shows the method for extracting T max and R th . Fig. 7 (a) shows T max and the maximum I drive during inverter operation for different V in values in the range of 0 V to 0.7 V. In the case of the device temperature during inverter operation, it is well known that it finally converges to the maximum temperature of the DC if the inverter operation pulse is continuously injected. Here, the maximum value of T max was extracted to calculate T max , where T max = maximum T max − initial temperature (300 K). In addition, R th and I drive were extracted. R th shows correlations between power and temperature and is calculated by the equation below [12]- [19]: where, V dd is the power supply voltage of 0.7 V. Fig. 7 (b) illustrates the visualized lattice temperature distribution of the 3-nm node CFET.
Here, T max is located at the nMOS's lower channel and does not change with different dimensions. This is because  nMOS and pMOS have the same I drive during inverter operation, but nMOS has a lower number of stacked channels compared with pMOS, so nMOS has a relatively high current density and triggers a high temperature. In addition, nMOS's lower channel has a longer distance to the thermal ground than the other channels, and thermal coupling severely occurs [12]- [19]. Therefore, nMOS's lower channel had the highest temperature.
In Fig. 8, T max and R th are shown for different numbers of stacked channels (N nMOS and N pMOS ). For T max in Fig. 8 (a), the increment of N nMOS and N pMOS increases T max because it induces a high I drive as the currents of both nMOS and pMOS increase. However, for R th in Fig. 8 (b), the increased gate area by incrementing N nMOS and N pMOS triggers better heat dissipation, so a reduction in R th occurs. Thus, if each device has the same power, increments of N nMOS and N pMOS can dissipate heat well from the device to the thermal ground. Fig. 9 shows T max and R th for different values of D nsh , D n/p , T nsh , and W nsh . In Fig. 9 (a) and (b), the increment of D nsh and D n/p lowers both T max and R th . Here, changes in D nsh and D n/p rarely cause changes in I drive , and T max mainly depends on the ability of heat dissipation from the devices to the thermal ground, similar to R th . With an increase in D nsh and D n/p , the heat dissipation ability improves as the thermal coupling weakens because of the large distance between channels or devices, which are sources of heat. Therefore, both T max and R th decrease with increasing D nsh and D n/p . However, it is notable that the values of T max and R th for different D nsh and D n/p are much smaller than those of the other parameters and are thus negligible. In Fig. 9 (c), R th shows turn-around at T nsh = 8 nm. With increment of T nsh from 6 nm to 8 nm, impact of increment of I drive is dominant compared to the impact of increment of gate area which decide heat dissipation. Thus, increased consumed power by increment of I drive increases R th . However, for T nsh over 8 nm, the impact of the increment in the gate area becomes dominant, so better heat dissipation decreases R th . Thus, R th shows turn-around at T nsh = 8 nm. For T nsh , change of gate area is relatively small compared to other dimension parameters as range of T nsh is small from 6 nm to 10 nm, so impact of I drive can be relatively high and turn-around occurs unlike other dimension parameters. In Fig. 9 (d) of W nsh , the increment of W nsh increases T max because it induces a high I drive . However, an increased gate area triggers better heat dissipation, and thus, a reduction in R th occurs.
Considering both inverter performance and thermal characteristics, it is notable that the reduction in D nsh and D n/p of CFET can improve f and PDP without significant degradation in T max and R th .

IV. CONCLUSION
For the first time, the inverter performance and thermal characteristics of a 3-nm node CFET with different dimensions were investigated using calibrated 3-D TCAD. In addition, device design guidelines for CFETs to achieve better inverter performance and thermal characteristics were suggested. First, inverter performances by different N nMOS , N pMOS , D nsh , D n/p , T nsh , and W nsh were investigated. For N nMOS and N pMOS , with a reduction in the above parameters, C eff decreases because the gate area decreases and the height of the metal via is reduced. However, R eff increases with a decrease in the effective width. Therefore, an optimum N nMOS /N pMOS ratio of 2/3 is required for the highest f as a trade-off between C eff and R eff . For D nsh and D n/p , their reduction decreases the height of the metal gate and source/drain metal via, thereby reducing C eff without changing R eff . Thus, the reduction of D nsh and D n/p can increase f and decrease PDP. Subsequently, the thermal characteristics by different N nMOS , N pMOS , D nsh , D n/p , T nsh , and W nsh were investigated. For the different N nMOS and N pMOS , their reduction decreases the gate area and disturbs the heat dissipation from the devices to the thermal ground, thereby increasing R th . In the case of D nsh and D n/p , their reduction induces a higher R th because of severe thermal coupling, but the change in R th is negligible. Considering both inverter performance and thermal characteristics from the perspective of down-scaling, it is notable that the reduction in D nsh and D n/p of CFET can improve both f and PDP without severe degradation. This is different from the other dimension parameters, which show a severe trade-off between inverter performance and thermal parameters. This study can provide crucial insights into the device design of CFET for a sub-3-nm node.

ACKNOWLEDGMENT
The EDA tool was supported by the IC Design Education Center, South Korea.