Reconfigurable and Storable Chaotic Logic Operations in Drive-Response VCSELs with Optical Feedback

Based on the system of drive-response vertical cavity surface emitting lasers (VCSELs) with optical feedback and the new electro-optic (EO) modulation theory, we propose a novel reconfigurable and storable logic operations scheme to perform the behaviors of flexible switching and delayed storage among different logic operations. Here, the optical feedback intensity is modulated into logic input, the applied electric field in drive system and response system are modulated into logical control signals, the logic output is decoded by threshold mechanism. When the logical control signal in drive system and response system remain equal and both of them satisfy different logic operation relationships with the logic inputs, the system can perform the mutual conversion and delayed storage among the logic operations such as AND, NAND, OR, NOR, XOR and XNOR. Furthermore, the half adder logic operations are also being realized. Finally, the influence of bit duration time and noise intensity on the reliability of the logic operations is analyzed, and the results indicate that the logic operations have good anti-noise performance.


I. INTRODUCTION
It is well known that the chaotic laser signal is not only extremely sensitive to the initial conditions of the system and external interference, but also has the characteristics of aperiodic and high randomness, which makes it widely used in the field of optical communication, such as high-speed physical random number generators, high-speed key distribution and signal carrier, etc. In recent years, optical chaotic logic operations based on semiconductor laser has attracted widespread attention since it provides a scheme to realize reconfigurable logic operation, where different logic operations such as AND, OR, XNOR, NAND, NOR, XOR, etc., are flexibly converted by the slight change of the parameters in a chaotic system. And optical chaotic logic operations are the most critical technology in future optical chaotic network secure communication, however, the technology of the optical chaotic logic operations still lags behind. For most of the logic processing of optical chaotic signals, such as multiplexing, demultiplexing, switching, regeneration, storage and calculation, it is necessary to implement all-optical chaotic logic devices and sequential logic ones with low power consumption and high speed. Compared to edge emitting laser, vertical cavity surface emitting laser (VCSEL) exhibits many advantages such as large modulation bandwidth, low threshold current, round beam output and easy coupling with fiber, etc.
[1]- [4]. Under the conditions of external light injection or bias current injection, the VCSEL is easy to emit mutually orthogonal chaotic x-polarized light (x-PL) and chaotic y-polarized light (y-PL), and it can also exhibit rich dynamic behaviors such as polarization switch and polarization bistability [5]- [14]. Based on the dynamic characteristics of VCSEL's polarization bistability, the C. Masoller's research group successfully implemented stochastic logic gates with different technical schemes [1], [2], [15]. In 2013, Yan put forward a feasible plan to implement all-optical logic gates based on "master-slave-response" synchronization system of chaotic multiple-quantum-well lasers [16]. In 2015, Zhong's team obtained optoelectronic composite logic gates based on electro-optic (EO) modulation theory and the VCSEL subjected to external optical injection [17]. In 2016, all-optical stochastic logic gates and their delay storages were successfully implemented based on generalized chaotic synchronization and polarization switch in system of the cascaded VCSELs with optical-injection [18]. In 2017, based on polarization bistability, the reconfigurable all-optical chaotic logic gates were firstly being successfully realized by the scheme for VCSEL subject the injection of light from tunable sampled grating distributed Bragg reflector laser [19]. In 2020, my research group use a simple technical scheme for the VCSEL subject the optical feedback to implement the reconfigurable optoelectronic chaotic logic gates [20]. Next year, a novel scheme for the reconfigurable optical chaotic logic operations with fast rate of picoseconds scale were proposed in our laboratory [21].
However, the most of logic operations implemented by the above schemes are static, the development of dynamic and reconfigurable chaotic logic operations are still in the initial stage. Since the VCSEL with external optical feedback or external optical injection, as a nonlinear system with high dimension has rich nonlinear dynamic behaviors, it is great prospect that reconfigurable chaotic logic operations are implemented. In this paper, we put forward a novel implementation scheme for reconfigurable and storable chaotic logic operations in a chaotic polarization system of drive-response VCSELs with optical feedback. And the half adder logic operations can also be performed based on this system. Finally, the reliability of logic operations is further analyzed.  The composition of the drive-response system and detailed light path are displayed in Figure 1. In the drive system, the light emitted by D-VCSEL first passes through the isolator 3 (IS 3 ), and then is separated into x-PL and y-PL by polarization beam splitter 2 (PBS 2 ). The x-PL passes through the light intensity meter 1 (LIM 1 ) and then is divided into two beams by beam splitter 2 (BS2). One beam of the x-PL is feedback into the periodic poled LiNbo 3 1 (PPLN 1 ) crystal by the plane mirror 1 (M 1 ), M 2 and M 6 in the feedback cavity, and the other beam of x-PL is directly injected into the PPLN 2 crystal. The y-PL from PBS 2 is divided into two beams by BS 1 . One beam of y-PL is reflected by M 3 , M 4 , M 5 and then passes through the faraday rotator 1 (FR 1 ) and half wave plate 1 (HWP 1 ), and finally is injected into the PPLN 1 crystal. The other beam of y-PL is directly injected into the PPLN 1 crystal through FR 2 and HWP 2. The above FR and HWP are mainly used to convert the polarized direction of y-PL to the z-axis direction of the crystal. The x-PL and y-PL injected into the crystal are regarded as the initial input of o-light and e-light respectively. The electric fields applied to PPLN 1 and PPLN 2 are denoted by E 1 and E 2 , respectively. The x-PL and y-PL from the PPLN 1 crystal (e-light is converted into y-PC by FR 2 and HWP 2 ) pass through IS 1 and IS 2 respectively, and then are injected into PBS 1 together. The light output from PBS 1 is divided into two beams by BS 3 , and then these two beams are injected into D-VCSEL through polymer tunable diffraction grating variable attenuator 1(VA 1 ) and VA 2 , respectively. The x-PL and y-PL from the PPLN 2 crystal pass through IS 4 and IS 5 respectively, and then are combined by PBS 3 into a beam of light, which is injected into the R-VCSEL through VA 3 .

II. THEORY AND MODEL
In order to implement dynamic switching between different logic operations, the logical control signal needs to meet the different logic operation relationships with the logic inputs synchronously. To solve this problem, we give the following technical solutions: the time-varying current source S 1 and S 2 output the current u 1 , u 1 ', u 2 and u 2 '. Here, the current u 1 and u 2 , in turn, are encoded into two electric logic inputs of the field programmable gate array (FPGA) such as i 1 and i 2 . Because the polymer tunable diffraction grating VA is controlled by the current, the optical feedback intensity k f1 and k f2 are determined by u 1 ' and u 2 ' respectively (see Fig. 1). Here, the k f1 and GELIANG XU et al: Reconfigurable and Storable Chaotic Logic Operations in Drive-Response VCSELs with Optical Feedback VOLUME XX, 2017 1 k f2 are encoded into optical logic inputs I 1 and I 2 , respectively. Due to u 1 =u 1 ', u 2 =u 2 ', the logic sets of the signals i 1 and i 2 are synchronized with those of the signals I 1 and I 2 . The two logic outputs of the FPGA are defined as Y 1 and Y 2 , which respectively control the E 1 and E 2 .
Using the FPGA, Y 1 and Y 2 both can perform different logic operations with i 1 and i 2 , so that C D and C R can implement different logic operations with I 1 and I 2 indirectly. The D-VCSEL in the drive system is injected by the light from the PPLN 1 crystal, its rate equations are derived as: Similarly, the rate equations of the R-VCSEL in the response system can be expressed as: In the above rate equations, the subscripts x, y, D, and R respectively mean the x-PL, y-PL, D-VCSEL and R-VCSEL; E represents the complex amplitude of light; N is the total carrier concentration; n is the difference in concentration between carriers with spin-up and carriers with spin-down; k f represents the optical feedback intensity;  1 is the round-trip time in the external cavity;  2 is the propagation time of light from the PPLN 2 to the R-VCSEL;  0 represents the center frequency of D-VCSEL and R-VCSEL; ζ x and ζ y are a pair of gaussian white noises that are independent of each other and obey the standard normal distribution. E Px1 and E Py1 are the complex amplitudes of the x-PL and y-PL output from the PPLN 1 crystal; similarly, E Px2 and E Py2 are the those of x-PL and y-PL from the PPLN 2 crystal. The meanings and values of other physical parameters are presented in Table  I below. Considering the x-PL and y-PL from D-VCSEL as the original inputs of the o-light and the e-light in PPLN 1 crystal, respectively, we have 11 0 ,, In where t 0 = 1 or 2 , the meanings and mathematical expressions of other physical parameters are present in Ref. [18]. When the D-VCSEL are subject to the injection of the output x-PL and y-PL from the PPLN 1 crystal, we have: Similarly, while the output x-PL and y-PL from the PPLN 2 crystal are injected into the R-VCSEL, we obtain

IIl. RESULTS AND DISCUSSION
Here, we suppose that the optical feedback intensity equals to the sum of two square waves that encode the two logic inputs, i.e., k f =k f1 +k f2 . Here, the logic input for the optical feedback intensity k f1 is defined as I 1 , and that for the optical feedback intensity k f2 is defined as I 2 . In this case, there are four logic input sets: (0, 0), (0, 1), (1, 0), and (1, 1). Representing the (0, 1) and (1, 0) with the same optical feedback intensity k fII , we can encode the four inputs with the three-level signals k fI , k fII , and k fIII , where k fI accounts for the set (0, 0), and k fIII represents the set (1, 1). The three-level signal used to vary k f is constant during a time interval T, defined as the bit duration time. We suppose that I 1 =I 2 =0 when k f1 =k f2 =0.56ns -1 (k fI =1.12ns -1 ); when k f1 =k f2 =0.57ns -1 , I 1 =I 2 =1 (k fIII =1.14ns -1 ); I 1 =0, I 2 =1 if k f1 =0.56ns -1 and k f2 =0.57ns -1 (k fII =1.13ns -1 ), similarly k f1 =0.57ns -1 , k f2 =0.56ns -1 (k fII =1.13ns -1 ) indicate that I 1 =1, I 2 =0. The applied electric field E 1 and E 2 in drive-response system are modulated into the logical control signal C D and C R respectively, it means that, if E 1 =E 2 =E 01 =0.3kV/mm, C D =C R =0; else if E 1 =E 2 =E 02 =0.75kV/mm, C D =C R =1. The logic output X 1 of the drive system is demodulated by the difference between the average value A D of the x-PL intensity from the D-VCSEL and the threshold A T ; similarly, the logic output X 2 of the response system is demodulated by the difference between the average value A R of that from the R-VCSEL and the threshold A T . Namely, if A D -A T >0, X 1 =1, else X 1 =0; in the same way The threshold value A T determines the reliability of the logic operations. In order to obtain a suitable threshold, we adopt the following technical solutions: since C D and C R can perform different logic operations with I 1 and I 2 by FPGA, such as AND, OR, XOR, etc. For different cases of logic operation C D, R , we have calculated the maximum value A Dmax of A D when C D =0, and the minimum value A Dmin of that under C D =1. The maximum value A Rmax of A R when C R =0, and the minimum value A Rmin of that under C R =1 also have been calculated. The specific calculation results are displayed in table Ⅱ. From the table, we obtain that the maximum value of A Dmax equals to 0.0053, and the minimum value of A Dmin equals to 0.016. Therefore, the threshold A T needs to satisfy the following condition: 0.0053<A T <0.016. Hence, we take A T as 0.01, that is, if A D <0.01 and A R <0.01, X 1 =X 2 =0; else X 1 =X 2 =1 when A D >0.01 and A R >0.01.   The system can realize different logic operations when the logical control signal meets different logic operation relationships with the logic inputs. In this paper, relying on FPGA to convert the logic operation relationships between the logical control signals C D (C R ) and I 1 , I 2 , the response system has the same logic outputs as the drive system when C R remains equal to C D , i.e., X 2 (t) = X 1 (t- 2 + 1 ), so as to realize the reconfigurable and storable logic operations. Figure 2 shows the numerical simulation results of logic operations. The blue dotted line in Fig. 2(a) represents the applied electric field E 1 (encoded into C D ), and the red dotted line represents the three-level signals k fI , k fII and k fIII (encoded into the logic inputs), the solid black line in Fig. 2(b)  obtained by the threshold mechanism as shown in Fig.  2(c). From Figs. 2(a), 2(b) and 2(c), it is found that when the noise intensity β sp is 2 × 10 9 , the different logic operations at different time periods can be implemented, controlling the logic operation between C D and two logic inputs. For example, if C D =I 1 •I 2 when the time t is between 10 ns and 50 ns, we obtain the logic AND operation, i.e., X 1 =I 1 •I 2 ; while t is between 50 ns and 90 ns, the logic OR operation can be performed when C D =I 1 +I 2 , i.e., X 1 =I 1 +I 2 ; with t varying from 90 ns to 130 ns, X 1 = I 1 ⊙I 2 if C D = I 1 ⊙I 2 , the logic output is logic XNOR operation; In the case that D = 1 • 2 ̅̅̅̅̅̅̅ , the logic output is of logic NAND operation, i.e., 1 = 1 • 2 ̅̅̅̅̅̅̅ , and when 130 ns≤t≤170 ns; If D = 1 + 2 ̅̅̅̅̅̅̅ , it is converted into the XNOR operation, i.e., 1 = 1 + 2 ̅̅̅̅̅̅̅ in the time period from 170 ns to 210 ns. Finally, with t being between 210 ns to 250 ns, the logic output is further converted into logic XOR operation due to the fact that C D =I 1 ⊕I 2 . When the logical control signals C D and C R remain equal at all times, the logic operations performed by the response system are the same as that of the drive system, as shown in Figs. 2(d), 2(e) and 2(f), indicating that the system has the ability to reconstruct and store logic operations.
Controlling the logic operation between the logical control signals and two logic inputs, the reconfigurable and storable logic operations such as XOR, AND, XNOR, OR, NAND and NOR are further implemented as shown in Fig. 3.
Depending on FPGA, we have C D = I 1 •I 2 and C R = I 1 ⊕ I 2 (see Figs. 4(a) and 4(d) ) at the same time, thus the drive system can implement the logic AND operation, i.e., X 1 = I 1 •I 2 , and the response system can realize the logic XOR operation, i.e., X 2 = I 1 ⊕I 2 , as shown in Figs . 4(b), 4(c), 4(e) and 4(f). Therefore, the half adder logic operations are also successfully implemented.

FIGURE 3. Reconfigurable chaotic logic operations and their delayed storage
The reliability of logic operations depends strongly on some system parameters. In the following we calculate the success probability P 1 and P 2 (as the ratio between the number of correct bits to the total number of bits) to quantify the reliabilities of the logic operations performed by the drive system and the response system, respectively. Here, we take the logic operations shown in Fig. 2 as an example to calculate the evolutions of P 1 and P 2 in the space of noise intensity β sp and bit duration T, as shown in Fig 5. It is found that the area of P 1 <0.8 in Fig. 5(a) accounts for a larger proportion when T varies from 0ns to 1ns, indicating that the reliability of logic operations is poor; As T gradually increases from 1ns to 2ns, the area with P 1 >0.9 accounts for a larger proportion, denoting that the reliability of logic operations is enhanced; when T continues to increase from 2ns to 10ns, the proportion of the area with P 1 =1 increases rapidly. It can also be seen that as the noise intensity β sp increases from 0 to 4×10 9 , the proportion of area with P 1 =1 is gradually shrinking, showing that reliability is slowly getting worse. The evolution trajectory of P 2 in Fig. 5(b) is similar to that of P 1 in Fig. 5(a).
In order to show the local changes of P 1 and P 2 in Fig.  5 in more detail, we further analyze the dependence of the success probability on the β sp for different T, as displayed in Fig. 6. As we can see from the Fig. 6(a) that if T=4ns, the value of P 1 is always equal to 1 when 0<β sp <1×10 9 , which indicates that the reliability of the logic operations is strong, and no error appeared in logic outputs; as β sp exceeds 1×10 9 , the value of P 1 begins to fluctuate, but is still above 0.9. When 0<β sp <3.75×10 9 , the P 1 is always equal to 1 if T=8ns, denoting that the logic operations are of reliability and stability; P 1 varies in a small range when β sp exceeds 3.75×10 9 , the reliability of the logic operations gets slightly worse. When β sp varies from 0 to 4×10 9 , the logic operations are so reliable that P 1 is always equal to 1 if T=10ns. From Fig. 6(b), one sees that value of P 2 oscillates severely with β sp increasing if T=4ns. When β sp increases from 0 to 2.7×10 9 , the value of P 2 always equals to 1 since T=8ns; with β sp further increasing from 2.7×10 9 to 4×10 9 , P 2 begin to fluctuate. The β sp within the range of 4×10 9 will not cause errors to the logic outputs due to the P 2 is always equal to 1 when T=10ns.
From the above results, it is concluded that the success probability P 1 and P 2 for logic operations implemented by the drive system and response system respectively are seriously dependent on the noise intensity β sp and bit duration time T. The values of P 1 and P 2 will become small and unstable if the value of T is too small or the value of β sp is too large. It is noted that the logic operations are highly reliable that both P 1 and P 2 are always equal to 1 under appropriate conditions such as T=8ns and β sp <2.7×10 9 , or T=10ns and β sp within the 4 ×10 9 .

Vl. CONCLUSIONS
We propose a novel reconfigurable and storable chaotic logic operations scheme by using the drive-response VCSELs with optical feedback, based on the EO modulation theory. Here, the optical feedback intensity is modulated into logic input, the applied electric field in drive system and response system are modulated into logical control signals, and logic outputs are demodulated by the threshold mechanism. Relying on FPGA to convert the logic operation relationships between the logical control signals and logic input, the system can perform the reconfigurable and storable processing of logic operations. Furthermore, the system can also implement the half adder logic operations when the chaotic logic AND and XOR operations are performed by the drive system and the response system, respectively. It is noted that the bit duration time and noise intensity have an impact on success probability of logic operations. And the reliability of logic operations are so strong that the success probability can be always equal to 1 even though the noise intensity is as high as 4×10 9 , indicating that the logic operations have good anti-noise performance. These results have potential application in the reconfigurable and storable chaotic logic computing system with high speed, security and low power cost.