Single-Stage Injection-locked Frequency Sixtupler in CMOS Process

High multiplication-factor even-modulus frequency multipliers are often configured as multi series frequency multipliers. This paper designs a single-stage LC-tank injection locked frequency sixtupler (ILFS) fabricated in 0.18 μm CMOS process and the ILFS merges many sub-circuits in one by sharing a common supply and passive inductive elements. The circuit design, operation principle and measurement results of the ILFS are addressed. The differential input and single-phase output ILFS circuit is made of two frequency doublers, a first-harmonic injection-locked oscillator and an active frequency tripler using one frequency doubler. The free-running frequency of the ILO is around 5.716 GHz. At the dc power consumption of 20.9 mW and at the incident power of 0 dBm, the ×6 input locking range is from the incident frequency 0.94 GHz to 1.02 GHz to provide an output signal source from the frequency 5.64 GHz to 6.12 GHz. The whole chip occupies a die area of 1.141×1.2 mm2. Other high multiplier factors are also measured on the designed chip.


I. INTRODUCTION
Frequency multipliers (FMs) are often used in wireless transceivers or radar systems, converting a low frequency signal into a high frequency signal. LC-type frequency multipliers have been formed in active frequency multipliers with filters, multiple-push harmonic voltage-controlled oscillators or injection-locked frequency multipliers (ILFMs). High-even multiplier factor frequency multipliers may consist of two frequency multipliers as well as amplifiers. Times six multipliers are probably made up of a frequency tripler (FT), a buffer amplifier, and a frequency doubler. The active frequency sixtupler [1]- [5] comprises of a first frequency tripler, a buffer amplifier, a second frequency doubler and an output power amplifier. A frequency tripler may use the concept of nonlinear amplifier or mixing first and second harmonics to generate third harmonic [6]. An integrated frequency sixtupler [7] can be composed of a nonlinear differential amplifier used as a frequency tripler followed by a Gilbert mixer used as a frequency doubler. The 2 nd sixtupler design approach [8] uses a two-stage approach. The first stage is an even-order harmonics generator and the second stage mixes the 2 nd and the 4 th harmonics, to generate the desired 6 th harmonic. A CMOS frequency sixtupler chain [9] uses a frequency tripler in front of a frequency doubler in the transmitter.
A CMOS two-stage injection-locked frequency sixtupler (ILFS) [10], [11] as shown in Fig. 1(a) uses a single-FET frequency tripler in front of an injection-locked oscillator (ILO) as a push-push frequency doubler, the FT FET biased at the pinch-off voltage uses filters as the load, this filter approach is a narrow-band approach, otherwise harmonics are injected to the ILO. The property of this sixtupler such as phase noise is not characterized. The 6 th harmonic signal is obtained from the ILO common inductor node based on the push-push technique, it suffers from low output voltage amplitude [11]. Fig. 1(a) and Fig. 1(b) show two block diagrams of conventional two-stage ×6 ILFS. A ×6 ILFS as shown in Fig. 1(a) can be configured as an active frequency tripler and an injection-locked frequency doubler. Combining an independent frequency doubler and an ILO forms an injection-locked frequency doubler with large output signal. The ×6 ILFS in Fig. 1 doubler [12], [13]. Combining an active frequency tripler and an ILO forms an injection-locked frequency tripler. On the other hand, the order of two sub-circuits in Fig. 1(a) and Fig.  1(b) can be rearranged. Fig. 1(c) shows a sixtupler [14] by interchanging the order of two sub-circuits in Fig. 1(b). Active frequency multipliers in Fig. 1(a) ~ Fig. 1(c) can be replaced by ×n ILO to form frequency sixtupler circuits. Rigorously speaking, the previous circuits fall in the categories of active frequency multipliers and ×2, ×3 ILFMs. A PLL with a ×6 FM [15] is used to boost the frequency of output signal and Fig. 1(d) shows a PLL with a ×6 ILFM to increase the frequency of output signal. A ×6 ILFM can be formed with an active ×6 FM, followed by a balun and an ILO to boost the output signal strength. The output locking range is limited by the output signal strength of the ×6 FM. This paper proposes a new single-stage injection-locked frequency sixtupler, which combines an injection-locked frequency doubler and an injection-locked frequency tripler in one, both sub-circuits share the same injection-locked oscillator (ILO). As compared to the frequency multiplier chains, the single-stage ILFS approach simplifies circuit design because of reduced circuit component numbers and no frequency misalignment between ×3 FM and ×2 FM stages. Secondly, it has large conversion gain at low injection power. By using a new balanced frequency doubler, large ×6 output amplitude is obtained enabling driving a next stage.

II. CIRCUIT DESIGN
The ILFS can be arranged in two ways. The first one uses a balun before frequency doubler, a balun after the doubler and an ILFT, and the second one uses a balun before a frequency tripler, an ILFT and a frequency doubler. Since the latter can merge the ILFT and the doubler in one circuit, it is the simpler ILFS structure used in this study. Fig. 2(a) shows the proposed single-stage sixtupler consisting of an LC resonator, a negative resistance circuit (-ROSC=-2/gm, gm : transconductance of M1), a frequency tripler and a frequency doubler. M1, M2, C1, C2, R3, and R4 act as a negative resistance generator, which forms an oscillator with the resonator composed of L1, L2, L3 and a parasitic capacitor CT. VOLUME XX, 2022 9 The size and bias of M1 affect the value of ROSC. A frequency tripler (FT) can be constructed by an isolated frequency doubler followed by a mixer [16]. Here, L6, M3 and M4 construct a mixer-based frequency tripler [17], they act concurrently as a frequency doubler and a frequency tripler. A differential injection signal is applied to the gates of M3 and M4, even-order (2 nd & 4 th ) harmonics existing in the FET currents are added in phase at the common FET source and the odd-order harmonics are suppressed due to 180 o phase difference. Thus the common node VL6 of L6, M3 and M4 generates a 2 nd /4 th harmonic of injection signal and the drains of M3 and M4 as mixers contain a 3 rd harmonic of injection signal by mixing the even-harmonic source signal and the gate input signal. The multiplier-by-3 (FT) input/output frequency relation of the injection mixer [11] is given by ωRF +2ωRF=ωo, where ωRF/ωo is the frequency of injection source/FT output. Alternatively, an additional FT input/output frequency relation of the injection mixer is given by 4ωRF-ωRF =ωo, where 4ωRF is self-generated at the common node of L6, M3 and M4. The oscillator and the FT form an injection-locked frequency tripler (ILFT). M7 and M8 are output buffers for the 3 rd harmonic extraction. Under the locking condition, the drain voltage signal of M3 (M4) is the 3 rd harmonic of injection gate signal, the mixing in M3 (M4) yields the 2 nd harmonic and 4 th harmonic source voltages. The injection self-induced even-harmonics at VL6 enhance the strength of the 3 rd drain harmonic and locking range. L4 and L5 are used to increase the locking range. The previous injection-locked frequency sixtupler [11] uses the architecture shown in Fig.  1(a) with an FT, buffers and injection locked frequency doubler, this circuit doesn't use the injection self-induced harmonic to enhance the locking range because the buffers block the feedback signal to the pregenerator. In the twostage ILFS [11], the FT output frequency must falls in the input locking range of ILO, the load filter of the FT and the load tank of the push-push doubler are concurrently designed to ensure wide locking range. The designed single-stage ILFS uses one ILO and one active frequency doubler, no frequency alignment problem is encountered, because the doubler always tracks the output frequency of the ILFT. M5 and M6 form a new balanced frequency doubler by taking the inputs from the ILO outputs via dc blocking capacitors C3 and C4, and the common source of M5 and M6 outputs a 6 th harmonic of injection signal. R5, and R6 are biasing resistors and VB1 is the gate bias. M9, R7 and C5 form an output buffer for the sixth harmonic extraction. In Fig. 2(a) CP is the parasitic capacitor due to the source-body diodes of M5 and M6. The new frequency doubler consumes no dc power and doesn't increase the voltage headroom. Fig. 2 show two reference ×6 ILFMs adapted from Fig. 2(a) by reconfiguring the frequency doubler. Both circuits tap the voltage V6 as the output signal. The 1 st one in Fig. 2(b) normally has smaller voltage swing and it relies on the resonator connected to the V6 node, and M1 and M2 supplies the 6 th harmonic current to generate the desired sixtupler output signal. The 2 nd one in Fig. 2(c) increases the voltage headroom caused by the current reused frequency doubler FETs M5 and M6 with biased gates. This frequency doubler accepts ILO output voltage to generate the 6 th harmonic current by biasing M5 and M6 in the class C mode. Fig. 2(a)-Fig. 2(c) use different push-push techniques to build the frequency doubler. Fig. 3(a) shows simulated voltage waveforms of injection-locked frequency sixtupler and it explains that the circuit contains the fundamental, second harmonic, third and sixth harmonics. The input signal is at ωo, the self-induced signal of M3 source is at 2ωo, the self-induced signal of M3 drain is at 3ωo, and the self-induced output signal of M9 drain is at 6ωo. The ILO push-push node VS6 (VD6, VL6) also contains a 6 th harmonic which is much smaller in amplitude than the sixth harmonic at the common node of M5 and M6. Fig. 3(b) shows simulated current and voltage waveforms to explain the operation function of the balanced frequency doubler. The gate terminal of one transistor is connected with current reused frequency doubler FETs M5 and M6 with biased gates. This frequency doubler accepts ILO output voltage to generate the 6 th harmonic current by biasing dynamically M5 and M6 in the class AB mode. According to Fig. 3 at VDD = 1.1 V, and VB1 = 1.7V, M5 and M6 is dc-biased in the linear mode. The drain current of each transistor from the common node M5 and M6 to the supply node shows one peak for each period while the ILO output voltage shows one voltage peak and the frequency doubler pair M5 and M6 provides an output voltage with two peaks. In Fig. 2(a), the gate voltage of M5 can be described by VB1 +Acos(3ωot), where A is the voltage amplitude and the source voltage of M5 is given by VDD -Acos(3ωot). When the dynamic gatesource voltage VGS is above the threshold voltage VTH, and when the drain voltage of M5 is low, M5 is on and CP dumps the charges on CP and VS6 goes down. When the drain voltage of M5 is higher than VS6, CP sinks the charges from VOLUME XX, 2022 9 and M6 is a virtual ground for the 3ωo harmonics. According to the simulation, the 6 th harmonic voltage V56 is significantly larger than VS6 and VD6, this is a merit of the proposed circuit to be used as a frequency sixtupler. According to the simulation under the bias condition as Fig. 3(b) when the load at VO3 varies from 50 Ω to 250 Ω, the free-running oscillation frequency foscS6 in the ILFS output is almost unchanged, because the node VS6 is a virtual ground. When the operating temperature varies from -20 o C to 50 o C, the free-running foscS6 in the ILFS output varies from 6.94GHz to 6.96 GHz. The free-running ILFS is robust to ambient variation. The locking range of a parallel RLC-tank ILO as shown in Fig. 4(a) around a resonant frequency is derived as [18]: The fundamental current Iinj to the LC tank is from injection mixer, and the fundamental oscillation current Iosc comes from the switching FET to the tank. The locking range is given by 2 ∆ωRFLR. In Fig. 4(a) R/C represents the equivalent resistance/capacitance due to the frequency doubler and injection FETs. The output phase noise of ILFT can be modified as [19] where ωm is the offset frequency and ωp is a parameter of injection source and the ILFT circuit. RFin n S , and ILFT no S , are respectively the phase noise of the injection source and the equivalent output noise due to the free-running ILFT. The output phase noise of an ILFS due to two independent noise sources is as follows: Suppose the ac drain-body and gate-body voltages of injection FET are respectively given by (4) where vda/vRF is the amplitude of the drain/gate voltage component,  3 and  are phases. The drain current is given by VL6 is the multiplication of the drain current (5) and the impedance associated with L6. gm is the drain current expansion coefficient. Under the injection-locked condition, ωRF=ωo, VL contains the signals at 4ωo and 2ωo, which mix VOLUME XX, 2022 9 with the injection voltage to generate the 3 rd harmonic injection current. The turn-on of cross-coupled FETs M1, M2 increase the drain voltage swing of M1, M2, so that the voltage swing of even-harmonic VL6 increase, and the selfinduced harmonic increases the locking range. The size of M5 and M6 and gate bias VB1 are used to optimize the circuit performance. At VDD = 0.9 V and VB1 = 1.7 V, the free-run ILO oscillation frequency is 3.47 GHz. The simulated output locking range at 0 dBm input power is from 6.6 GHz to 7.62 GHz as shown in Fig. 4(b). M5 and M6 can be modeled as a channel resistor in shunt with parasitic capacitor. Decreasing the channel width of M5 and M6 increases the channel resistance and reduces the parasitic capacitance, this increases the free-run ILO oscillation frequency as shown in Fig. 4(b) and increases the output ILO strength and the locking range decreases because of increasing resonator Qfactor. As VB1 decreases from 1.7 V, the ILO voltage swing increases but the ×6 output power strength decreases and the locking range decreases too. If the channel width of M5 and M6 and gate bias VB1 are too large, the ILO can't oscillate, because the ILO outputs are shorted. Simulation shows the gate bias VINJ of M3 and M4 increases from 0.4 V to 0.85 V, the locking range increases and the power consumption increases too.

III. MEASUREMENT RESULTS
The ×6 ILFM has been designed and fabricated in the TSMC 0.18 μm 1P6M CMOS technology. The die micrograph occupying an area of 1.141×1.2 mm 2 is shown in Fig. 5. The three left-hand side inductive passives are for the frequency tripler, while the right-hand side inductive passives are for the ILO. Die measurement was carried on PCB using Agilent signal generator NS183A, KRYTAR's 3 dB 180 Degree Hybrid and Agilent spectrum analyzer E4407B. Fig.  6(a) shows measured free-run spectrum of ILO buffer output. The carrier is at 2.88 GHz. Fig. 6(b) shows measured locked spectrum of ILO buffer output, the output contains the 1 st , 2 nd , 3 rd and 4 th harmonics. The former is the leakage caused by the layout in the PCB and IC asymmetry. The 2 nd and 4 th harmonics are the mixing by-products. Fig. 7(a) shows measured ×3 input sensitivity measured from ILO buffer output Vo1+. At VDD = 1 V and 0 dBm input power, the output locking range is from 2.72 GHz to 3.56 GHz. Fig. 7(b) shows measured phase noises of the locked ×3 circuit and the injection signal at finj = 0.976 GHz. The locked phase noise at 1MHz is greater than the injection signal by 8.92 dBc/Hz at 1 MHz offset frequency. Fig. 8(a) shows measured free-run spectrum of ILFS output buffer, the carrier is at 5.75 GHz and its output power is -11.15 dBm. Other harmonics are smaller than the carrier by more than 21.46 dBm. Fig. 8(b) shows measured locked spectrum of ILFS buffer output, it contains more harmonics than those shown in Fig. 8(a) and the harmonics are caused by the leakage of injection signal and mixing products. The sixth harmonic is larger than the 1 st harmonic by 17.55 dBm. Caused by the unbalanced layout, the phase difference of the ILFT inputs may be not exactly 180 o , the injected fundamental is leaked to the ILFT outputs and it induces a doubler frequency signal at the ILFS output. The fundamental leakage is suppressed by the ILFT load filter, and the doubler leakage in the ILFS output is also suppressed. Fig. 9(a) shows measured ×6 input sensitivity measured from Vo3. At 0 dBm input power and VDD=1 V, the locking range is from 5.628 GHz to 6.234 GHz. the performance improves as the supply decreases, because the locking range increases and the power reduces. Fig. 9(b) shows measured phase noises of the locked ILFS and the injection signal at finj = 0.976 GHz. The locked phase noise at 1MHz is greater than the injection signal by 15.4 dBc/Hz at 1 MHz offset frequency. The ideal phase noise difference is 17.37 dBc/Hz. Fig. 10 shows measured ×6 locking range, power consumption and free-run doubler frequency versus VINJ. As VINJ decreases, the conductance of M3 and M4 decreases, the power consumption decreases and the measured locking range increases. Fig. 11(a) shows measured ×6 harmonic output power levels after calibration of the cable loss over different chip input power at the input frequency finj of 1.01 GHz, the harmonic injection suppression improves as injection power increases and the ILFS operates normally irrespective of input power level. Fig. 11(b) shows the harmonics over frequency range of interest with the input power of 0 dBm. From 5.916 GHz to 6 .084 GHz, the undesired harmonics are lower than the 6 th harmonics by more than 10 dBm. Around 6.06 GHz, the harmonic suppression is more than 15 dBm.
The designed circuit in Fig. 2(a) can perform other frequency conversions. It can be used as a differential ×5 injection locked frequency multiplier performed by the previous ILFT except the change of the input frequency range and a single-phase ×10 injection locked frequency multiplier played by the previous ILFS. Table 1 is the measured performance summary. Measured data shows that the proposed ×6 ILFM with the new balanced frequency doubler provides undesired harmonic suppression, large output power and good phase noise performance at all measured offset frequency range.

IV. CONCLUSION
This paper presents a single-stage, compact fully integrated n-core CMOS LC-tank injection-locked frequency sixtupler that combines an injection-locked frequency tripler and a new balanced frequency doubler. The proposed ×6 circuit shows good injection-locked phase noise performance with enough locking range, good harmonic suppression from low to high input power, and large output amplitude to drive next stage, and it uses a 1 st -harmonic ILO, a 3 rd harmonic pre-generator combining a mixer and a frequency doubler/quadrupler, and a new balanced frequency doubler, the circuit can be used as an injection-locked frequency tripler too by taking the output from the ILO buffers. The circuit is also used as an injection locked ×10/×5 frequency multiplier, and further improvement can be achieved by using output filtering. The other high multiplication-factor injection-locked frequency multipliers also show good phase noise and the frequency sixtupler is extendable to a ×12 and ×18 frequency multiplier by combining with a frequency doubler and tripler respectively.