Type-II Compensation for Automotive Buck Converters Implemented by Fully Integrated Capacitor Multiplier

This paper presents a solution for full integration of a Type-II compensation circuit for DC-DC buck converters. It employs a novel active circuit based on capacitor multiplier, able to emulate the R-series-C ensemble within the conventional Gm-RC compensation network. The proposed solution was used to design a current-mode DC-DC buck converter for automotive applications. The implementation of key circuits in a 180 nm CMOS process is presented in some detail. Simulation results demonstrate that the converter meets all design requirements: it provides a 5 V output voltage over wide ranges of the input voltage, 6 V to 45 V, and load current, between 10 mA and 300 mA. Its frequency and transient responses compare well against the performance of a similar converter that employs a conventional Gm-RC compensation circuit. It consumes 20 $\mu \text{A}$ more, but requires significantly less die area, than its counterpart. Furthermore, the tuning required to compensate for process and temperature variations is realized by programming the multiplication factor of the capacitor multiplier.


I. INTRODUCTION
The buck converter is one of the most popular Switch-Mode Power Supply (SMPS) topology [1]. It is widely used in complex power conversion and distribution systems, e.g. automotive systems, server motherboards, broadband communication boards, etc. [2]. In such systems, multiple converters are connected to a common battery voltage and generate the required local voltage levels such as 1.8 V, 3.3 V and/or 5 V [3], [4]. Fig. 1 presents the simplified block diagram of the buck converter with current mode control and a Type-II Gm-RC compensation network. Usually, C 1 , C 3 and R 2 are external components which have to be appropriately sized by the customer in order to maintain loop stability and converter performance over all conditions of operation.
The associate editor coordinating the review of this manuscript and approving it for publication was Yuh-Shyan Hwang .
The quest for ever lower cost and smaller size demands to integrate as much of the system as possible. Full integration of the compensation network is particularly targeted as it reduces the bill of materials down to only the controller IC, the input decoupling and the LC output filter. However, to integrate the compensation network one has to deal with additional design challenges, such as: a). placing high value capacitors on-chip is very expensive, usually prohibitively so in standard CMOS processes b). users want control over key parameters of the compensation network in order to tailor them to their system requirements and c). the circuit topology should allow for a straightforward implementation of digital tuning or trimming, necessary to compensate for process, supply voltage and temperature (PVT) variations. These requirements can be met to some degree by using a high switching frequency and a programmable compensation network based on capacitor and/or resistor matrices. The former usually leads to large dynamic power losses while the later require large die area.
An effective way to reduce the die area occupied by the integrated compensation network is to implement the large capacitor required by using a capacitor multiplier.
For example, the AO-RC Type-II compensation network presented in [5] is implemented by a floating capacitor multiplier. Reference [6] reports a buck converter with fully integrated compensation network based on a capacitor multiplier; the Gm-RC compensation network implemented by a capacitor multiplier resulted in a fast transient response of the convertor presented in [7]. However, these solutions do not meet all the requirements described above: they do not provide for frequency tuning and have been demonstrated only for convertors that operate over narrow input voltage ranges.
This paper presents a solution to fully integrate Type-II Gm-RC compensation networks. The R 2 -series-C 1 ensemble shown in Fig. 1 is implemented by a novel capacitor multiplier based on one Gm cell with two outputs. Frequency tuning is realized effectively by programming the multiplication factor.
Section II presents the capacitor multiplier topology and the resulting Type-II compensation network. Mathematical analysis is followed by detailed description of the proposed transistor level implementation. Section III presents a current-mode automotive DC-DC buck converter that uses the proposed Gm-RC compensation designed in a 180 nm CMOS process. Simulation results obtained for this design are compared against the performance of the converter implemented with the conventional Gm-RC compensation, as well as against similar converters published previously. The main points of the topology and circuit implementation presented here are summarized in the last Section, which also discusses the main conclusions drawn from this work.  [8], [9] and (b) simplified equivalent R-C circuit.

II. TYPE-II FREQUENCY COMPENSATION NETWORK BASED ON CAPACITOR MULTIPLIER A. PROPOSED R-C EMULATOR BASED ON CAPACITOR MULTIPLIER: PRINCIPLE OF OPERATION AND IMPLEMENTATION
The block diagram of the capacitor multiplier introduced in [8] and [9] is shown in Fig. 2 (a). It uses a placed capacitance, C placed , and one transconductor with two outputs called Gm MULT . A transconductor core realizes the necessary voltage-to-current conversion, then the resulting current, i Gm , is conveyed to two distinct high impedance output stages. The output stages are modelled in Fig. 2 (a) by the current controlled current sources CCCS 1 and CCCS 2 , that have the output resistors and capacitors R Out1,2 and C Out1,2 . The current provided at Out 1 , i Out1 , is K times larger than the one supplied by Out 2 , i Out2 . A negative feedback loop is closed around the transconductor Gm MULT by connecting the output Out 2 to the inverting input of the core.
The impedance seen at the circuit input, denoted Z IN in Fig. 2 (a), is purely capacitive if R Out1,2 can be considered infinitely large and capacitances C Out1,2 can be neglected. In these conditions, the equivalent capacitance can be approximated by: where M = 1+ K is the capacitance multiplying factor [9]. A more detailed analysis, considering the finite value of R Out2 , yields the equivalent impedance depicted in Fig. 2 Besides the capacitance C eq , which retains the expressions given by (1), the Z IN model comprises a parasitic series resistor, denoted R S , and a parallel resistor, denoted R P . The expressions of these parasitic resistors can be approximated as follows: It follows that the output resistance R Out1 should be made as large as possible in order to maximize the frequency range this circuit can be effectively used as a capacitor multiplier [9].
It was demonstrated in [9] that the effect the finite value of R Out2 has on Z IN can be neglected by comparison; also, that A large resistance at the Out 1 output can be obtained by using gain boosting as in [9] or another one of the many circuit topologies described in [10]. The starting point for the approach used here is the current mirror with high output impedance introduced in [11], depicted in Fig. 3 (a). An important shortcoming is that the output voltage is limited to V In -V GS_Mfb ; in general terms, the output voltage is not completely independent of the input voltage. This can be avoided by inserting a cascode transistor in the output path, as shown in Fig. 3 (b). The small-signal output resistance seen at the drain of the additional cascode M cas1 can be approximated by: An additional constant voltage, called V cas in Fig. 3 (b), is necessary to drive the gate of cascode M cas1 . This also enables the implementation of a second current output, called i Out2 in Fig. 3 (b). The second output has a smaller output resistance than the main output, given by (3). Overall, the circuit depicted by Fig. 3 (b) is an effective way to implement a current mirror with two outputs, one with the very large resistance given by (3) and the other with the smaller, yet still fairly large output, resistance of a regular cascoded stage.
Equations (1) and (2) indicate that the structure presented in Fig. 2(a) can be used to implement a wanted R-C network, not only a capacitance multiplier as in [9]. Furthermore, the resulting R-C network has the useful feature that the product C eq · R s = C placed / Gm CORE does not dependent on the factor M. Fig. 4 presents the proposed circuit implementation of the transconductor Gm MULT . It uses a symmetrical topology that comprises an input differential pair with resistive degeneration, implemented by transistors M InP , M InM and the resistor R deg , and three current mirrors. The differential pair converts the input differential voltage into a signal current that is taken in by the two current mirrors encompassed by dotted-line rectangles. They use the circuit topology shown in Fig. 3 (b) but with complementary implementation. The signal current passing through M InP is conveyed directly to the outputs by the current mirror ''B'' -encompassed by the dotted-line rectangle on the top-right corner. The signal current passing through M InM is reflected by the current mirror ''A'' on the top-left corner of the schematic, then conveyed to the outputs by the current mirror ''C'' at the bottom of Fig. 4. Note that the current mirrors ''B'' and ''C'' have two outputs each: the ones with high-output impedance connected at node Out 1 and the simple cascoded outputs connected at node Out 2 . Also, the signal current provided by the high-output impedance Out 1 is K times larger than the one provided by the simple cascoded output Out 2 .

B. GM-RC FREQUENCY COMPENSATION NETWORK BASED ON THE PROPOSED CAPACITOR MULTIPLIER
Fig. 5 (a) presents the conventional Type-II Gm-RC frequency compensation network used for ensuring the stability of buck DC-DC converters [7], [12], [13]. The transconductor Gm converts the difference between the reference voltage Vref and a scaled-down version of the buck output voltage, V fb . The resulting current is applied to the RC network formed by C 1 , R 2 , C 3 , and generate the error voltage signal, V e . The transfer function H(jf) = V e / (V ref -V fb ) introduced by this circuit into the DC-DC converter loop gain comprises a pole and a zero [12]: where: The frequency compensation network provides a phase boost to the overall loop gain of the buck converter. For maximum impact on the phase margin, the phase boost should reach its maximum value at the crossover frequency of the converter loop gain [12], [13]. This condition usually leads to a large value for C 1 , rendering it difficult and/or expensive to integrate [7]. Another design challenge is to maintain the pole and zero defined by (5) in suitable locations, despite inevitable PVT variations.
The solution proposed here is to replace the R 2 -series-C 1 ensemble with the impedance realized by the capacitance multiplier shown in Fig. 2, as illustrated by Fig. 5 (b). Thus, capacitor C 1 and resistor R 2 in Fig. 5 (a) are emulated by C eq . and R S from Fig. 2 (b). The parallel resistor shown in Fig. 2 (b), R P , appears as an unwanted component. Its value should be made far larger than the output resistance of the main transconductor, Gm COMP , in order to render immaterial its impact on the operation of the frequency compensating network. This can be achieved by using the circuit implementation proposed in Fig. 4 for the active part of the capacitor multiplier, the transconductor Gm MULT .
Let us analyze the impact of the following sizing conditions: By substituting (6) and (7) into (5) the gain, pole and zero that define the transfer function of the compensation network proposed in Fig. 5 (b) result as follows: where Gm COMP is the transconductance of the main transconductor within the compensation network and Gm CORE is the core transconductance within the Gm MULT , as shown in Fig. 2 (a). Equation (8) indicates several advantages of this approach: -the total capacitance required by the feedback compensation network is reduced substantially.
-the gain H BP depends on ratios of same-type integrated resistors and capacitors, the multiplication ratio, M, and the ratio between transconductances Gm COMP and Gm CORE . Therefore, the impact of PVT variation on H PB can be minimized by using a circuit implementation for the main transconductor similar to the one used for Gm MULT , that is, the circuit presented in Fig. 4.
-one can control the value of the gain H PB and the location of the pole f p by adjusting the multiplication factor. This can be achieved by simply making programmable the gain of the current mirrors denoted ''A'' and ''C'' in Fig. 4.  The following design tradeoff should be considered when choosing the nominal value and tunning range for M: on the one hand, a large nominal value and wide range allows for a substantial reduction of die area and for fine tuning; on the other hand, the larger the M the larger the current consumption and the smaller the smaller the value of R out1 . Moreover, eq. (8) indicates that the distance between the f z and f p is proportional to M, while H PB is inversely proportional to M, for a given set of C 1 , C 3 , R 1 , R 2 and R b values.

III. DESIGN EXAMPLE: AUTOMOTIVE BUCK CONVERTER WITH TYPE-II COMPENSATION NETWORK A. DESIGN REQUIREMENTS AND CIRCUIT IMPLEMENTATION
The proposed compensation network was used to design a current mode DC-DC buck converter considering specific automotive requirements that included load dump, start impulse, spikes and wide ranges for the input (battery) voltage and temperature [14]- [16]. The block diagram is shown in Fig. 1 and the main requirements are summarized in Table 1.
Two versions of the buck converter were implemented in the 180 nm CMOS process XH018 from XFAB: one used the conventional Gm-RC compensation network, shown in Fig. 5 (a), while the other one made use of proposed compensation network shown in Fig. 5 (b), with the capacitor multiplier implemented by the circuit presented in Fig. 4. The same transconductor was used to implement the Gm COMP for both networks. It was based on the circuit topology shown in Fig. 4, except that only the output denoted Out 1 was necessary.
The circuits within the control loop were supplied from an internally generated 3.3 V reference voltage. These conditions allow for a fair and direct comparison between the two compensation networks.
The conventional Gm-RC compensation network was designed by following the standard approach [13]: • the unity-gain frequency of the convertor loop gain was set to one tenth of the switching frequency, that is, f 0dB =50 kHz;  • the zero was placed to one fifth of the unity-gain frequency, that is f z = 10 kHz; • the pole was placed at half the switching frequency, that is f p = 250 kHz. The values of passive components within the compensation network were obtained by solving (5) for the values above. The resistors that implement the feedback voltage divider, R 1 and R b , were sized so that V out = 5 V when the reference voltage has the typical value V ref = 1.2 V. Table 2 lists the values of all passive components shown in Fig. 5 (a).
For the proposed compensation network shown in Fig. 5 (b) the sizing started with the multiplication factor M. The nominal value of M was set to 4, a value for which the circuit implementation shown in Fig. 4 can provide the wanted frequency characteristics up to a frequency at least one decade above the switching frequency. Furthermore, the gain for the Out 1 outputs of the current mirrors A and C, denoted K in Fig. 4, was made programmable. Thus, the value of M can be changed between 3, 4 and 5 by using digital controls. This allows the user to fine-tune the converter frequency characteristics as explained in the previous section and [9].
The feedback resistors R 1 and R b were set to the same values used for the conventional Gm-RC compensation network. The other circuit elements shown in Fig. 5 (b) were sized by solving the set of simultaneous equations (8) for the values obtained for the conventional compensation network.
By design, C placed is M times smaller than the C 1 . Table 3 lists the resulting values for all circuit elements.
Note that the core transconductor within the capacitance multiplier, Gm CORE , needs to provide a transconductance about 150 times smaller than Gm COMP . This makes it easier to realize the large value for the R out1 output resistance required by (2). Also, the capacitance multiplier only needs a fraction of the current required by the Gm COMP transconductor: overall, Gm MULT required 20 µA, while Gm COMP needed 100 µA. Most importantly, the power consumption of both networks had no practical impact on the buck converter efficiency. The total capacitance used by the proposed network is significantly smaller than the one used by the conventional Gm-RC compensation network: 78 pF against 216 pF. Fig. 6 presents the layout of the compensation network proposed in Fig. 5 (b), with the circuit implementation of the transconductors there shown in Fig. 4.  The conventional Gm-RC compensation network, shown in Fig. 5 (a), requires an area about 3.5 times larger: although it does not need the cell Gm MULT , it requires a capacitor four times larger than the C placed in Fig. 6, plus a 76.5 k resistor.
The active circuit shown in Fig. 5 (b), used here to emulate the R 2 -C 1 ensemble, comprises a feedback loop closed between Out 2 and the inverting input of Gm MULT . Its stability needs to be ensured for all operating conditions. Fig. 7 presents the module and phase frequency characteristics of that loop gain. They were obtained by running simulations of an extracted-RC netlist, considering the entire range of process, supply voltage and temperature (PVT) variations. These results indicate that the loop remains stable over all operating conditions, with the phase margin close to 90 degrees. Fig. 8 illustrates the impact increasing the multiplication factor M has on the frequency characteristic of the output resistance R out1 . In line with the circuit analysis performed in the previous section, the low-frequency value of Rout1is remarkably large but it decreases as M increases. However,  its value remains relatively large over the frequency range of interested for the application envisaged here: 39 M at 10 kHz which corresponds to F PB value and 2 M at 1MHz. Fig. 9 presents the frequency characteristics yielded by schematic-only simulations of the two designed compensation networks described in the previous sub-section. The frequency characteristics yielded by an ''ideal'' compensation network -that is, the standard Gm-RC network shown in Fig. 5 (a) implemented by using an idealized model for Gm COMP and ideal passive components with the values listed in Table 2 -are also depicted in Fig. 9, as a reference.

B. PERFORMANCE COMPARISON OF THE CONVETIONAL AN PROPOSED NETWORKS
One notices that there is no significant difference between the frequency characteristics of the designed networks, the VOLUME 10, 2022 conventional Gm-RC and the proposed one, based on capacitance multiplication. Furthermore, these characteristics practically overlap the ideal ones over a wide frequency range, that includes the critical frequency band over which the phase boosting is realized. However, the transfer characteristics yielded by the integrated compensation networks diverge from the ideal ones at frequencies bellow 1 kHz and higher than 250 kHz. This is caused mainly by the finite value of the Gm COMP and Gm MULT transconductors and their parasitic capacitances, inherent to an integrated implementation.
Let us now present results obtained by running simulations on RC-extracted netlists, that include both parasitic resistances and capacitors extracted from the layout shown in Fig 6. Table 4 summarizes the values yielded by Monte Carlo and PVT simulations for the main parameters of the frequency characteristics of the two integrated Gm-RC compensation networks described in the previous sub-section. Again, the differences between them are insignificant. This demonstrates that the impact the offset and internal poles of the additional transconductor Gm MULT , used to implement the capacitance multiplier, have on the frequency characteristic of the proposed compensation network can be made negligible by careful design . Fig 10. presents the frequency characteristics realized by the proposed Gm-Cap.Multiplier with M set to 4, over the entire range of process, mismatch, supply voltage and temperature variations. It highlights an essential feature of the proposed circuit: the frequency characteristic key parameters H PB , F PB and F ZERO exhibit remarkably small variations. Fig. 11 highlights an important advantage the compensation network proposed here has over the conventional Gm-RC approach: the possibility to adjust the circuit by changing M. It presents the frequency characteristics of the proposed compensation circuit when the value of the multiplication ratio M is set to 3, 4 and 5. The gain at the phase boost frequency, H PB , can be adjusted between 16.9 dB and 21.2 dB, while the phase boost frequency is maintained at 50 kHz +/-10 kHz.
Let us now assess the performance of the entire current mode buck converter when using the two compensation networks considered here, the conventional Gm-RC and the proposed one based on the capacitor multiplier. To keep the focus  on the comparison between the compensation networks, all the other functional blocks shown in Fig. 1 were replaced by VerilogA behavioral models. Fig. 12 presents the frequency characteristics for the loop gain of the entire buck converter, implemented by using the compensation network proposed here, for typical process, room temperature and nominal supply voltage. These results demonstrate that the converter phase margin can be set to values between 36.2 degrees and 61.6 degrees by varying M between 3 and 5, while the crossover frequency is kept relatively constant, within the range 52 kHz +/-10 kHz.  The corresponding plots obtained when the conventional Gm-RC compensation network was used instead are also presented in Fig. 12, with continuous line. They overlap the plots yielded by the buck that uses the of the compensation circuit proposed when its multiplication factor M was set to 4. Fig. 13 presents the buck converter response to a line voltage step, when V In goes down from 13 V to 6 V in 100 ns. This simulation corresponds to the real-life engine start-up case: the automobile starter motor draws hundreds of amperes of current from the battery, pulling down its voltage level for a short period of time [13]. The plots shown in the middle and bottom of Fig. 13 show the error voltage that appears at the output of the compensation circuit (V e ) and the buck converter output voltage (V Out ). The plots yielded by the two compensation networks analyzed here practically overlap, the converter responses are nearly identical.   An unsuppressed load dump could generate voltages as large as 35 V to 45 V [16]. In this case, too, the standard Gm-RC and the new compensation network, based on capacitance multiplier, yield practically identical V e and V Out plots.
The load transient performance of the buck converter implemented with the two compensation networks was assessed by considering two cases: i). the load current stepping up, from 100 mA to 300 mA, in 100 ns -see Fig. 15 -and ii). the load current stepping down, from 100 mA to 10 mA, in 100 ns -see Fig. 16. For both test cases, there are no significant differences between the converter responses to these load jumps when using different compensation networks. Simulation results presented in Fig. 12 to Fig. 16 were obtained by using the industry-standard Cadence Virtuoso design environment. They demonstrate that replacing the standard Gm-RC compensation network with the new one described in Section II does not have a negative impact on the converter performance.
The first column in Table 5 lists the main parameters of the buck convertor implemented with the compensation network based on capacitance multiplier, obtained for typical process and nominal operation conditions. As predicted by the results listed in Table 4, PVT variations do not have a major impact on the converter parameters, which remain within the limits set by the design requirements listed in Table 1.
However, several converter parameters are significantly impacted by the actual values of external components deviating from their nominal values. This is highlighted by the parameter values listed in the second column in Table 5: they were obtained for the buck converter that used the Gm-Cap. Multiplier compensation with nominal value set to M = 4 when the actual values of both L Out and C Out were set at 20 % over their nominal values. Similar results are obtained if the compensation network based on capacitance multiplier is used, but in this case the buck parameters can be brought back close to the values obtained in nominal conditions -listed in the first column of Table 5 -by simply setting the multiplication factor M = 3 instead of its nominal value, M = 4. Table 6 summarizes the performance of the two converters presented in this work -the one which uses the conventional Gm-RC Type-II compensation network and the other that uses the newly proposed capacitor multiplierbased frequency compensation network. To allow for a direct comparison, Table 6 also presents the performance of several previously reported converters that used capacitance multipliers.

C. COMPARISON AGAINST CONVERTERS PUBLISHED PREVIOUSLY
Most features and parameters of the converters listed in Table 6 are similar, except for three important points: i). The two converters presented here can handle a wide input voltage range: 6 V to 45 V, compared to 1.4 V to 4.2 V for the nearest competitor. The wide input voltage range required by automotive applications led to larger values for the external inductor and a longer settling time.
ii). We use a smaller multiplication factor: M takes value between 3 and 5. As explained in Section III, a larger value for M makes it more difficult to ensure the required large output resistance and wide operating frequency range for the cell Gm MULT shown in Fig. 4. Moreover, simulation results shown in and Fig. 12, and listed in Tables 6 indicate that a  wider range for M is not necessary. iii). Only the newly proposed compensation network based on capacitance multiplier allows for the multiplication factor to be programmed digitally. The usefulness of this feature was demonstrated by the simulation results shown in Fig. 11, Fig. 12 and listed in Table 5.
An important feature for assessing the performance of circuits based on capacitor multipliers is the die area reduction, estimated by comparison with the area necessary for a conventional implementation, based on placed capacitors. Note that a larger multiplication factor does not necessarily equates to a larger area reduction. For example, in [7] the 76 pF capacitor within an R-C compensation network is emulated by a basic capacitance multiplier with M = 19 and a placed capacitor of 4 pF. Thus, the die area occupied by a 72 pF placed capacitor was saved (the area occupied by the active circuit is negligible by comparison with the passive devices). Under the same conditions, the circuit proposed here yields a die area reduction at least twice as large, despite its smaller multiplication factor. For M = 4, the proposed circuit emulates an entire RC network, with R = 10.9 k and C = 208 pF, by using a 52 pF placed capacitor.

IV. CONCLUSION
A new solution for integrating a Type-II compensation circuit for DC-DC buck converters was presented in this paper. The main idea is to emulate the R-series-C ensemble within the standard Gm-RC compensation network by using a novel capacitor multiplier tailored for this task.
The proposed topology for the Gm-Cap.Multiplier frequency compensation circuit was described in some detail, including the key sizing equations. It has two important advantages over the conventional Gm-RC circuit: i). it uses a significantly smaller die area, as it requires a placed capacitor M times smaller than the one required by the Gm-RC circuit, where M is the capacitance multiplication factor, and no placed resistor and ii). it provides a simple yet effective solution for frequency tuning, by adjusting the value of M.
A transistor-level implementation of the Gm-Cap. Multiplier circuit was presented. An improved version of a current mirror with large output impedance was developed for this circuit.
In order to prove the effectiveness of the Gm-Cap. Multiplier approach, its performance was compared against the conventional Gm-RC frequency compensation circuit in a real-life design example: a buck converter for automotive applications. The converter had to operate over a wide range of supply voltages, from 6 V to 45 V, with the switching frequency set to 500 kHz. It had to maintain the output voltage V Out = 5 V with an output voltage ripple no larger than 50 mV and provide a maximum output current of 300 mA. Two versions of the buck converter were designed in a 180 nm standard CMOS process: one used the standard Gm-RC frequency compensation network while the other used the proposed Gm-Cap.Multiplier approach.
Simulation results presented in the paper demonstrated that the converters implemented with the two compensation networks have practically same performances and almost identical frequency and transient responses. The Gm-Cap. Multiplier circuit consumes only 20 µA more than the standard Gm-RC circuit but requires a total placed capacitance (C 1 and C 3 ) of only 78 pF, instead of the 216 pF required by its counterpart. Furthermore, it provides an effective way to implement tuning of the converter open-loop frequency characteristics, by making the multiplication factor digitally programmable. This allows the users to reduce the impact factors such as PVT variations inherent to an integrated implementation, and deviations of the actual values of external components from their nominal values, may have on the converter performance.
VLAD-ALEXANDRU IONESCU was born in Bucharest, Romania, in 1986. He received the B.E. and M.E. degrees in electrical engineering from the Politehnica University of Bucharest, Romania, in 2009 and 2011, respectively. Since 2009, he has been working with Infineon Technologies Romania. His current research interests include automotive electronics, power management solutions, functional safety, linear voltage regulators, and circuit design optimization using machine learning methods.
MARINA DANA ŢOPA (Member, IEEE) received the M.S. and Ph.D. degrees in electrical engineering from the Technical University of Cluj-Napoca, Romania, in 1981 and 1998, respectively. Since 1983, she has been with the Department of Basis of Electronics, Technical University of Cluj-Napoca. She is currently a Professor and lectures on signals and systems theory. She has published over 190 papers in journals and conference proceedings, and has contributed to 14 books. Her research interests include analysis and design of electronic circuits; digital signal processing, mainly audio signals; and room acoustics.