A High Step-Up PWM Non-Isolated DC-DC Converter With Soft Switching Operation

A high step-up PWM non-isolated dc–dc converter with soft switching is proposed in this paper. The converter has minimum auxiliary elements to achieve high power density and high voltage gain. The ZVS operation of the main power switch results in negligible capacitive turn-on losses. Since the duty cycle of the auxiliary switch is narrow and its operation is under ZCS condition, the losses that the auxiliary circuit imposes are not significant. Also, all the diodes are operated under soft-switching conditions solving the reverse recovery problem. All the inductors are coupled on only one magnetic core, reducing size and conduction losses. Compared to the hard switched counterpart, the electromagnetic interference of the proposed converter is reduced. Furthermore, the output voltage of the proposed converter is controlled by an integral sliding mode control strategy during the load variations. Also, the proposed integral sliding mode control strategy has been compared with the PI control strategy, improving the transient response and the robustness under load variations while the switching frequency is constant. The effectiveness and accuracy of the proposed converter are verified by practical laboratory results which are obtained from a 250W prototype.


I. INTRODUCTION
Recently, the massy usage of fossil fuels effects on the environment. This is an important issue which causes to find renewable energy sources to generate electrical energy [1], [2]. The solar system is one of the suggestive players in renewable energy sources because of the emission-free and clear quality [3]- [6]. One of the exciting topics is to employ the new power electronic circuits whose high power density, high efficiency, and broad conversion ratio are their trends [7]. The development of high step-up converters has become critical for converting the low voltage of photovoltaic (PV) panels to a desired voltage level for grid-connected applications. Generally, many high step-up converters are famous for being used in electronic devices such as renewable energy sources like photovoltaic and fuel cell systems. Moreover, the high-intensity-discharge (HID) lamps, the fuel cells, the uninterruptible power supply (UPS), and the communication power system's front-end stage are The associate editor coordinating the review of this manuscript and approving it for publication was Shihong Ding . some of the applications that high power-density and high step-up non-isolated converters are used [8], [9].
To obtain the high voltage gain by using the conventional boost converter, the high duty cycle should be used for the power switch. Therefore, the current level through the converter rises, so the voltage drop increases which decrease the efficiency of the converter. Moreover, the high-priced power switches should be chosen. In order to solve these problems and achieve high voltage gain, many techniques are introduced, such as the coupled inductors, switchedcapacitors, and multiplier circuits. Nevertheless, in the switched-capacitors and the multiplier circuits, the number of capacitors and the semiconductors are high, so the conduction losses and the switching losses in these topologies increase. Also, the power density of the converter is reduced. The coupled inductor technique, which is used in the proposed converter, is one of the most popular methods to increase the voltage gain, but by using more than one core, the size and volume of the converter are increased [10], [11].
In the switching converters, the size and the weight of the reactive components should be downgraded to reduce the costs of the converter [10], [11]. To achieve this, the VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ operation should be on high switching frequency [12]; therefore, in high-frequency hard-switched converters, the losses of switching and the EMI are increased, resulting in lower efficiency in comparison with the soft switched converters due to the sudden changes of voltage and current of the switches [11], [13]. To overcome these drawbacks, various passive [14], [15] or active [16], [17] soft switching techniques are proposed. The resonant converters are a kind of soft switched converters in which no auxiliary switch added to the structure. But for controlling the output power in these converters, the switching frequency should not vary, so cannot achieve the optimum design of the magnetic elements. The active clamp technique makes the power switches operate under ZVS conditions with no capacitive turn-on losses. However, in the active clamp circuit, the circulating current in the auxiliary circuit is high, so the conduction losses rise; thus, the efficiency decreases. Moreover, the Zero-Current-Transition (ZCT) and the Zero-Voltage-Transition (ZVT) are two commonly used methods of the soft switching active techniques, in which an auxiliary circuit with at least one power switch is attached to the converter to provide soft transition conditions [18]- [20].
In the ZVT technique, which used in the proposed converter, an auxiliary circuit is added to the converter, after the main switch, in parallel with the structure. The ZVT circuit in the proposed converter consists of a switch, a diode, an inductor, and a coupled inductor. Using the ZVT circuit makes the main switch operates under the ZVS soft-switching condition with no capacitive turn-on losses for the main switch. Also, there are no switching losses for the MOSFETs because of the soft-switching conditions. Furthermore, because of the inductor, which series with the auxiliary switch, the auxiliary switch operates under the ZCS condition. The ZCS operation of the MOSFET leads to narrow switching losses of the converter. Further, the circulating current and conduction losses of the auxiliary circuit is reduced due to the low duty cycle. Moreover, using the ZVT technique makes the converters operate similar to the regular Pulse-Width-Modulation (PWM) converters [13] which the designation of their controller is simple. In this paper, a new PWM high step-up converter is presented, which illustrated in Fig. 1. In this structure, the soft-switching conditions is obtained for all the semiconductors by using the ZVT circuit while there are no extra stresses on the MOSFETs. The soft-switching conditions are also achieved for all the diodes, solving the reverse recovery problem and decreasing the power losses. The high voltage conversion of 30-500V makes the circuit suitable for photovoltaic applications. In order to improve the efficiency, all the inductors are coupled on only one magnetic core, as shown in Fig. 2. Also, a higher power density is achieved compared to other converters, which have more than one magnetic core.
To guarantee the stability and adjust the output voltage to the required value under the load variations, the output voltage of the proposed converter can be controlled by Sliding  Mode Control (SMC) technique, which is more attractive than regular PWM controllers used in [11] and [14]. The advantages which make the SMC family more suitable compared to the proportional-integral (PI) controller are the stability against parameter variations, disturbances rejection, fast dynamic responses, and inherent robustness of tracking control [21], [22]. On the other hand, there are also disadvantages. One of the crux disadvantages of applying SMC on dc-dc converters is design filter circuit difficulty due to the operation frequency variation [21]. To achieve constant frequency operation, the PWM converters are used in the related applications, but the Steady-State Error (SSE) are increased. Another disadvantage of the SMC is need a high-switching frequency for control action which results in the so-called chattering effect [23], [24]. In order to solve these drawbacks, a kind of SMC called Integral Sliding Mode Control (ISMC) is proposed [22] and [24]. The ISMC has strong robustness under load variations. This property caused to fix the output voltage level of the converter to the desired value. In this paper, an ISMC strategy is used for adjusting the output voltage of the proposed converter to the required value under the load variations. To validate the analysis, a practical prototype is implemented on a SPARTAN-6 XC6SLX9 FPGA chip which its clock manager is developed in comparison with the SPARTAN-3 FPGA chip which used in [21] and [23], so the processing speed has been improved and resulted in less chattering effects.
Firstly, the main contribution of the proposed converter is the modular ZVT auxiliary circuit which there is no need for new auxiliary circuit for the converter with extra phases. Secondly, the circulating current in the proposed auxiliary circuit is low because the short turned on time of the auxiliary switch. According to the soft-switching condition which is provided for the auxiliary switch and the auxiliary diode operation, there is no significant losses of the auxiliary circuit imposing to the proposed converter. Moreover, in order to create a voltage source on the auxiliary circuit, a tertiary coupled inductor is applied on the main core of the proposed converter which decreases the volume and increases the power density. Moreover, the softswitching condition is achieved for a wide range of the load variations.
In the following, the proposed converter and the soft switching operating principles are presented in section II. Section III has explained the ISMC design and its comparison with the PI controller. Moreover, section IV presents the experimental results that verified the soft-switching conditions, the fixed output voltage on load variations, and the conduction EMI comparison between the soft switched converter and the hard-switched counterpart. Finally, the conclusion is written at the end of the paper in section V.

II. OPERATING PRINCIPLES AND DESIGNATIONS
A high step-up PWM non-isolated DC-DC converter with soft switching operation is proposed. The converter comprised a ZVT circuit, a clamp circuit, and a charge-pump capacitor. The ZVT auxiliary circuit includes an auxiliary switch (S a ), an auxiliary diode (D a ), an auxiliary inductor (L a ), and a tertiary inductor (L 3 ). This auxiliary circuit is added to the converter in parallel. A clamp circuit is used identically in the output, after the ZVT circuit, which solves most efficiency issues. The clamp circuit includes two diodes named D 1 and D 2 and a clamp capacitor named C c . Eventually, the charge-pump capacitor (C cp ) is located crosswise to the coupled inductors (L 1 , L 2 ), which increases the voltage gain. Further, the primary inductor (L 1 ) current is continuous because of adding this charge-pump capacitor. So, the Continuous-Conduction-Mode (CCM) is available for this converter. Also, according to Fig. 2, the L 3 inductor, added by the auxiliary circuit, is on the magnetic core, which contains the two primary and secondary inductors (L 1 and L 2 ). Using only one magnetic core decreases the total volume and the power losses of the converter, which leads to higher power density and efficiency, in comparison with other converters which contain more than one core.

A. OPERATING PRINCIPLES
The operation is on eight modes for every switching cycle at full-load. Each mode expresses the proposed converter's accurate performance. Figure 3 and Fig. 4, illustrate the theoretical waveforms and the counterpart circuit for each mode, respectively. In Fig. 3, the ''V GS(Sm) '' is the gatesource pulse of the main switch, the ''V GS(Sa) '' is the gate-source pulse of the auxiliary switch, the ''I Sm , V Sm '' is the drain-source current and voltage of the main switch, and the ''I Sa , V Sa '' is the drain-source current and voltage of the auxiliary switch. Also, the current and voltage of the D 1 , D 2 , If the N 1 through N 3 be the turn's number of L 1 through L 3 , respectively, the turns ratio n and m are equal to: Prior to the first mode, all the MOSFETs are turned off, and the snubber capacitor's voltage is reached to its maximum amount. Also, only the output diode is conducting, and the other diodes are off. For the analysis, it is considered that: • All the semiconductors are assumed to be ideal. • Output and clamp capacitors are chosen spacious; so, their voltages are constant during the switching cycle.
Prior to turn on the main switch, S m , the auxiliary switch, S a , should be turned on for discharging the snubber capacitor C s . Therefore, this mode commences, and the S a turns on with the ZCS condition because of the L a inductor series. The auxiliary switch S a current can be calculated as follows, where D is the duty cycle of the S m : When the S a is turned on, the D a diode turns on with the ZCS condition too. Also, the L a inductor's current increases, and the output diode D o current decreases, both linearly, so the ZCS turn-off for output diode D o is provided. The current of the D o diode reaches zero and this mode ends.

2) MODE 2 [t 1 , t 2 ]
The output diode turns off, and the snubber capacitor C s is discharged via resonance with the L a inductor. Therefore, the voltage of C s is decreased resonantly to zero, so the ZVS condition is obtained for turning the main switch on is provided. The resonantly decreased voltage of the snubber capacitor C s can be derived as below, where ω is the angular frequency.
Then, the body diode of the main switch becomes forward biased and clamps its voltage to zero level, and this mode ends.

3) MODE 3 [t 2 , t 3 ]
The body diode becomes forward biased, this mode begins, and then the S m could be turned on under ZVS condition. Because of the constant voltage difference between the two ends of L a , which is defined as ''mV in '', the current of L a is decreased linearly. Then, the body diode current is moved to the main switch.

4) MODE 4 [t 3 , t 4 ]
The current of the main switch S m rises linearly to magnetizing current and the main switch is turned on with the ZVS condition. Also, the L a inductor's current reduces gradually to zero, and the D a diode turns off with the ZCS condition. Afterward, the auxiliary switch S a can be turned off under ZCS condition, too.

5) MODE 5 [t 4 , t 5 ]
The output diode D o is off, and the main switch S m is on. Thus, the magnetizing inductor, L m , is charged. The voltage of the L 2 inductor can be calculated as: Moreover, the output current is supplied by the capacitor C o while the D 2 diode conducts under ZCS condition,and the capacitor C cp is charged from the paths of main switch S m , clamp capacitor C c and D 2 diode. This mode continues until the main switch S m turns off.
The main switch (S m ) is turned off. Also, its voltage rises gradually due to the snubber capacitor paralleled with it. Thus, the main switch S m turns off with the ZVS condition. The voltage of the main switch can be derived as: V Sm max = V Cs max = V out n + 2 where i Lm is the magnetizing current. Also, the D 2 diode's current is reduced to zero, then the clamp diode, D 1 , turns on, and this mode ends.

7) MODE 7 [t 6 , t 7 ]
The D 1 turns on with the ZVS condition. Then, the L a inductor's energy is moved to the clamp capacitor C c . The L a inductor's voltage is derived as below: where D is the main switch duty cycle. The D 2 diode turns off under the ZVS condition, and the D o turns on with the ZCS condition. Also, the current of the output diode D o is as follows where D is the main switch duty cycle, and i Lm is the magnetizing current: Furthermore, the magnetizing inductor's energy is discharged in the output, and the D 1 turns off with the ZCS condition.

8) MODE 8 [t 7 , t 8 ]
The D 1 diode is turned off. The magnetizing inductor's energy moves from the output diode D o to output. This mode continues until the auxiliary switch S a is turned on.

B. DESIGN PROCEDURE
The converter's voltage gain is acquired by a KVL between the output, clamp capacitor, and the secondary inductor as follow, where D is the duty cycle, and k is the effect of the leakage inductor.
Without considering the leakage inductance energy, the voltage gain is calculated as follow: To obtain the snubber capacitor (C s ) value, the converter is checked in Mode 2 when the C s capacitor is discharged via resonance with the L a inductor. The C s capacitor must be spacious enough to decrease the stresses of the main switch S m . The designation of the C s capacitor in this paper is like a regular snubber capacitor, where the main switch voltage's rise time and the magnetizing inductor current are named by t r and i Lm , respectively. The snubber capacitor C s value can be acquired as below: As well as the C s capacitor is attained, the L a inductor is calculated by the angular frequency (5), where f sw = 1/T is the switching frequency. Moreover, the C cp is a charge-pump capacitor whose voltage value can be derived by a KVL between the chargepump capacitor, the clamp capacitor, and the secondary inductor in Mode 5 operation. The C cp voltage is calculated as: Moreover, the clamp capacitor voltage is also computed by this KVL as follow: The characteristics of the presented converter are provided in Table 1 compared to the other related converters. According to this table, the proposed structure has fewer components and MOSFETs in comparison with the converters in [26], [29], [30], and [32], reducing weight, size, and cost, and improving the power density of the converter. Also, the voltage gain of the proposed converter is higher than the converters in [25] and [26]. Although the converters in [27]- [29] and [32] have a higher voltage gain in comparison with the proposed structure, the converter presented in [29] operates under ZCS condition.
The ZCS condition applied to the power switches of the converters in [25] and [29] raises the capacitive turn-on losses of the converter. Further, the converters in [27], [28], and [30] operate under hard-switching condition. The converters in [27] and [30] have 18 total component counts resulting in less power density and higher costs compared to the proposed structure. Moreover, although the voltage gain of the converter in [32], which has three voltage multiplier stages, is higher than that of the proposed converter, the proposed converter has fewer components. Furthermore, the active clamp technique is used for the converter in [32] for making the MOSFETs operate with the ZVS condition. Also, this technique increases the current flow and the current stress of the main switches, while its experimental results illustrate the current of the main switch is almost 50A for the 500W prototype. In addition, the switching operation in the converter [28] is hard-switching, so the switching losses and the EMI of the converter are high. It is noted that the A in Table 1  is the number of stages and k = 1 is the number of the diodecapacitor Voltage Multiplier (VM) stages of the converter.
Moreover, the voltage and current stresses of the proposed converter and the converters introduced in [25]- [30] and [32] are written in Table 2. The voltage stress of the converters in [25] and [26] is higher than the voltage stress of the proposed converter, while the current stress of the proposed converter is lower than that of the converters in [27]- [32]. It is noted that the ESR in Table 2 is the equivalent series resistance of the capacitors. For better understanding, the comparison between the voltage gains of the converters in [25]- [32] is plotted in Fig. 5.

C. POWER LOSSES
This section presents the effects of the non-ideal components of the proposed converter on the total losses. By considering the non-ideal components, the conduction losses of the MOSFETs and the diodes, the conduction losses of the coupled inductors, and the conduction losses of the capacitors are calculated. Because of the ZVS condition provided for the main switch, it has no capacitive turn-on losses. However, the capacitive turn-on losses of the auxiliary switch are considered. The core losses are few enough, which is ignored. The conduction losses of the power switches depend on the drain-source on resistance and the root-mean-square (RMS) current of the switches. The conduction losses of the MOSFETs are calculated as: Because of the ZVS condition, which is provided for the main switch, its capacitive turn-on losses equal zero, and there are only the capacitive turn-on losses of the auxiliary switch, which are calculated as follows: The conduction losses of all the diodes depend on their forward voltage drops and average currents flowing through them, which are obtained as follows: V f (I avg D1 + I avg D2 + I avg Da ) The conduction losses of the inductors are also considered because they have parasitic resistances. The losses of the inductors are calculated as follows: According to the above calculations, the total calculated power losses of the proposed converter is 9.21W for the 250W full-load prototype. Thus, 96.32% of calculated efficiency is achieved.

D. AUXILIARY CIRCUIT DERIVATION
A new ZVT auxiliary circuit is applied to the proposed converter, which contains the minimum number of elements to provide soft-switching conditions for the power switches. A new ZVT auxiliary circuit is applied to the proposed converter which contains the minimum number of elements to provide soft switching conditions for the power switches. The leakage inductance of the tertiary coupled inductor which is located on the ZVT auxiliary circuit series with the L a inductor, so there is resonance between the inductors and the snubber capacitor. Thus, the ZVS operation for the main switch is provided. Further, the auxiliary switch of the converter is operated under ZCS condition because of the L a inductor, which is series with it. So, the auxiliary circuit does not impose significant losses to the proposed converter because of the short duty cycle of the auxiliary switch and the soft-switching operation of both power switches.
The proposed auxiliary circuit has a simple operation. As analyzed in section II, to turn the main switch on under ZVS condition, the auxiliary switch should turn on sooner than the main switch. So, the auxiliary inductor La resonances with the snubber capacitor. The voltage of the main switch reduces gradually to zero; then the main switch can be turned on under ZVS condition. The auxiliary inductor of L a , which series with the auxiliary switch, increases and decreases their current slowly. So the ZCS condition for turning on and off instants is provided for the auxiliary switch.
The proposed ZVT auxiliary circuit could apply to other related high step-up converters (single-phase and doublephases). For instance, in Fig. 6, a double phases (Fig. 6(a)) and a single-phase ( Fig. 6(b)) high step-up converters are presented, which have the higher voltage gain and lower voltage stress on the switches compared to the proposed converter. However, the total component count of these converters is high, reducing the power density and increasing the total cost, weight, and size of the converter. This paper, VOLUME 10, 2022 designs a new topology operating with suitable specifications to be used in photovoltaic systems.

III. ISMC DESIGN
In this section, a controller is designed based on ISMC to adjust the output voltage of the proposed converter to the required level under load variations. The power switches' duty cycles are changed with the controller while the load varies. The ISMC strategy has more benefits compared with the PI system. Some of these advantages are fast response, guarantee stability, and robustness in the face of uncertainties and environmental situations. Moreover, the proposed control method operates on the wide range of the quiescent point, while the PI controller operation depends on the quiescent point strongly. The tuning of the coefficients of the PI controller is also complicated. Furthermore, the chattering effect and the steady-state error is minimized by this controller ability. In the following, the design procedure of the proposed control method is explained.

A. SLIDING SURFACE
To design the proposed controller based on ISMC strategy, sliding surface (s) is considered as: (24) where e = V ref − V out is the voltage error. Also, V ref and V out are the reference and the actual value of the converter's output voltage, respectively. K is the positive constant gain suitable for the system transient requirement. The s = 0 represents the accurate tracking of the converter's voltage. Moreover, the system states attain the sliding surface and then slide along the surface. Thus: Based on (25), derivatives of s equal zero, which gives: The aforementioned equation ensures the voltage error converges to zero. Since (23) equals zero initially, the converter's output voltage gathers asymptotically to the base with a time constant of 1/K.

B. SMC LAW
The SMC design is employed in the systems to force the state variables to the surface. In the proposed control method, the output voltage reference of the converter is generated as the input of the PWM module.
To derive the conditions on the control law, a candidate Lyapunov function is employed, which drives the state to the sliding surface. The ''W'' is the Lyapunov function which is introduced as: With differentiating s by (23), the motion projections of the system (12) on sliding surface s are derived, as: According to (12), dV out /dt is calculated as: Substituting (30) into (29) yields: The switch control law is chosen to form dW/dt < 0 for S = 0. Therefore, the control law is introduced by (32) as: where, The K c is the positive control gain.

C. THE STABILITY PROOF
For making the sliding surfaces stable, the time derivative of the Lyapunov function (28) must be a negative-definite function: Since s.sat(s) is positive, dW/dt is absolutely negative. Since W > 0 and dW/dt < 0, s reaches zero asymptotically. Accordingly, the proposed controller is stable.

D. THE ROBUSTNESS PROOF
In terms of practicable application, the disturbances of the system include the sample errors of analog-digital converting, the noises, and the parameter variations that could affect the sliding surface, s. Consequently, (31) is rewritten: where H is the disturbance term. Thus, (28) is rewritten as: The dW/dt is undoubtedly negative. If the positive control gains satisfy the conditions, named K c > |H|. Hence, the ISMC emphasizes strong robustness.
The proposed control method block diagram is illustrated in Fig. 7. Consequently, the proposed converter's output voltage is driven to the referenced level, and the instantaneous errors of the reference and the output voltages of the proposed converter are employed as the input of the ISMC. Moreover, the discrete-time nature of the simulation and implementation on a FPGA chip resulted in finite amplitude and ''zigzag'' motion of the frequency due to the imperfection in the sign function implementation [24]. This effect, named chattering, maximizes the output voltage ripple. To remove the chattering effect, the saturation function is used and makes the ISMC suitable for controlling the converter's output voltage with minimum chattering and steady-state error.

A. SOFT SWITCHING EXPERIMENTAL RESULTS
To prove the proposed converter proficiency, a prototype has been implemented. Also, to find the exact design specifications, Table 3 is presented. According to Table 3, the converter's input voltage is 30V, and its output voltage is designed 500V. The switching frequency is 100 kHz, and the output power is 250W. The proposed converter's practical prototype photo and the FPGA board of the controller are VOLUME 10, 2022 depicted in Fig. 8. The semiconductor elements' practical waveforms on full-load are shown in Fig. 9. As maintained by this figure, the soft-switching conditions are verified for all semiconductors. It is observed by Fig. 9(a) that the main switch S m is turned on and off under ZVS condition. In addition, the maximum voltage of the S m is curbed to less than 150V. In addition to that, the conduction losses could be downgraded. Besides, Fig. 9(b) shows the ZCS condition on the auxiliary switch for turn on and off instance due to the slow increase and decrease of its current. According to the Fig. 9(b), the drain-source capacitor of the auxiliary switch resonates with the L a inductor resulting a ringing on the voltage of the auxiliary switch at the turn off instance. As illustrated in Figs. 9(c) and (d), the soft-switching operation is obtained for D 1 and D 2 diodes. The D 1 diode is turned on and turned off under ZVS and ZCS conditions, due to the gradually decrease of voltage and current respectively. Also, the D 2 diode is turned on under ZCS and turned off under ZVS conditions. Moreover, the waveforms of the D o , depicted in Fig. 9(e), illustrates the output diode turns on and off under ZCS condition. Also, there is a resonance on the output diode voltage at the turn off instance because of the parasitic capacitor of the output diode which resonates with the leakage inductance of the coupled inductors.
The measured efficiency of the proposed converter and its hard-switched counterpart is plotted in Fig. 10(a) under 100W loads to full-load. As a result, the full-load measured efficiency of the proposed converter is 96.32% which is higher than that of the hard-switched counterpart. In addition, the losses distribution of the proposed converter is illustrated in Fig. 10(b). In this figure, the semiconductor devices losses and the inductors losses are considered. According to this chart, the majority of losses are associated to power switches. Also, the conduction losses of the diodes significantly affect the converter's efficiency. The total losses can be declined by choosing the MOSFETs with low R DS (on). Also, to improve the converter's efficiency, more coppers are recommended.

B. PI AND ISMC PRACTICAL WAVEFORMS
Both of the controllers are implemented on a SPARTAN-6 XC6SLX9 FPGA chip to compare the experimental results of the PI and ISMC. The implementation process is as follows, which is similar for both controllers. The presented  converter's output voltage is conveyed to analog to digital converter (ADC) pins of the FPGA board; the design calculations of the controller are done, then a PWM signal at 100 kHz is directly generated to control the duty cycle of the power switches.
In order to make a good challenge for the proposed control method and adjust the output voltage of the proposed converter to the desired value (500V), the proposed converter's output power is changed over time. The practical results of the output voltage and current over power variations are shown in Fig. 11. In this scenario, the output power of the proposed converter is changed from half-load to full-load at t = 0.26s, and full-load declined to half load at t = 0.91s (the timing range accords to t = 0.26s and t = 0.91s are assumed from the beginning of these waveforms in Fig. 11(a) and (b)). The experimental results of the output voltage and current of the proposed converter by using the conventional PI and the proposed controllers are presented in Fig. 11(a) and (b), respectively. As can be simply found from Fig. 11(a), the output voltage response sustains a constant value. The earliest transient of the CH2 at t = 0.26s illustrates the output voltage undershoot, which its amplitude is approximately 50V, and the next transient at t = 0.91s shows the output voltage overshoot which is also about 50V. The settling time of the output voltage by the PI controller shows the controller's response time is about 50ms for both of the power alterations. Additionally, in Fig. 11 (b), the experimental results of the proposed controller are shown. The earliest transient of CH2 at t = 0.23s and the next one at t = 0.91s match the output voltage undershoot and overshoot respectively, which are approximately 20V, and about 13ms settling time shown for both of the power alterations of 50% to 100% and vice versa. Also, the steady-state error which is shown in Fig. 11(a), is eliminated by the ISMC controller. As a conclude, the output current alteration in Fig. 11(b) shows the faster response time of the proposed controller compared with the PI controller, which is shown in Fig. 11(a).

C. PRACTICAL RESULT OF THE CONDUCTED EMI
For measuring the conducted EMI, a setup consisting of a CISPR22 LISN, and a GWINSTEK GSP-830 spectrum analyzer is used. The proposed converter's EMI at full-load and the hard-switching counterpart's EMI is measured. The conditions and the components of both converters are the same. Also, the LISN is positioned between the power supply with 30V, and the input of the converter and the spectrum analyzer is located on RS [17]. The major contribution of common-mode noise to differential-mode noise is achieved on peak detect mode. Figure 12 illustrates the total conducted EMI of the hard-switched counterpart and the proposed converter. Under CISPR 22 standard, the frequency range of the conducted EMI is bounded from 150 kHz to 30MHz by the horizontal axis [10], [11]. The vertical axis shows the electromagnetic interference value which is limited between 20dBµV and 100dBµV. Figure 12(a) illustrates the EMI of the hard-switched counterpart with 80dBµV and the Fig. 12(b) shows the EMI of the proposed converter. It is understood by Fig. 12 that the proposed converter's EMI peak is approximately 8dBµV less than the hard-switching counterpart.

V. CONCLUSION
In the presented paper, a high step-up PWM non-isolated DC-DC converter with soft switching operations is proposed. The converter's diodes and MOSFETs are operated under soft switching conditions, which improve the reverse recovery problem, the efficiency, and the conducted EMI of the proposed converter. The main switch operates under ZVS condition. Thus, the capacitive turn-on losses is ignored. Moreover, a control method based on ISMC is presented, which regulates the converter's output voltage during the load variations. The presented theoretical analysis is confirmed through experimental tests under full-load for soft switching conditions and under half-load and full-load for the controller strategy. The experimental results show the soft-switching conditions for all the semiconductors, and the proposed controller has about 37ms faster transient response and approximately 30V less over/undershoot peak compared to the conventional PI controller. Furthermore, based on the EMI experimental results, the proposed converter has 8dBµV less EMI than the hard-switched counterpart in peak detect mode. In addition, compared to the hard-switched counterpart, the measured efficiency of the proposed converter is improved by 6.31%. HASSAN HAES ALHELOU (Senior Member, IEEE) is currently with Tishreen University, Syria. He is also with the School of Electrical and Electronic Engineering, University College Dublin, Ireland. He has participated in more than 15 industrial projects. He has published more than 160 research articles in high-quality peerreviewed journals and international conferences. He is included in the 2018 Publons list of the top 1% best reviewer and researchers in the field of engineering in the world. His research interests include power system operation, power system dynamics and control, smart grids, micro-grids, demand response, and load shedding. He was a recipient of the Outstanding Reviewer Award from many journals, such as Energy Conversion and Management (ECM), ISA Transactions, and Applied Energy. He was also a recipient of the Best Young Researcher in the Arab Student Forum Creative among 61 researchers from 16 countries at Alexandria University, Egypt, in 2011. He has performed more than 800 reviews for high prestigious journals, including IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, IEEE TRANSACTIONS ON POWER SYSTEMS, and International Journal of Electrical Power and Energy Systems. VOLUME 10, 2022