Performance Analysis of Multi-Carrier PWM and Space Vector Modulation Techniques for Five-Phase Three-Level Neutral Point Clamped Inverter

In industries, the demand for multi-phase Multi-Level Inverters (MLIs) increases in medium and high voltage applications due to its advantages over 3-phase MLIs. The multi-phase motors have reduced switching loss, Common Mode Voltage (CMV) and voltage stress across switches. Thus the interest on multi-phase inverter drive is also increasing in recent years. The controlling of inverter drive is done by Pulse Width Modulation (PWM) techniques which is majorly classified as Multi-Carrier PWM (MCPWM) and Space Vector Modulation Techniques (SVM). The controlling of inverter is done by comparing analog signals in MCPWM, while in SVM technique the digital pulse is generated which reduces the computational time. In MLI, the dc-link voltage should be balanced to obtain better efficiency of the inverter. The dc-link voltage balancing can be acknowledged by calculating the Neutral Point Fluctuation (NPF). Similarly, the reduction of CMV is also very important as it is responsible for the generation of bearing current of the motors. This paper discusses various PWM techniques like PD, POD, APOD, IC, PSC, VFC PWM and SVM (general SVM, OFV and SVM with Zero CMV) for 5-phase NPC 3L Inverter. The Optimized Five Vector (OFV) which has 113 vectors is preferred than normal SVM as it has inequality relationship between 5-phase voltages. Though OFV gives better results in terms of higher output voltage and lower NPF, the CMV is not eliminated. To eliminate CMV, 51 vectors that generates Zero CMV is selected to drive the inverter where output voltage and NPF is also improved. However, due to the presence of x-y components in this technique the distortion is present. Thus SVM with 31 vectors is proposed in this paper where the x-y components are neglected to reduce the distortion. The performance of the inverter drive is enhanced by applying SVM with 31 vectors. The NPF, CMV and losses are calculated for all PWM techniques, also the THD performances of an inverter is found for various techniques. The simulation is carried out for all PWM techniques and the results are verified by experimental results.


I. INTRODUCTION
The MLIs have gained more attraction for controlling motor drives with high voltage and current ratings [1]. The MLIs are most commonly categorized into Neutral-Point Clamped Inverter (NPC), Flying Capacitor Inverter and Cascaded H-Bridge Inverter [2][3][4][5]. Among these three types, NPC draws the industry attraction due to small electromagnetic interference and increased efficiency. NPC inverters mathematical calculations and operational limitations are reviewed in [6]. Though NPC is well established in MV high power application, it has certain challenges like power quality improvement, rejection of Common Mode Voltage (CMV) and DC-Link Capacitor balancing [7]. Several strategies have been taken into consideration to improve power quality, CMV and reduction of Total Harmonic Distortion (THD) [8][9][10]. The inverter drive is controlled by providing PWM strategies which are categorized as Multi-carrier PWM, Selective Harmonic Elimination PWM [11] and Space Vector Modulation [12].
In MCPWM, PWM is generated by changing the level and phase of carrier signals. The level-shifted PWM like Phase Disposition (PD), Phase Opposition Disposition (POD) and Alternate Phase Opposition Disposition (APOD) are discussed in [13][14][15]. In phase-shifting carrier PWM (PSC PWM), the power loss in the semiconductor switches is equally distributed [16][17][18]. The Interleaved Carrier (IC) PWM techniques is discussed in [19,20]. An investigation is done for level-shifted PWM, phase-shifted PWM and IC PWM in [21,22] which proposes that the PD PWM technique gives a better THD profile among phase-shifted and level-shifted PWM techniques. The current harmonics and current per phase are high in 3-phase motors. This issue can be reduced by using the 5-phase motors [23] and the torque ripple frequency is also increased which is given as 2n±1, where n is the number of phases [24].
The 5-phase motors are preferred in high-power applications like air crafts, locomotive tractions, hybrid and electric vehicles, etc., [25]. The PWM control techniques for 5-phase inverters are discussed in various papers over the past decades. The PD PWM technique is applied in [26] where the voltage balancing is also done. The harmonic distortion factor for 5-phase PWM techniques is compared among PD, POD, APOD and PS PWM where the POD technique provides the highest harmonic distortion factor [27]. Various PWM techniques are compared for 5-phase Open-End Winding topology [28]. The PD technique offers a better THD profile compared to other PWM techniques. Several research studies have compared PWM techniques in a 5-phase inverter [29][30][31][32]. In this paper, various MCPWM is discussed along with IC PWM and Variable Frequency Carrier (VFC) PWM technique for 5-phase load that can generate Three Level (3L) output.
The research SVM techniques for 5-phase inverter is majorly done for two-level inverters [33,34] and the control techniques of 5-phase two-level inverters [35,36]. SVM techniques for 5-phase 3L NPC are discussed in this paper, where 243 vectors are available [37,38]. However, only 113 vectors are utilized to produce desired voltage at d-q subspace and maintain zero average voltage at x-y sub-space which is named as Optimized Five Vector [39,40]. Many control strategies like Model Predictive Control, Direct Torque Control, Field Oriented Control has been discussed in [41 -43]. The CMV responsible for bearing current can be eliminated by selecting 51 vectors that generate zero CMV [44]. The voltage distortion is further reduced by reducing the switching vectors to 31 which is proposed in this paper. As the 5-phase inverter is getting more attention in the industries, a comparative study for various MCPWM and SVM techniques for 5-phase loads is done in this paper. Section II is explained about structure, CMV, NPF and loss calculations of 5-phase NPC-MLI. In section III, various PWM and SVM strategies are discussed. The section IV comprises of simulation results for MCPWM and SVM techniques of 5-phase 3L NPC MLI. The experimentation is done and their results are presented in section V and followed by a conclusion in section VI.

II. 5-phase NPC-MLI
The multi-phase drive has advantages over the traditional 3-phase drive. The multi-phase drive has higher reliability, reduced harmonic current losses and current per phase, less noise, fault tolerance and efficiency are improved. The 3L NPC-MLI for 5-phase load is displayed in Fig.1. The five legs of inverter are shared by two dc-link capacitors (C1 and C2) with a common dc source Vdc. This topology consists of twenty semiconductor switching devices (S1A-S4E) and ten clamping diodes (D1A-D2E). In phase-A, the Switches S1A and S3A are complement to each other, similarly, the switches S2A and S4A are complement to each other. ON, then output will be +Vdc/2. When the bottom two switches S3A and S4A are turned ON, then output will be -Vdc/2. The output will be Zero when switches S1A and S4A are in ON condition. The modes of operation for 3L NPC inverter are shown in Fig. 2.

A. Neutral Point Fluctuation:
In NPC-MLI, two dc-link capacitors are used in parallel to dc voltage source (Vdc). The voltage across both capacitors should be equal (Vdc/2). Still, the dc-link voltages are not balanced owing to the unequal commutation of the switches and injection of third harmonic current in neutral point. This variation of voltages at a neutral point is called Neutral Point Fluctuation. The NPF is calculated by using the formula given below   where Vc2 is the voltage across C2 capacitor and Vdc is the input voltage. The 3L NPC inverter has 4 operating areas during the change of switching states. The flow of Neutral Point Current is shown in Fig. 3 and the commutation loop in Fig. 4.

B. Common Mode Voltage
The average sum of instant voltage is called commonmode voltage (CMV). It is also known as the voltage between the neutral point of load and the inverter's ground. CMV for the 5-phase inverter is given as = + + + +

5
(2) where Van, Vbn, Vcn, Vdn and Ven are the voltage between phase and neutral of load. The high frequency model for 5-phase load is shown in Fig. 5 (a) where R is the resistance of stator winding per phase, L is self-inductance and Cw is a capacitance between neutral of star-connected winding and phase winding of stator, Cg is a stray capacitance between the neutral point of stator winding and ground potential. The voltage and current equations of each phase in the high-frequency model are given in Table 2.
The common-mode current of the inverter will be flowing through stray capacitance Cg and calculated from Eqn. 3.
The common-mode model for 5-phase load is presented in Fig. 5 (b) in which lo, Ro and Cwo are the zero-sequence component of L, R and C respectively. The differential mode model is presented in Fig. 5 (c) in which lq, Rq and Cwq are the q-axis component of L, R and C respectively, while the d-axis model will be same as the q-axis model.
The admittance transfer function for the common-mode model (Yo) is described as in Eqn. 4 which can be derived from

C. Losses Calculation
In an inverter, the power electronic switches are turned ON and OFF, leading to an increase in junction temperature. This increase in temperature is due to switching and conduction loss of switching devices. Thus, the switching loss and conduction loss are considered for loss calculation [45,46].

1) Conduction Losses
When the switch is turned ON, the voltage drop across collector and emitter terminal (VCE) is multiplied by current will result in conduction losses. When the switch is turned The average current, RMS current and conduction loss for switch S1A are given in Eqn. 8, 9 and 10. The conduction loss for switch S4A is same as in S1A.
The average current, RMS current and conduction loss for switch S2A are given in Eqn. 11, 12 and 13. The conduction loss for switch S3A is same as in S2A. The average current, RMS current and conduction loss for diodes (D) which is parallel to the switches S1A, S2A, S3A and S4A are given in Eqn. 14, 15 and 16. The conduction loss for the diodes parallel to switches are equal.

2) Switching Losses
The current will start rising during the turn-on period even before voltage drops to forward voltage drop. Likewise, the voltage will start rising during the turn-off period even before the current reduces to forward leakage current. The losses occur during turn-on and turn-off time is called as switching loss and it is expressed as = + 2 (20) The switching losses can be minimized by selecting proper PWM techniques which has less switching loss. The switching loss at switches S1A, S2A, S3A and S4A and the diodes D1A, D2A, D3A and D4A is given in Eqn. 21-24. (1 + cos ∅)

III. PWM Strategies for Multilevel converters
In Multi-level converter applications, many PWM strategies like MCPWM and SVM are available. The MCPWM scheme is usually classified into Level Shifting (LS) PWM, PSC PWM and VFC PWM. The LS PWM techniques are further classified into PD, POD and APOD PWM. The carrier signal required for MCPWM is n-1 carrier, where n is number of levels in line voltage. IC PWM method is also considered with other MCPWM techniques. The SVM schemes for generating 3L output are also considered here. The output voltage and THD performances are studied for different PWM techniques.

A. Phase Disposition (PD) PWM
In the PD PWM technique, the amplitude and frequency of all carrier signals are same, however, all carriers are displaced to different positions. The arrangements of reference and carrier signals for a 3L inverter are shown in Fig. 6 (a). In this technique, high-frequency carrier signals also can be used. The expression for modulation index and frequency ratio is given as Where Ac and Am are the amplitude of carrier and modulating signal respectively, meanwhile fc and the fm are the frequencies of carrier and modulating signal respectively. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

B. Phase Opposition Disposition (POD) PWM
In POD PWM technique also, amplitude and frequency of all carrier signals are maintained constant. However, the phase angles of carrier signals below and above zero reference are shifted by 180 o . The arrangement of carrier signals shown in Fig. 6 (b) is for 3L inverter. This method is a combination of phase opposition and phase disposition methods. The carriers above zero reference generate positive levels, while the carriers below zero reference produce negative levels. The zero level is generated without the help of carrier signals.

C. Alternative Phase Opposition Disposition (APOD) PWM
All the carrier signals have same amplitude and frequency in APOD PWM technique however the phase angle of alternate carriers is shifted by 180 o as shown in Fig. 6 (c), which is shown for 3L inverter. The carriers above and below zero reference are used to produce positive levels and negative levels. The voltage stress is reduced to some extent with this technique. It can be noted that POD and the APOD techniques will give similar results for 3L inverters, while they are different for higher-level inverters. If the level is higher than three, then POD and APOD give different outputs in which the APOD technique provides better THD performances.

D. Interleaved Carrier (IC) PWM
In IC PWM, the amplitude and frequency of all carrier signals are the same. On the other hand, they will overlap each other. Some parts of the upper carrier will be overlapped with the lower carrier signal and vice versa. This technique will improve the output voltage and reduce THD. The positive and negative levels will be generated using upper and lower carriers. The carrier and reference signal arrangements for 3L IC PWM technique are shown in the Fig. 6 (d).

E. Phase Shifting Carrier (PSC) PWM
In the PSC PWM technique, all carrier signals' levels are the same; however, the phase of every carrier signal is moved by certain degrees that result in a stepped output waveform. The amplitude and frequency of the carrier signal are identical for all carriers. The phase-shifting degree is based on the number of carriers used. The carrier and reference signal arrangements of 3L PSC PWM are shown in Fig. 6 (e).

F. Variable Frequency Carrier (VFC) PWM
In the VFC PWM technique, all carriers will not have same frequency. Some of the carriers will have different frequencies. The carrier and reference signal arrangements of 3L VFC PWM are shown in Fig. 6 (f). The carriers above zero level generate positive levels and the carriers below zero level generates negative levels.

G. Space Vector Modulation (SVM)
In 5-phase 3L NPC MLI, the possibilities of switching states are 3 5 = 243. Out of these switching vectors, 3 are zero vectors and the remaining 240 are active vectors. Two vector spaces are available for the 5-phase system, namely d-q space and x-y space. The space vector voltages Vdq and Vxy are calculated from Eqn. 27  The phase voltage across stator winding can be given as Where Sa, Sb, Sc, Sd and Se (+1, 0 or -1) are the switching states of a, b, c, d and e phases.
The space vector diagram for d-q space model is shown in Fig. 7. The space vector has ten sectors each separated by 36 o from one another. There are two vertices in 5-phase SVM, one is the Vertex vector whose angle is (θ = 0 o , 36 o , 72 o , so on) and the other is a non-vertex vector whose angle is (θ = 18 o , 54 o , 90 o so on). From the space vector diagram, it can be noticed that 120 vectors are present in vertex vector out of which 60 vectors are redundant, while 40 vectors are available in non-vertex vector and 80 vectors will be placed in between vertex and non-vertex with the remaining three vectors are zero vectors placed at the origin. The magnitude of vertex and non-vertex vectors is given in table 3. It can be noticed that where, To, T1, T2, T3 and T4 are the dwell time of switching vectors ⃗⃗⃗ , 1 ⃗⃗⃗ , 2 ⃗⃗⃗ , 3 ⃗⃗⃗ and 4 ⃗⃗⃗ of selected switching sequence, Ts is the switching period, ⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗ and ⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗⃗ are the reference output voltage in d-q and x-y space.
The matrix form of dwell time is given in Eqn. 33.

1) Optimized Five Vector SVM
The general 3L SVM which has 243 vectors are not used because of the inequality relationship between 5-phase voltages. Thus, vectors are reduced to 113 vectors to produce desired voltage reference at d-q subspace and maintain zeroaverage voltage at x-y subspace. These vectors are called OFV. The sector I representation of SVM and OFV SVM for 5-phase 3L is shown in Fig. 8 (a) and Fig. 8 (b). The balancing of DC-link capacitor voltage in unbalanced condition is taken care by redundant vectors available in SVM. The OFV has 21 vectors in sector I compared to general 3L SVM which has 39 vectors. The magnitudes of vectors in OFV SVM are 0.2Vdc, 0.324Vdc, 0.4Vdc, 0.524Vdc and 0.647Vdc. The potential switching sequences based on OFV have been listed in Table 4. The sub-region 1 to 10 will produce desired voltage reference in d-q sub-space by removing the x-y sub-space vectors whose regions are shown in Fig. 8 (b). The switching sequences 11 to 16 are unable to nullify x-y sub-space vectors. Thus, the switching sequences at region A1 to K1 are only employed in OFV SVM. The SVM of OFV for 5-phase 3L NPC MLI at d-q subspace is shown in Fig. 9. The sub-region 1 to 10 will produce desired voltage reference in d-q sub-space by removing the x-y sub-space vectors whose regions are shown in Fig. 8 (b). The switching sequences 11 to 16 are unable to nullify x-y sub-space vectors. Thus, the switching sequences at region A1 to K1 are only employed in OFV SVM. The SVM of OFV for 5-phase 3L NPC MLI at d-q subspace is shown in Fig. 9.

2) SVM with Zero CMV
To eliminate CMV in a 5-phase inverter, the SVM for 3L is developed with 51 selected vectors with zero CMV which is listed in Table. 5. The SVM diagram is shown in Fig. 10 (a) and 10 (b) are for d-q plane and x-y plane which produce zero CMV at the output. The voltage resulting from 51 vectors will have distortion due to the availability of x-y components. By neglecting the vectors in x-y components, the distortion is further reduced as shown in Fig. 11 (a) and Fig. 11 (b) x axis y axis (b)

IV. Simulation Results
The performance of 5-phase 3L NPC is investigated for various MCPWM schemes with MATLAB/ Simulink. A 300V DC supply is given with a 100µF capacitor and 10 kHz switching frequency. The RL load is considered with R=10Ω and L=2mH. The output voltage and THD waveform for different PWM schemes with a modulation index of 1 (Mi =1) are shown in Fig. 12. The Third Harmonic Injection (THI) is done for all MC PWM techniques and their performances are also studied.
The line voltage, CMV, DC link voltages and voltage THD of PD is shown in Fig. 12 (a), where quarter symmetry of the output voltage is maintained in this technique. The voltage is read as 170.80V, while CMV is high in this condition. The NPF is at considerable range as VC1 and VC2 is obtained in the range of 140 V to 160V. The results of POD technique are shown in Fig. 12 (b), output voltage is maintained similar to PD technique whereas CMV is reduced to 39V and THD is increased to 39.81%. In APOD technique, all output results will be similar to POD technique as both This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. techniques are equivalent in 3L PWM generation. The results of APOD technique is shown in Fig. 12(c). The phase of the carrier signal is varied by keeping the amplitude and frequency unchanged. The voltage level drop in this technique while CMV and THD is increased as shown in Fig. 12(d), however NPF is very low in PSC PWM. The performances of IC and VFC PWM techniques are displayed in Fig. 12 (e) and Fig. 12 (f). The output voltage is increased in IC PWM whereas CMV is very high with voltage THD also reads more. The VFC PWM technique reduces the voltage THD level to match with PD PWM technique, however NPF touches the highest value among other PWM techniques which increases the dc-link balancing issue. Fig. 13 (a). The output voltage drops a little compared to normal PO PWM technique whereas NPF is increased by the injection of third harmonic content to the carrier signal. The results of POD THI and APOD THI are given in Fig. 13 (b) and Fig. 13 (c). The output voltage, CMV, DC link voltage and voltage THD is similar in both conditions for 3L inverter. The performance of PSC THI like line voltage, voltage THD, CMV and DC link voltage is obtained as in Fig. 13 (d). The THD is reduced after few orders and it is increased again near to the 200 th order. Though NPF is less, CMV is high in this technique. The output of NPC inverter when applied with IC THI and VFC THI are shown in Fig. 13 (e) and Fig. 13 (f). The output voltage of IC THI PWM technique is higher (169.90V) than other THI technique whereas voltage THD and CMV is higher in this technique. The results of VFC THI reads the output voltage as 159.20V with THD is better among other THI techniques while NPF is high in this types as the frequency of each carrier signal is different.

The 3 rd harmonic is injected in all types of MC PWM; the line voltage, THD, CMV and DC link voltage for PD Third Harmonic Injection (THI) is shown in
The simulation for SVM techniques is also done using MATLAB Simulink. The results of OFV SVM are shown in Fig. 14  generates Zero CMV and its results are shown in Fig. 14 (b). It is noted that the CMV is Zero in this SVM technique, with voltage THD is obtained as 25.62% and NPF as 1.33%. The output performance are increased as the switching states are reduced in this type. The switching vectors are further reduced to 31 which reduces the ripples with output voltage, THD, CMV and DC link voltages are shown in Fig. 14 (c). The CMV is Zero and the voltage THD is obtained as 24.86%. The NPF is also less in this type and it is calculated as 1.44%. It can be noticed that in 51 vectors and 31 vectors types of SVM, the CMV is completely eliminated. The simulation is carried out for different modulation indices (Mi=1, 0.9, 0.8, …, 0.1). The inverter output voltage is almost identical for all PWM techniques, however THD performance is the one to be noticed among these techniques. The PD and VFC provide better THD performances 20.33% and 22.66%, respectively, compared to other PWM techniques. When the modulation index is reduced, the output line voltage is considerably reduced for all PWM techniques. If the modulation index is 0.5 or less, then the output voltage will be of 2L instead of 3L. The inverter output line voltage, THD%, CMV and NPF% obtained from various PWM schemes at different modulation indices are listed in Table 6. The NPF% is calculated for different PWM techniques across dc-link capacitors. From the table it is noted that the IC PWM technique has least fluctuation in capacitor voltages while the VFC PWM technique has highest fluctuation among the discussed PWM. The NPF for all PWM technique is in acceptance range. The CMV for various PWM Techniques are also listed and it is found that CMV is less for POD and APOD techniques while it is high in IC PWM technique.
The results from the above table shows that PD and VFC PWM techniques provide better THD performance, while NPF is high. The NPF is less in PSC PWM techniques when compared to other MC PWM techniques while the CMV is less in POD and APOD PWM techniques. The results of SVM techniques are better when compared to MC PWM techniques, also the CMV is eliminated in both 51 vectors and 31 vectors. However, the voltage ripple and THD is less in 31 vectors.
The losses of power switching devices are obtained through PLECS software. The conduction loss of each switch in phase A is shown in Fig. 15, while the switching loss across four switches is shown in Fig.16 with their diode loss in Fig. 17. The average overall loss for switches in phase A is shown in Fig. 18. The losses in other phases will be identical to the losses obtained in phase A. Thus, phase A is represented in the following figures. It can be noticed that the conduction loss is high in middle switches (S2 and S3) as it is conducted for a longer period of time than S1 and S4. In VFC PWM, the conduction loss is high in S1 and S2 as the frequency is less in top carrier while the conduction loss is less in S3 and S4 as shown in Fig. 15 (a).
The conduction loss in slightly higher when THI is done and it is noticed in Fig. 16. This is due to the variation in pulses as third harmonic content is included with normal reference signals. The diode loss is very low in all PWM techniques except PSC PWM as shown in Fig.17, the increase in diode loss is due to continuous conduction in all switches. The average total loss is high in IC, VFC, IC THI and VFC THI PWM techniques. The overall loss is less in other techniques, whereas the loss is even reduced in OFV SVM techniques as it given digital pulse to the switches. The losses are even further reduced in 51 vector and 31 vector type of SVM. This reduction is due to the usage of less number of switching states. The efficiency of the inverter is calculated as Efficiency, ƞ = Where Ploss=Pcon+Psw, Pcon is the conduction loss of semiconductor switches and diodes, while Psw is switching loss of semiconductor switches and diodes in the inverter. The efficiency of inverter is calculated for different PWM techniques for the modulation index is 1 and shown in Fig.19.
From the results, it is observed that the performances of NPC inverter is better when applying SVM PWM. The efficiency is noted high with the proposed 31 vectors SVM among other PWM techniques.

V. Experimental Results
The experimentation for 5-phase NPC MLI is done by using RL load with R=10Ω and L=2mH. IGBT -SKM100GM12T4 switches are used to develop the 5-phase NPC MLI. The pulse for inverter is given by RTGUI -FPGA controller. The DC link voltage is considered 300V with the capacitor rated as 100µF. The experimental setup for 5-phase NPC 3L inverter is developed as shown in Fig. 20. The THD analysis of the experimentation is done by TEKTRONIX MSO 046. The 5-phase NPC MLI is applied with PD, POD,  APOD, IC, PSC, VFC, PD THI, POD THI, APOD THI, IC  THI, PSC THI, VFC THI, OFV SVM, 51 vector SVM , and proposed 31 vector SVM techniques and the corresponding results are obtained.
The experiment is carried out by providing PD PWM techniques and the output voltage, CMV, dc-link voltage and THD is obtained as shown in Fig. 21 (a). The NPF is read as 6.67% and voltage THD is 22.35%. In POD PWM technique, CMV is reduced to 50V with NPF is same as previous condition while voltage THD is higher (40.19%) as shown in Fig. 21 (b). The results of APOD technique is similar to POD technique in 3L inverter as shown in Fig. 21 (c). The NPF is read as 2% in PSC PWM technique, while THD is 48.56% as shown in Fig. 21 (d). In IC PWM, NPF is read as 3.33% while, CMV and voltage THD is high as 150V and 42.28% which is displayed in Fig. 21 (e). In VFC PWM technique, though voltage THD is less, CMV and NPF is high as shown in Fig. 21 (f).
The third harmonic reference is injected and the experiment is conducted for 5-phase 3L NPC inverter. The output voltage, CMV, dc-link voltage and voltage THD for PD THI PWM technique is shown in Fig. 22 (a). NPF and voltage THD is high when THI is done. The results of POD THI and APOD THI are similar to each other, CMV and NPF in these techniques are 50V and 13.33% respectively which is shown in Fig. 22 (b) and Fig. 22 (c). Though CMV less in this type, NPF and voltage THD remain high. The PSC THI technique reads CMV as 150V, NPF is 3.33% and voltage THD is 46.39% as shown in Fig. 22 (d). The CMV for IC THI is obtained also high as 150V with NPF as 6.67% and voltage THD as 59.25% as displayed in Fig. 22 (e). The CMV of VFC THI technique is obtained as 100V with NPF is read as 13.33% and the voltage THD in this technique is 40.93% which is lower among THI PWM types as shown in Fig. 22  This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

FIGURE 22. Experimentation results -Line voltage, CMV, DC link voltages and THD for (a) PD THI, (b) POD THI, (c) APOD THI, (d) PSC THI, (e) IC THI, (f) VFC THI
The SVM is applied and results are obtained. The output voltage, CMV, DC link voltage and THD of OFV are shown in Fig. 23 (a). The result of NPC MLI when 51 vectors are applied is shown in Fig. 23 (b) while the performance of NPC MLI for proposed 31 vectors is shown in Fig. 23 (c). The voltage THD of 51 vectors and 31 vectors are obtained as 26.78% and 25.12% respectively. The results of SVM indicate that its performance is better than MC PWM techniques. The CMV is also eliminated in 51 vectors and 31 vectors SVM while THD is lower in later technique. The DClink capacitor voltage is very close to balancing voltage, which means NPF is very low in SVM techniques. This shows that the SVM techniques with reduced switching states provide better results such as zero CMV, reduced NPF and lower voltage THD.
The experimentation is done by applying different modulation indices (Mi = 1, 0.6 and 0.3) and corresponding results are listed in Table. 7. The results obtained show that the SVM technique gives better performances in all parameters as obtained in simulation. The PWM techniques for the 5-phase NPC inverter discussed in this paper can be applied in motor driving applications in the industries. The SVM with a reduced number of switching states provides better performance with zero CMV to the inverter. The leakage current is reduced by eliminating the CMV from the inverter.   The results of different PWM and SVM technique are compared by plotting the graph in Fig. 24 and Fig. 25. The results of NPC inverter when modulation index is taken as 1 is considered for the above graph which shows that the output voltage is high in the proposed SVM with 31 vector and the CMV is eliminated and read as 0V. Furthermore, the THD % and NPF % is less in this type compared to the other PWM techniques. Thus the proposed SVM with 31 vectors offers better results which can be applicable for motor applications in the industries as well as in Electric Vehicles.

VI. CONCLUSION
The output performances of 5-phase NPC inverter is analyzed with various PWM and SVM techniques. The load considered for this work is RL load with R=10Ω and L=2mH. The MCPWM techniques like PD, POD, APOD, PSCIC and VFC are implemented for 5-phase 3L NPC inverter. The harmonic content and NPF is better in PD PWM technique, however the CMV is high in this type, while in POD PWM technique CMV and NPF is reduced nevertheless the THD is increased to 40.19%. Similar results are obtained for APOD technique as it is equivalent to POD technique in case of 3L inverter. Though NPF is very less in PSC PWM, CMV is increased in addition to reduction in output voltage. In IC PWM technique, the output voltage is higher than any other technique besides reduction in THD and NPF, however CMV is at the peak which leads to the flow of leakage current when motor load is used. The VFC PWM technique provides better output voltage and THD performance, nevertheless the CMV and NPF is high in this condition. The 5-phase NPC inverter performance is investigated by injecting the third harmonic content with the reference signal. The output voltage of PD THI, POD THI, APOD THI and VFC THI are in the equal range, however the PSC THI provide lower output voltage while the IC THI gives the highest among THI types. In terms of voltage THD, the PD THI and VFC THI offers better results whereas THD is poor in IC THI technique. The CMV is very high in PSC THI and IC THI technique, nevertheless POD THI and APOD THI provides less CMV. In case of NPF, the PSC THI gives lower fluctuation however other THI PWM techniques delivers high fluctuation in the neutral point of the inverter.
Based on the analysis of various MCPWM techniques, it is noted that each techniques gives better result in any one or two parameter; however it fails in remaining parameters.  APOD  PSC  IC  VFC   PD THI  POD THI  APOD THI  PSC THI  IC THI  VFC THI  OFV   51 vectors  31 vectors Percentage % THD % NPF %