A K/Ka-band Switchless Reconfigurable 65nm CMOS LNA based on Suspended Substrate Coupled Line

This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author’s best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band’s drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP1dB & OP1dB), third-order input & output intercept point (IIP3 & OIP3) of -17/-16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61×0.92 mm2.


I. INTRODUCTION
The K-Ka band  GHz) applications such as 5th generation (5G) networking, radar, and astronomy detection depend heavily on wideband mm-wave front-ends. As one of the most critical active components, low noise amplifiers (LNAs) are the primary block in the mm-wave receiver front-ends. We expect to achieve a low noise figure, a modest gain, high linearity, and low power consumption for LNAs to extend the dynamic range and increase the receiver system's sensitivity, which adds to the LNA design challenges. In recent decades exhaustive research has been done on wideband LNAs [1]. The most promising topology used to realize the ultra-wideband LNA is a Distributed amplifier (DA) [2]. But DA is not suitable in many cases because of low unity-gain bandwidth, high NF, and larger area. Other bandwidth enhancement techniques such as shunt-resistive feedback, dual inductive peaking, improving dynamic load, a frequency-dependent feedback loop (FDFL), split common gate transistor (SCGT) have been reported in [3][4][5][6]. These proposed bandwidth enhancement techniques degrade the other RF parameters like noise performance. The main issue with wideband LNAs is that they amplify the unwanted signal with the desired signal, degrading the receiver's sensitivity. Reconfigurable LNAs are another approach to develop wideband receivers with good interference rejection, and many multiband LNAs are reported in [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. A reconfigurable multimode LNA realized by incorporating a switched multitap transformer into the input matching network and tunable load based on electrical and magnetic tuning operating at 3 single bands (24/28/39 GHz) is proposed in [8], but they have less gain around 12 dB and high NF up to 5 dB.
A 28/60 GHz reconfigurable LNA based on RF switches for mm-wave transceivers is reported in [12]. This LNA also suffers from a feeble gain of 14 dB with an NF of 4.6 dB. By using highly optimized RF switches, they still suffer ON-loss of 1 dB and OFF-loss of 0.7 dB. A 44/60 GHz reconfigurable LNA based on Q-enhanced metamaterial transmission lines is presented in [13], but they have a high NF of 5.6 dB and IIP3 of -14 dBm. The notable advantage of this paper is that it achieves 30 dB rejection between two bands, but they didn't achieve good FoM, and this design is not suitable for wideband frequency of operation. A dualband switchable LNA based on LC tunable tank and tunable stub based on Hetero-junction Bipolar Transistor (HBT) switch working at 28/60 GHz is reported in [14] though it achieves decent NF of 2.8 dB, low power consumption; still, it suffers from low gain. The demerit is that the LC tank impedance matching is not suitable for wideband impedance matching. A tri-band reconfigurable LNA operating at 24/33/50 GHz based on triple coupling transformer (TCT) with additional gain boosting to achieve gain up to 32 dB with 6 dB minimum noise figure is reported in [15]. This TCT technique introduces high NF and poor linearity and also not suitable for wideband design. In these reported works [12][13][14][15], and [26] all operating at mm-wave bands have only a narrow band of operation and had their design tradeoffs, and their design techniques are not suitable for the wideband application, which is our goal here.
A 22-47 GHz, two-stage LNA with 22.2 dB peak gain and 4.3 dB NF using coupled L-type interstage matching inductors is presented in [16]. This LNA has one of the best design tradeoffs with only the demerit of poor IIP3. The research gap is that the asymmetric L-type inductors used here cause instability due to pole-zero shifts. A concurrent dual-band single-ended input to differential output LNA operating at 18-25 GHz and 33-46 GHz with 16 dB gain and 4.3 dB NF is reported in [17]. Though this LNA has low gain and high NF, it also has a unique advantage in controlling stopband rejection and passband gain balance simultaneously. A 21-41 GHz, 28.5 dB gain, and 3.2 dB NF LNA with triple coupled transformer technique is reported in [18]. This LNA also has one of the best design tradeoffs; still, no LNA has achieved ultra-low NF with high linearity. In [19], LNA with 12.8 dB gain and 1.4 dB NF operating at 14-31 GHz is reported. This is the only LNA among all the discussed works with NF less than 1.5 dB, but gain falls below 13 dB. A 19.5-28.5 GHz variable low power LNA achieving a gain of 7.8-23.2 dB with a 0.4-1.6 V supply is presented in [20]; still, they have not achieved ultra-low NF. The literature reported in [16][17][18][19][20] is suitable for wideband mm-wave receiver systems, but they have their limitations of the LNA design tradeoffs in gain, NF, linearity, power consumptions, area, and sensitivity. The point of observations in all the reported works except [13] uses one or more components such as tunable inductors, varactors, transformer, and RF switches, which require additional power supplies and are difficult to implement at high frequencies due to the associated loss and tradeoffs.
Considering the drawbacks of the bandwidth enhancement and other reconfigurable techniques for the ultra-wideband LNA, this article proposes a new switchless reconfigurable LNA based on the inter-stage and outputstage Suspended Substrate Coupled Line (SSCL) for the full K-Ka band  GHz. An 8-20 GHz switchless dualband reconfigurable LNA and a 6-18 GHz switchless dualband reconfigurable power amplifier (PA) are reported in [21][22] using a coupled line-based diplexer which is similar to the SSCL used in this article.
This article presents a K/Ka dual-band switchless reconfigurable and wideband LNA based on interstage and output stage SSCL, providing the necessary LNA matching network. The statistical analysis and Design of Experiments (DoE) are done to test the design's yield and robustness. The DoE analysis notices each passive and active parameter's percentage contribution and sensitivity to the overall response. This makes the optimization an easy task as it identifies the sensitive parameters perfectly. This CMOS-based switchless reconfigurable LNA has achieved a better LNA design tradeoff with better harmonics and linearity performance comparing the reported works. This paper outline is presented as: Section 2 explains the suspended substrate coupled line's design and consideration. The LNA circuit design stages and considerations are discussed in section 3, while the experimental setup, simulation, and measured results with the comparison table are presented in section 4. Finally, the conclusion is given in section 5.

A. COUPLED LINE ANALYSIS
The traditional coupled microstrip line is shown in Fig. 1 (a). Its analysis is discussed here as an example to understand the proposed SSCL's dual-band activity mechanism better. In a coupled line structure, the load impedance Zload is considered to be the same as the coupled line's characteristic impedance 0 . In this case, the output voltage of the coupled port (port 3) and through port (port 2) can be determined as a function of the input voltage denoted in equations (1) and (2). [23] ℎ ℎ = . √1 − 2 √1 − 2 cos + sin = .
(2) Here is the coupled line's coupling coefficient, and θ is the coupled line's electrical length. According to the current flow mechanism in an electromagnetic situation, there are two modes for the coupled line. In the first mode, the current flows down on the conductor with a contra-flow current back up the other conductor caused by displacement current coupling between the two conductors. This is termed the odd mode current, and it has associated odd mode characteristic impedance 0 . In the other mode, the current flow by displacement current between each center conductor carries the same polarity and the common ground between them. Hence this is called even mode current, and it has an associated even mode characteristic impedance 0 [23]. The coupling coefficient as a function of odd mode impedance 0 and even mode impedance 0 can be given by: The relation between the characteristic impedance 0 and odd and even mode impedance is given as: (1) and (2), we can see that at very low frequencies or terse line length (θ << π/2), nearly all input power is transmitted to port 2, with none being coupled to port 3. The maximum coupled power transmitted to port 3 is achieved at θ = π/2 or l = λ/4, as shown in Fig. 2(a). From Fig. 2(a), the maximum coupled power is approximately -3 dB with a long-coupled line (θ = π/2) for K = 0.7. For this reason, the traditional coupled line structure in Fig. 1(a) may not be applicable in the proposed LNA.
The scattering matrix [S] of a four-port coupled-line coupler can be written as: The modified structure of the coupled line is shown in Fig. 1(b). The isolated port (port 4) is grounded initially (without C8). The shunt capacitance C7 at port 2 (through port) behaves as a short circuit for ideal high-band frequencies operation. The input impedance matching network of the low-band LNA absorbs this C7 during the low-band frequency operation. The through port output signal is mirrored with an 180 0 phase shift and re-enters the coupled line. The signal is then coupled to the isolated port, mirrored with an 180 0 phase shift, and finally emerges from the coupled port (port 3) with the initial coupled signal. The output voltage of isolated port (port 4) and coupled port (port 3) as a function of the input voltage can be expressed as: It is noted that from (8), the coupled port output signal consists of two parts: . . 2 . . The phase difference between the two parts is identical to the coupled line's double electrical length, as shown in Fig. 2(b). When the coupled line's electrical length is λ/4, the phase difference between the two parts of the coupled power is 180 0 ; then, the minimum coupled power is obtained. Fig.  2(b) and Fig. 2(c) illustrate the coupled power in port 3 of the coupled line shown in Fig. 1(b) according to different coupling coefficient and electrical lengths (θ) of the coupled line. When the electrical length is 30 0 ~ 45 0 or 135 0 ~ 150 0 , maximum coupled power can be obtained for a definite . Here, a maximum coupled power of -4 dB can only be achieved for K= 0.7, which is not sufficient to be used in the interstage of the LNA. The phase difference between the two parts of the coupled power . . 2 . is the cause of inadequate coupled power, and it is shown in Fig. 2(d). To compensate for the phase difference between two parts of the coupled power, we added a shunt capacitance C8 to the isolated port. The phase response after adding C8 is shown in Fig. 2(e). From VOLUME XX, 2022 3 Fig. 2(e), without the capacitor C8, there is 180 0 phase difference when the electrical length is 90 0 or λ/4, causing minimum coupling, but after adding shunt capacitance C8 to the isolated port, the phase difference becomes 0 0 at λ/4 electrical length which maximizes the coupling.

B. COMPARISON OF BASIC COUPLED LINE STRUCTURE WITH PROPOSED SSCL
The proposed coupled line is first tested with the traditional microstrip line (MCL) and Shielded microstrip line (SMCL) shown in Fig. 3(a) as an inter-stage. The schematic of the proposed structure shown in Fig. 4(a) is simulated, and the simulation results in Fig. 5(a) show that the coupling power suffers a loss of around -4.8 dB because of the described reason in the above subsection. Due to dispersion, fringing effects, and other EM losses due to mm-waves, the losses occur. We have already developed a wafer-level integrated suspended substrate line (SSL) platform to avoid these losses in our previous work [24]. The metal layers M1 and M4 act as the ground, while the metal layer M3 act as a signal trace. The metal layer M2 act as a signal reflection path. When the signal passes through the metal layer M3 at such high mm-wave bands, an EM field is developed, which causes a fringing effect around the M3 layer. Additional losses such as dispersion loss and dielectric loss also occur. But here, as the signal trace path has a reflection path (M2) and ground layers (M1, M4), the developed EM field is confined to the air cavity. This allows us to have the minimum loss, and we receive high coupled power at the output.

III. DESIGN AND ANALYSIS OF CMOS LNA
The simplified block showing the proposed dual-band switchless reconfigurable LNA topology is shown in Fig. 6. It consists of three Amplifier stages: Broadband drive stage, High-band (Ka) stage, and Low-band (K) stage and two coupled stages based on SSCL as Inter-stage SSCL and Outer-stage SSCL. Common source (CS) topology is used in all three amplifier stages. Here transmission lines are used instead of spiral inductors to save the chip area and reduce other associated losses. The long transmission lines are bent to achieve a compact chip area. Transmission lines and bypass capacitors are used as bias circuits for the proposed LNA instead of using a standard quarter-wave long transformer to behave like short circuits within the designed bandwidth and reduce chip area. The complete schematic of the proposed reconfigurable LNA is shown in Fig. 7. This proposed reconfigurable Switchless LNA can be used in three modes: Dual-band mode, high-band (Ka) band mode, and low-band (K) band mode. Vd3 is turned off for the Ka-band stage, K band stage Vd2 is turned off, and both are in ON condition for the dual-band stage. The circuit design of the broadband drive stage and high-band low-band stage are detailed as follows.

A. BROADBAND DRIVE STAGE DESIGN
The broadband drive stage is the first block in the proposed reconfigurable LNA topology where the input RF signal is received, as shown in Fig. 7. This stage plays a decisive role in the input matching and noise performance of the reconfigurable LNA. It consists of a two cascaded CS stage using the transistor M1 and M2 operating at gate voltage Vg1 = 0.43 V. Capacitors (C1, C2) and transmission lines with length L1 and width W1 form the input matching network where the signal passes and is fed to the gate of the transistor M1. The drain and gate voltage are given to M1 and M2 through transmission lines with lengths L3, L2, and L5, L4.
Source degeneration is incorporated through the transmission line with length Ls1 and Ls2 to M1 and M2 to bring the optimum impedance for minimum NF close to the complex conjugate of input impedance. By this, low NF and input impedance matching is achieved simultaneously. The capacitor C3 is used to block the dc from flowing from the first stage to the next stage. The input impedance ( ) of the circuit, which depends mainly on this stage, can be calculated using the simplified small-signal model of the first CS stage is shown in Fig. 8.
denotes the combined impedances of all the preceding stages. For simplicity, impedance in transmission lines such as L2, LS1, and L3 is considered inductance. In Fig. 8 denotes the transconductance of the transistor M1, whose value is proportional to the width of the transistor, and denotes gate-source and drain-source capacitance, and denotes equivalent input and output Miller capacitance due to gate-drain capacitance .
The simulated S-parameters of the broadband drive stage are shown in Fig. 9. The gain (S21) is above 20 dB till 33 GHz, and it falls to 16 dB at 40 GHz. The return loss (S11) is well below -10 dB from 18-40 GHz.

B. DESIGN OF HIGH BAND (KA) AND LOW BAND (K) LNA STAGES
The broadband drive stage's simulated results show that the gain variation is 7 dB from 18-40 GHz. Though it is challenging to maintain almost gain flatness over the entire bandwidth, the high-band and low-band stages consist of two transistors employed to reduce the gain variation below 2 dB. The low-band stage consists of transistor M5 and M6 in CS two-stage cascaded topology operating in the gate voltage Vg3 = 0.4 V. This stage is designed to operate only in the K band, from 18-24 GHz. The simulated S-parameters of the low-band drive stage are shown in Fig. 10(a). The gain (S21) is 10 dB to 8 dB in the passband of 18-24 GHz, then it falls to 2 dB at 40 GHz. The return loss (S11) is well below -10 dB from 18-24 GHz, and high reflections are received above this range.
The high-band stage consists of transistor M3 and M4 in CS two-stage cascaded topology operating in the gate voltage Vg2 = 0.47 V. This stage is designed to operate only in the Ka-band, which is from 25-40 GHz. The simulated Sparameters of the high-band drive stage are shown in Fig.  10(b). The gain (S21) is 12 dB to 10 dB in the passband of 25-40 GHz. The return loss (S11) is well below -10 dB from 25-40 GHz, and high reflections are received in the 18-24 GHz band. To avoid instabilities due to possible oscillation loops in the multi-device amplifier's complex structure or due to the device's nonlinear behavior, R-C resistive feedback using (R1, C10) at the gate and drain of the transistor M4 is incorporated. Connecting the coupled port (port 3) of the output stage SSCL directly to the 50 Ω output load is not advisable. This is because the SSCL is formed using stacked layer by layer formation in the substrate, which is challenging to connect to the output load directly. Also, the impedance of SSCL changes with a change in frequency, which is predominantly inductive. In some worst cases, the impedance may be purely inductive and may cause instability to the circuit. We have connected an R-C (R2-C17) circuit between the output stage SSCL and the output load to avoid these all. The connected R-C network neutralizes any abrupt change in inductive impedance that arises in the worst case and improves output matching(S22).

C. MERGING OF ALL STAGES
After individually designing and testing all the stages like SSCL interstage, SSCL output-stage, Broadband stage, High and low band stages. All the stages are connected, as shown in Fig. 6. The broadband drive stage's output is fed to port 1 of the SSCL interstage, where the signal got divided into two single bands as Ka-band and K-band. Based on the principle of SSCL as described in the previous section. The Ka-band is coupled through port 3 of SSCL, and the leftover K band passes through port 2 and is fed to the corresponding amplifier stages. After getting amplification from the corresponding stages, two single-band signals merged at the output using the designed output stage SSCL. As already described, SSCL at output merges the signal from port 2 and port 3 and gives the broadband signal at port 1 as output. Table 1 shows the total dc drain current in various modes of operation and the drain voltage states of single-band transistors used to achieve switch-free dual-band operation.

D. NOISE FIGURE ANALYSIS
The general method to convert any noisy multi-port network to an equivalent noise-less network plus standard current and voltage noises at the input port is depicted as follows to analyze the complete LNA's noise figure. Representing all of the internal noise sources as current noises, general noisy multi-port can be explained as a combination of a noise-less multi-port and some current noises at the ports, as shown in Fig. 11(a). The input and output ports are represented as port1 and port 2, respectively, and Fig. 11(b) shows the equivalent standard multi-port network.  To find equivalent current and voltage source noises at the input port, we describe the network by Y matrix: Equivalent current and voltage noises in Fig. 11 This expression is used in the above equation The optimum source admittance _ for minimum noise factor is calculated as: The minimum noise figure is calculated as: Finally, the noise factor of the multi-port is calculated as: The simulated NF of the individual broadband, high band, and low band stages are shown in Fig. 12. The broadband stage NF follows a U shape curve with a maximum value of 1.15 dB at 40 GHz. This shows that the technique discussed above optimized the NF to a low value of 1.15 dB only. The NF of the low band stage is around 1.6 dB in the K band, and it increases above this band. The NF of the high band stage is around 1.2 dB in the Ka-band and is highly intolerable up to 7 dB in the K band.

E. STATISTICAL ANALYSIS
As the device parameters are subject to Process Voltage and Temperature (PVT) variation, the yield analysis is essential in estimating the actual yield and the confidence levels. The confidence level is the area under a normal Gaussian curve over a given number of standard deviations. The designed LNA is tested for 5% and 1% error tolerance under Gaussian distribution. The results for NF, Gain, and return loss are shown in Fig.13 (a), (b), and (c), respectively. It is noted that the stable gain of 25 dB, NF of 1.6 dB, and return loss of -11 dB are achieved with 1% tolerance. It results in a yield estimation of 100%, giving a 99.7% confidence level for 1000 iterations. But for the 5% tolerance yield estimation, 10% of the iteration failed to yield 90%. The parameters' limit is set as a minimum 20 dB gain, maximum 2 dB NF, and minimum -10 dB return loss. But usually, CMOS process PVT variations are less than 1% only, which means the designed reconfigurable switchless LNA provides a stable and accurate design.

F. DOE ANALYSIS
Design of Experiments (DOE) is a data-driven technique for robust design to understand the design parameter's contribution in achieving the specific goal like a flat gain of 25 dB, NF of 1.5 dB with good return loss, and high linearity. The design parameter's percentage contribution to the specific goal, such as NF, Gain, and return loss, are shown in Fig. 14. To test at both the K and Ka bands, the LNA is tested at 20 GHz and 35 GHz, shown in Fig. 14 (a) and (b), respectively. It is observed that the same parameter from the broadband drive stage contributes to design goals with the only variation in the percentage sensitivity. It is also observed that the parameter M5_W from the low-band stage contributes to gain a little at 20 GHz, and the parameter M3_W from the high-band stage contributes to gain a little at 35 GHz.

FIGURE 14. Design parameter contribution at (a) Low-band at 20 GHz (b) High-band at 35 GHz
The design parameters which contribute less than 1% are neglected in Fig. 14 for better clarity. Extra care has been taken for these sensitive and contributing parameters while fabricating to get reliable, accurate measurement results.

IV. PERFORMANCE ANALYSIS OF RECONFIGURABLE SWITCHLESS LNA
The LNA is implemented using RF 65nm process design technology and fabricated using the Magnachip Hynix Samsung process. The fabricated chip is a layer-by-layer formation using substrates and metal oxide metal (MoM) capacitors. The six-layer copper interconnects fabricated using nano-clustering silica. These six layers are stacked up on silicon wafers along with other components of LNA to provide flexibility, which in turn avoids parasitic losses by CMOS mm-wave process. The stacking multi-layer process is used for mounting the passive components on the silicon die. The microchip die photograph of the fabricated LNA is shown in Fig. 15(a). The total core area of the chip is 0.61×0.92 mm 2 . The full-wave simulation and measurement readings of LNA have characterized performance parameters with optimized dimensions to achieve high performance over a wideband of operation. VOLUME XX, 2022 3

A. EXPERIMENTAL VERIFICATION
For on-wafer LNA, S-parameters and noise performance are measured using micro-probe sets such as Karl Suss (KSM) microprobe system, PNA-X (N5245B) Keysight's technologies up to 50 GHz, and Cascade Microtech microprobe tips, with 100 µm pitch. The PNA and microprobes must be calibrated before going to measurement. The short-open-load-through calibration technique has been employed for microprobe systems.  The calibration sets include gold short circuits (Short), gold open pads (Open), and gold plus thin film resistors (Load or Match) [25]. The complete measurement setup using PNA-X is shown in Fig. 15(b). PNA-X uses a more accurate cold source method than the usual Y-factor method, where the NF of the device under test (DUT) is calculated from two separate measurements. The first measurement is the available gain of the DUT. This is done with great precision using vector air corrected S-parameters measurement. The second measurement is the noise power coming from the output of the DUT, with room temperature (25 0 C) loaded at the input. This PNA-X noise figure option includes a built-in low noise receiver with 3 different gain settings. This means a broad range of devices with any combination of gain and NF can be tested without the need for any additional hardware.
Vector Air corrected S-parameters correct the mismatch between the imperfect source match of the test system and the input impedance of the DUT. Mismatch correction is also applied when measuring the DUT output noise power. The source mismatch caused by the KSM probes and microprobetips is corrected using the standard impedance tuner module. By varying the source impedance presented to the input of the DUT, and measuring the resulting NF, accurate 50 Ω NF is calculated. Pasternack PE6085 50 Ω impedance converter adapter connector is used for good output match of S22. The comparison of state-of-art LNA with other reported ones is shown in Table 3. The FoM expressions are given below.
The input and output impedance of the dual-band LNA is shown as a smith chart in Fig 16. It is noted that the input impedance starts from the capacitive region at 18 GHz marked as m3 and touches the real axis at 20 GHz. It then follows the inductive region and again touches the real axis at 28 GHz, marked as m2. From m2, it again passes through the capacitive region and touches the real axis at the end frequency 40 GHz marked as m1.
(a) (b) The output impedance is capacitive dominance from starting frequency 18 GHz marked as m6 and meets the real axis at 25 GHz, marked as m4. Hence it is noted that the Kband (18)(19)(20)(21)(22)(23)(24) GHz impedance is capacitive, and Ka-band (25-40) GHz impedance is inductive. For the RF frequency range, the stability is determined using the K factor that depends on S-parameters. To achieve stability, it is required to have K >1 and Δ <1.
Both K and Δ are given by the equations given below. LNA stability is measured and plotted in Fig. 17. It is noted that the designed reconfigurable switchless LNA is unconditionally stable in the desired frequency range of 18 to 40 GHz. The measured and simulated NF and S-parameters of the proposed reconfigurable switchless LNA in all three modes, dual-band mode, high-band mode, and low-band mode, are shown in Fig. 18 to Fig. 20. It is noted that from Fig.18, the NF varies from 1.05 dB at 18 GHz to 1.2 dB at 40 GHz in dual-band mode with a minimum of around 0.9 dB at 21 GHz. The gain of 27 dB with only 0.2 dB variation and 2 VOLUME XX, 2022 3 dB variation is achieved across the entire frequency range of 18 to 24 GHz and 24 to 40 GHz, as seen from Fig. 19(a). This is phenomenal performance in terms of gain for having such a slight variation for the entire 22 GHz bandwidth comparing the reported works discussed. The return loss (S11) is sufficiently well below 10 dB to avoid any reflection. Other parameters, such as S12 and S22, also show satisfactory performance. The simulated Group delay and the phase response for the proposed LNA in dual-band are shown in Fig. 19(b) also provides satisfactory performance. As seen in Fig. 20(a), a stable gain of 22 dB with 2 dB variation is achieved in Ka-band mode (25 to 40 GHz) in high-band mode. NF of around 1.5 dB is achieved with a good return loss of below 10 dB. In low-band mode, as seen in Fig. 20(b) stable gain of 25 dB with 1 dB variation is achieved in K-band mode (18 to 24 GHz). NF of around 1.5 dB is achieved with a good return loss of below 10 dB. The linearity analysis has been done to compute the fundamental signal's harmonics, such as third-order harmonics. Here as we are dealing with mm-wave bands till 40 GHz, even second harmonics analysis has been done. The measured values at 20 GHz (K-band) and 35 GHz (Ka-band) are shown in Fig. 21(a) and (b), respectively. From the plot, it is noted that at 20 GHz Input 1-dB compression point (IP1dB) of -17 dBm, output 1-dB compression point (OP1dB) of +7.1 dBm, Input intercept Third-order point (IIP3) of 0 dBm, output intercept Third-order point (OIP3) of +25 dBm and Input intercept second-order point (IIP2) of +5 dBm are achieved.
Similarly, it is observed from the Fig. 21(b) at 35 GHz Input 1-dB compression point (IP1dB) of -16 dBm, output 1-dB compression point (OP1dB) of +6.4 dBm, Input intercept Third-order point (IIP3) of 0 dBm, output intercept Thirdorder point (OIP3) of +23 dBm and Input intercept secondorder point (IIP2) of +5 dBm are achieved. This value shows that our designed reconfigurable switchless LNA performs better in suppressing harmonics to provide high linearity to the input. This is achieved by using optimized source degeneration using transmission lines at each CS stage to keep the gain under 28 dB and proposed SSCL at interstage and at the output to reduce the intermodulation distortion effects (IMD). The IIP3 increases automatically once the IMD reduces, which results in a better linear device.

V. CONCLUSION
This article demonstrates and fabricated a switch-free reconfigurable dual-band LNA operating in 18-40 GHz in 65nm CMOS technology. We theoretically analyzed and developed Suspended Substrate Coupled Lines (SSCL) in the interstage and output-stage to obtain frequency reconfigurable capabilities. The input dual-band signals are divided into single band amplifiers by the interstage SSCL and combined in the output port by the output-stage SSCL. The unit transistor of the proposed LNA is designed in Common-Source (CS) architecture and uses the inductive effect of transmission lines to degenerate the source by obtaining low noise and input matching simultaneously. The fabricated 0.56 mm 2 LNA chip exhibits a measured smallsignal gain of 27-27.2 dB with around 1 dB NF in [18][19][20][21][22][23][24] GHz and a measured small-signal gain of 25-27 dB with around 1.2 dB NF in 24-40 GHz. The statistical and DoE analysis is presented to test the yield and robustness of the design. The designed LNA is highly linear by achieving I1dB of -16 dBm, IIP3 of 0 dBm, O1dB of +6.4 dBm, OIP3 of +25 dBm. The proposed chip also consumes only 25.7 mW in the dual-band operation. The reason for having three modes of operation is to minimize the power dissipation by 8-9 mW which comes in handy during limited power supply in remote areas. The state of art comparison shows that the designed LNA achieves reasonably well mean values in all parameters, leading to achieving the highest FOM among the reported works and applied in modern wireless receiver systems.