A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET

This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system. An Equivalent Split-Capacitor is proposed to enlarge redundancy range and alleviate the settling error of the bridge capacitor array. A hybrid capacitor switching procedure is adopted to reduce power consumption and the variation of input common-mode voltage of the comparator. Measurement results of the 14-nm CMOS SAR-ADC achieves a SNDR of 61.29 dB and 58.34dB at low and Nyquist input frequency, respectively, resulting in figure-of-merits(FoMs) of 8.2 and 11.15fJ/conversion-step, respectively. The ADC core occupies an active area 0.112mm2.


I. INTRODUCTION
With the rapid development of wireless communication and integrated circuit, people's daily life is becoming more convenient and intelligent. Electronic devices such as tablet computers and smart phones are playing a more and more important role in people's daily life. The battery life has a great impact on the experience of these handheld devices. Low-power chips are very helpful to prolong the service time of the battery. The ADC is a very important block in the wireless receiver, it converts analog signals to the digital signals and then transmits them to digital baseband. Therefore, the ADC with low-power architecture becomes more and more attractive. The successive approximation register(SAR) ADC is compatible with advanced digital technology and the structure of SAR ADC is simple, which makes it energy-efficient architecture. It takes several cycles for SAR ADC to finish one conversion. However, with the continuous advancement of CMOS technology, the channel length of the transistor keeps decreasing. The conversion speed of SAR ADC has been greatly improved. The singlechannel SAR ADC with 10-bit to 12-bit resolutions has achieved a sampling rate of more than 100MS/s with excellent efficiency and small area [1]- [3]. Although pipelined ADC also achieves the 100MS/s-200MS/s sampling rates with 10 bit-12 bit, pipelined ADC consumes more power than SAR ADC under advanced CMOS technology. The pipelined ADC needs highperformance operational amplifier, which burns up power. Besides, the supply voltage becomes lower and lower in advanced CMOS process, which reduces the output signal swing and gain of the operational amplifier. Increasing sampling capacitance can improve signal-to-noise ratio(SNR) of the pipelined ADC. However, it generates a lot of power dissipation. The SAR ADC consists of DAC capacitor array, comparator and digital control logic circuit. The dynamic comparator is preferred because lower power can be achieved. More and more digital control logic circuits are realized by dynamic logic, which consumes less power dissipation. Besides, advanced technology is beneficial to save power dissipation of asynchronous digital control circuit. Many energy-efficient capacitor switching processes can greatly save the power dissipation of the capacitor array. capacitor array converges from half of the Vref to ground, which causes the dynamic offset of the comparator and degrades the performance of ADC. Vcm-based switching method [15] also greatly reduces the power dissipation. However, it requires an extra reference voltage Vcm and lots of switches. The variation of the common mode voltage is reduced by 50% in switchback switching process [16]. Bidirectional single-side switch technique [17] reduces the capacitance by 75% and the variation of common mode voltage by 50%. However, it needs complex control logic and extra reference voltage Vcm. The reference voltage in the SAR ADC is provided by reference voltage buffer(RVB). When off-chip the RVB is adopted in SAR ADC, the parasitic inductance of bonding wires and PCB trace causes the reference voltage ringing and degrades the settling of DAC. A large decoupling capacitor is needed to stabilize the reference voltage, which occupies the a lot of area. The parasitic inductance of bonding wires does not exit when on-chip RVB is adopted. The on-chip RVB can reduce the power consumption and chip size. This paper proposed an equivalent split-capacitor which can enlarge redundancy range and alleviate the settling error of the bridge capacitor array. Besides, a hybrid capacitor switching process is proposed. Compared with the monotonic switching process, the proposed hybrid capacitor switching process reduces the variation of common mode voltage by 93.75%. The reference voltage buffer and the clock generator have an important impact on the performance of the SAR ADC. The structure and design of these two blocks are also discussed in this paper. The proposed SAR ADC achieves 8.2fJ/conversion-step and occupies an active area 0.112mm 2 . The remainder of this paper is as follows. The section II presents the overall architecture of the proposed SAR ADC. The section III describes the proposed techniques, including an equivalent split-capacitor based on the bridge capacitor array and the hybrid switching procedure. The section IV presents key building blocks implementation, including bootstrapped switch, high-speed and low-noise comparator, digital control logic, reference voltage buffer and clock generator. The measurement results of proposed SAR ADC and comparison to recent works are showed in section V. Finally, the conclusion is summarized in section VI. Fig. 1 shows the overall architecture of the proposed SAR ADC. The top SAR ADC is composed of clock generator, reference voltage buffer and ADC core. Clock generator is used to provide the sampling clock for the bootstrapped switch. The vinclk and vipclk are differential sinusoidal signal with the frequency of the 400MHz. Clock generator VOLUME XX, 2017 1 FIGURE 1. The overall architecture of the proposed SAR ADC converts the differential input sinusoidal signal to singleended output square wave, then yields the square wave with a duty cycle of 25% though logical operation. The clock jitter of the clock generator will cause the uncertainty of the sampling time. The larger clock jitter is, that is, the higher uncertainty of the sampling time. As a result, the lower SNR can be achieved.

A. EQUIVALENT SPLIT-CAPACITOR
For SAR ADC with the binary weighted DAC capacitor array, the number of the unit capacitor increases exponential with the resolution. However, the bridge capacitor array has less number of unit capacitor compared with binary weighted DAC capacitor array. Thus, the bridge capacitor array has less interconnections, which can reduce the parasitic capacitance, power dissipation and improve the speed. Fig. 2 shows the conventional N-bit bridge DAC capacitor array. The bridge capacitor array is composed of p-bit LSB array and q-bit MSB array. The bridge capacitor Ca is not an integer but a fraction, which is not conducive to layout matching and causes the non-linearity. In Fig. 3,  the voltage R V is applied at the node 1 and the node 2 respectively. When the voltage R V  is applied at the node 1, the corresponding equivalent circuit is shown in Fig. 4.
is applied at the node 2, the corresponding equivalent circuit is shown in Fig. 5. In order to maintain correct weighting, the voltage . CMSBtotal is the sum of capacitance of the all capacitors in MSB array, CMSBtotal is shown as equation (1). CLSBtotal is the sum of capacitance of the all capacitors in the LSB array, CLSBtotal is shown as equation (2).
From the equation (5), the equation (6) can be obtained.
From the equation (6), as long as the value of K, p and Cd1 is appropriate, the integer Ca can be obtained. In this design, 12-bit DAC capacitor array is divided into 8-bit MSB array and 4-bit LSB array. In order to save the area, the K=1 in the equation (6). In the case K=1, p=4, the equation (6) can be written the equation (7).
In the equation (7), when Cd1 is equal to 15Cu, Ca is equal to 2Cu. When Cd1 is equal to 30Cu, Ca is equal to 3Cu. Too large Ca will cause large the parasitic capacitance, which is detrimental to the linearity of the ADC. In this design, Ca is equal to 3Cu. The DAC settling issues has become very serious in SAR ADC with 100MS/s. The SAR ADC can get the correct conversion only when settling error of DAC is less than 1/2LSB, which will consume a lot of power and reduce the speed of the ADC. The redundancy can alleviate the DAC settling issues. The Fig. 6 shows the 4-bit binary weight and non-binary weight with redundancy SAR search algorithm.

FIGURE 6. The 4-bit binary weight and non-binary weight with redundancy SAR search algorithm
In Fig. 6, the blue line represents the input signal of SAR ADC. The red line represents the search path with right decision. The green line represents the search path with wrong decision. In the binary-weight SAR ADC, right decimal output is 0×8+1×4+0×2+0×1=4. If the wrong decision occurs in the second comparison, the decimal output is 0×0+0×4+1×2+1×1=3. A wrong decision can not be corrected in this algorithm. In the non-binary weight with redundancy SAR ADC, the right decimal output is 0×7+0×3+1×2+1×2+0×1=4. If the wrong decision occurs in the second comparison, the decimal output is 0×7+1×3+0×2+0×2+1×1=4. In this redundant algorithm, a wrong decision can be corrected as long as subsequent comparisons are all correct. For M bit SAR ADC, it needs N (N>M) steps to finish conversion if the redundancy is introduced. Wj represents the weighting of the j-th step. If a wrong decision occurs in the j-th step, the error can be corrected when Wj must satisfy the equation (8).  12-bit DAC capacitor array is divided into 8-bit MSB array and 4-bit LSB array. There is no redundancy in the DAC capacitor array. Therefore, it can not alleviate settling issue of the DAC. The binary-scaled recombination method [11] is applied to bridge capacitor array in Fig. 8. In Fig. 8, the MSB capacitor C11 is divided in two parts, 56Cu and 8(2 3 )Cu. Next, 8Cu is divided into 2Cu, 2Cu, 2Cu, 1Cu and 1Cu respectively. These groups are added to other groups or inserted in MSB array. The same method is applied to LSB array. However, weighting of the capacitor C55 is 32LSB, the sum of total weighting of LSB array is 31LSB. The weighting of the capacitor C55 is larger than the sum of total weighting of LSB array. Therefore, there is no redundancy in the capacitor C55. The weighting of the capacitor C55 is large. If a wrong decision occurs in the comparison cycle corresponding to the capacitor C55, which will produce the wrong digital output and affect the performance of the ADC.

FIGURE 9. The proposed equivalent split-capacitor in bridge structure
Equivalent split-capacitor is proposed in Fig. 9 to solve the redundancy problem of the capacitor C55. The MSB capacitor C11 is divided in two groups, 56Cu and 8Cu. Next, 8Cu is divided into 2Cu, 2Cu, 1Cu, 1Cu, 1Cu, 1Cu. The capacitors 2Cu, 2Cu, 1Cu and 1Cu are added to the capacitors C8, C7, C6 and C5. 1Cu is inserted to MSB array to form the capacitor C55. The remaining purple 1Cu is ready to be allocated to the LSB array. Due to the existence of the bridge capacitor Ca, the purple capacitor 1Cu can not be directly placed in the LSB array. In the Fig. 9, the weighting of the capacitor C55 is 32LSB in the MSB array and the weighing of the capacitor C13 is the 2LSB in the LSB array. In other words, the weighting of the unit capacitor Cu is 32LSB in the MSB array and the weighting of the unit capacitor Cu is 2LSB in the LSB array. The weighting of the unit capacitor Cu in the MSB is 16 times the weighting of the unit capacitor Cu in the LSB array. Therefore, the purple the 1Cu in the MSB array is equivalent 16Cu in the LSB array. The 16Cu is called the equivalent bridge capacitor. When 16Cu is added to LSB array, the linearity of LSB array will change. The capacitor Cdummy changes from 30Cu to 14Cu to keep the linearity of ADC unchanged. The equivalent split capacitor 16Cu is divided into seven groups, 4Cu, 4Cu, 2Cu, 2Cu, 2Cu, 1Cu, 1Cu. These groups are added to other groups or inserted in LSB array. In Fig. 9, the sum of total weighting of LSB array is 63LSB, which is larger than the weighting of the capacitor C55. Therefore, there is redundancy in the capacitor C55. If a wrong judgment occurs in the comparison cycle corresponding to the capacitor C55, which can be corrected. Table 1 shows the comparison of redundant range with different redundant schemes. In the 8th cycle(the last cycle of MSB array), the redundant range is 0 LSB in [20] and the redundant range is 32 LSB in proposed equivalent splitcapacitor method. The weighting of the 8th cycle is relatively large. If the wrong decision is made in the 8th cycle, the performance of ADC will degrade. The proposed equivalent split-capacitor method can provide a certain range redundancy to tolerate DAC settling error. Besides, there is no redundancy in the 6th and the 7th cycle in [20]. However, the proposed method has redundancy in the 6th and the 7th cycle. Therefore, proposed hybrid redundancy is suitable for the bridge structure and high-resolution ADC. The digital output can be expressed as: (10)

FIGURE 10. Digital error correction operation
16-bit original output digital codes are converted to 12-bit binary codes by the logical operation in Fig. 10. The schematic of digital error correction(DEC) is showed in Fig.  11. The DEC is composed of 12 D-type Flip Flops(DFF) and 11 full-adders(FA). The CLKs is sampling clock from the clock generator in Fig. 11. Reducing the noise of the comparator requires a lot of power dissipation. The adaptive-tracking-average technique [19] is used to relax requirement for the noise of the comparator. In order to average the comapartor noise, the multiple comparison of LSB is used in the adaptive-tracking-average. In Fig.12, seven purple unit capacitors Ca1 to Ca7 are added to the DAC capacitor array to repeat LSB decision 7 times. In order to keep the weighting of the LSB array unchanged, Seven unit capacitors Ca1 to Ca7 are split from the capacitor Cdummy. As a result, the capacitor Cdummy changes from 14Cu to 7Cu. Fig. 12 is the DAC capacitor array with equivalent split-capacitor and the LSB averaging.

B. THE PROPOSED HYBRID CAPACITOR SWITCHING PROCEDURE
The power dissipation of DAC capacitor array accounts for a large proportion among SAR ADC power. The power dissipation of the DAC capacitor array is determined by the switching methods and the total capacitance of DAC capacitor array. The power dissipation produced by different switching procedures varies greatly for the same capaictor array. The conventional switching procedure is not energyefficient. The monotonic switching procedure [14] can greatly reduce the power consumption. Nevertheless, its common-mode voltage is not constant and changes from half of Vref to the ground in the process of the quantization, which causes the variation of comparator offset voltage and degrades the linearity of the SAR ADC. Compared with the monotonic switching process, the variation of the common mode voltage is reduced by 50% using the bidirectional single-side switching procedure . However, this variation is still relatively large and affects the dynamic offset of the comparator and SNR of SAR ADC. The hybrid capacitor switching procedure is proposed to reduce the variation of the common mode voltage and the power dissipation of the DAC capacitor array. Fig.13  After the second comparison, one of the MSB-1 capacitor is switched from ground to Vref. Then, the proposed process switches other capacitors from Vref to ground. The power consumption of each conversion process is shown in Fig. 13. VOLUME XX, 2017 1 The power consumption of the proposed hybrid capacitor switching process is 88.2% less than the conventional switching procedure and 37.5% less than the monotonic switching procedure. Table 2 shows power consumption of each output code for 4-bit the DAC capacitor array based on the the monotonic capacitor switching process and proposed hybrid capacitor switching process. For 4-bit SAR ADC, the LSB capacitor is not switched after the fourth comparison. Therefore, the power consumption corresponding to the output codes 0000 and 0001 is equal. The same is true for other output codes. The power dissipation corresponding to each binary digital output code of the proposed capacitor switching process is smaller than that of the monotonic capacitor switching process in the table 2. In Fig. 13, only the MSB capacitor is connected to the Vcm during the sampling. For N(N≥6) bit SAR ADC, when SAR ADC is sampling, the MSB, MSB-1 and MSB-2 capacitors are connected to Vcm. The MSB-4 capacitors are connected to ground and other capacitors are connected to Vref. The capacitor switching procedure is same as that in Fig. 13. The common mode voltage variation of DAC capacitor array is showed in Fig. 14. Common mode voltage changes from Vcm to ground in monotonic capacitor switching process. The common mode voltage variation is reduced by 50% and converges to Vcm in the bidirectional switching procedure. Common mode voltage variation is reduced by 93.75% and converges to the Vcm in the proposed switching process. Therefore, it alleviates the need for the special comparator and avoids the degradation of the linearity. In order to avoid Vcm, the MSB, MSB-1 and MSB-2 capacitors are divided VOLUME XX, 2017 1 into two equal halves. One half is connected to ground and other half is connected to Vref. The proposed capacitor switching procedure can not only reduce power consumption, but also reduce the variation of common mode voltage.

IV. IMPLEMENTATION OF KEY BUILDING BLOCKS
The fundamental building blocks of the proposed SAR ADC include the bootstrapped switch, the three-stage low-noise comparator, the asynchronous digital control logic, the DAC capacitor array, the reference voltage buffer and the clock generator. The design consideration of these building blocks are described in following subsections.

A. BOOTSTRAPPED SWITCH
The bootstrapped switch is used to sample the input signals to the DAC capacitor array. Therefore, it can affect the SNDR and SFDR of the SAR ADC. The performance of the bootstrapped switch will degrade at high frequency. In order to solve this problem, an improved bootstrapped switch is proposed in [21], as shown in Fig. 15 As a result, the capacitive load of the node VG is reduced and VG can quickly follow Vin. The bulks of transistors M7, M8, M9 and M3 in critical loops are tied to their sources to avoid body effect and reduce on-resistance. The bulk of the transistor M10 is tied to the bottom-plate of Cs. In the tracking state, the bulk and source of transistor M10 are connected together because transistor M10 is on. In hold state, the bulk of transistor M10 is connected to ground rather than input signal, which does not require a dummy transistor of M10 to eliminate input signal feedback in [11].

B. A THREE-STAGE COMPARATOR
The comparator has a great influence on the performance of SAR ADC. The noise of comparator affects the SNR of the SAR ADC. However, the tradeoff between the noise and power dissipation is not linear. The resolving time of comparator affects the speed of the ADC. Fig. 16 shows a multistage comparator with the inverter [8], which can VOLUME XX, 2017 1 achieve low noise and high speed. The first stage is the inverter with common mode voltage feedback, which can achieve high gain and suppress the noise and offset. The second stage is half latch, which can further amplify the signal. The third stage is the dynamic latch, which affects the resolving time of the comparator. Resistors R1 and R2 sense output voltage Vout_cm to control transistors M5 and M6, which can stabilize output common mode voltage. When ADC is sampling, CLKs is high and transistors M6 and M5 are off. As a result, the first stage does not work, which can save power dissipation. When CLKs is ground and CLKc is VDD, transistors M13 and M14 are off, transistors MS1 and MS2 are on, the nodes M and N are low. Transistors MS3 and MS4 are on, the nodes P and Q are high. At this time, the comparator are in reset state. When CLKs is low and CLKc is low, transistors M13 and M14 are on, the first stage compares the input differential signals Vin and Vip. The second stage forces one of the nodes M and N to be high and the other to be low. Transistors MS3 and MS4 in the third stage amplify outputs of the second pre-amplifier to the dynamic latch in the third stage, which forces one of nodes P and Q to be low and other to be high.

C. ASYNCHRONOUS DYNAMIC CONTROL LOGIC
In order to save the power dissipation and improve the speed, asynchronous dynamic control logic is used. Fig. 17 shows the dynamic logic control cell(DLCC  Fig. 18 and timing of asynchronous dynamic control logic is shown as Fig. 19.

D. CAPACITOR ARRAY
The Metal-Oxide-Metal(MOM) capacitor is selected as the unit capacitor of DAC capacitor array. Fig. 20 shows the structure of the unit capacitor, which is composed of 5layers  Fig. 22 is proposed to achieve good matching of DAC capacitor array. The purple DUM represents dummy capacitors in Fig. 22.    Fig. 23 is a two-stage amplifier. Fig. 24 shows the schematic of OTA. The first stage is differential amplifier with current mirror load. The second stage is common-source amplifier. When R2>1/gm7, the resistor R2 and the capacitor Cm form a left plane zero(1/(R2Cm)), which can compensate phase margin(PM) and reduce power consumption. Generally, 1/(3gm1)>R2>1/gm7.

F. CLOCK GENERATOR
Clock generator is used to provide the sampling clock for ADC. The clock jitter has a great impact on the performance of ADC. The larger clock jitter is, that is, the higher uncertainty of the sampling time. For sinusoidal signal of Vin=Acos(2fin), the clock jitter power is given by: Where, jitter is root-mean-square jitter. Clock generator with low clock jitter is very beneficial to high-resolution ADC. Fig. 25 shows low clock jitter circuit [23], which consists of three stages. The first stage is differential amplifier with active load, which can suppress the common-mode noise. Resistors R1 and R2 form common-mode feedback circuit, which provides appropriate static working point for the node A and stabilize voltage at the node A. The second stage is differential-to-single-ended conversion, which has a large impact on the clock edge slope and clock jitter. The third stage is digital buffer, which is used to generate square wave. The digital buffer needs to have large gain and produce noise as less as possible.

V. MEASURMENT RESULTS
The prototype SAR ADC is fabricated using 1P8M 14-nm CMOS FinFET technology. The chip photograph and the layout zoomed-in view of the SAR ADC is showed in Fig. 26. The SAR ADC core occupies an active area of 0.112mm 2 . Fig.27 shows the measured spectrum with inputs at 4.85MHz and 49.85MHz with 100MS/s Fs when LSB averaging is not carried out. At Fin=4.85MHz, the measured SNDR and SFDR are 58.67dB and 80.36dB, respectively. When input frequency increases to 49.85MHz, the measured SNDR and SFDR are 56.01dB and 76.5dB. Fig. 28 shows the measured spectrum with inputs at 4.85MHz and 49.85MHz with 100MS/s Fs when LSB averaging is carried out. At Fin= 4.85MHz, the measured the SNDR and SFDR are 61.29dB and 82.08dB. When input frequency increases to 49.85MHz, the measured the SNDR and SFDR are 58.34dB and 78.02dB. At Fin =4.85MHz, SNDR, SFDR and ENOB are increased by 2.62dB, 1.72dB and 0.44bit respectively. At Fin=49.85MHz, SNDR, SFDR and ENOB are increased by 2.33dB, 1.52dB and 0.39bit, respectively. Through comparison between Fig. 27 and Fig. 28, the LSB averaging is helpful to improve the ENOB.   The power consumption of ADC is 0.78mW including comparator, bootstrapped switch, DAC capacitor array and digital control logic. This power consumption does not include the power consumption of the reference voltage buffer and the clock generator. The proposed SAR ADC achieved a figure-of-merit(FOM) of 8.2 and 11.15 fJ/conversion-step at low-frequency input and Nyquist input frequency, respectively. Table.3 summaries the performance and compares our work with recent arts, the proposed SAR ADC has reached the level of the research front. Besides, the FoM of the proposed SAR ADC at Nyquist is lowest among ADCs [11], [20], [24], [25], [26].

VI. CONCLUSION
A 12-bit 100MS/s SAR ADC with the clock generator and on-chip reference voltage buffer is presented in this paper. In order to enlarge the redundancy range and alleviate settling error of bridge DAC capacitor array, an equivalent bridgecapacitor is proposed. A hybrid capacitor switching procedure is adopted to reduce power dissipation and the variation of input common-mode voltage of the comparator. Fabricated in 14nm CMOS FinFET technology, the proposed