A High Step-up Sextuple Voltage Boosting 13S-13L Inverter with Fewer Switch Count

In this work, a high step-up sextuple voltage boosting 13 switches – 13 level inverter (SVB-13S -13LI) structure was proposed through a pulse width modulation technique with selective harmonic elimination. This topology can deliver six times of voltage boosting capability. A single voltage source, 13 switches, two diodes, and three capacitors are utilized to obtain the objective of this research. This work carried out various tests on the proposed topology to find efficiency, voltage stress, total standing voltage, and voltage gain. The detailed comparative study of existing inverter topologies is tabulated to prove the proposed topology has a better performance. The main feature of this topology is six times voltage boosting, a minimum number of switches, less voltage stress, and a self-balanced floating capacitor. Further to isolate or eliminate the undesired low order harmonics the particle swarm optimization-based SHPWM Technique is used. For proving the above-mentioned merits, the simulation was carried out using MATLAB SIMULINK and their corresponding THD results are compared with different Modulation indexes. Also, experimental results are validated by the FPGA SPARTAN 6E controller and their cost function [CF] for the unit price ($) are compared with the state-of-art literature 13-level inverters.


I. INTRODUCTION
To promote adoptable of the conventional variable voltage-frequency as an efficient model, the process of DC-AC power conversion plays a vital role. Among many conventional methods, a multilevel inverter (MLIs) is wellknown and widely deployed across most power-consuming applications. That demands include flexible AC transmission systems or renewable energy resources and high voltage transmission or variable frequency drives on several standard voltages [1]. Conventional MLIs topologies in the literature and listed as 1. Neutral-Point-Clamped MLI 2. Cascade H-Bridge MLI 3. Diode-clamped MLI 4. Flying capacitor MLI [FC-MLI] is expressed from [2]. In PV applications, SCMLIs can achieve advantageous features like voltage boosting, capacitor voltage self-balancing, grid compatible distortionfree waveform, and reduction in filter size [3]. In [4], [7] though the peak inverse voltage of the switches is low, more switching devices are needed even for low voltage gain. In [5], six times voltage booting is achievable, but the rating of the switches is high which also limits the charging of the capacitor when the modulation index is low. SCMLIs introduced [6], incorporation of typical H-bridge with switched capacitor demands more semiconductor devices. In addition to that, the capacitor voltage balancing becomes difficult which also increases the cost function. In [8], though high voltage gain is attained with less number of switches, the topology suffers from high TSV and high rating capacitors. To meet the above challenges by implementing a multilevel inverter with the switched capacitor (MLI-SCs) and to get a boosting ability, it is to be designed in such a way that it hosts a smaller transformer (or) inductor than by using the SCMLI. The challenge of implementing T-type topology based on SCs is its high unreliability for Highvoltage application and its back-end H-bridge [HB] generates a negative voltage level [9].
The maximum output voltage endured must use the four-power semiconductor switch on the HB [10]. Fig. 1 depicts the block diagram of the SHE technique for the multilevel inverter. By making a series-parallel input voltage source in SCs get a grid of the necessity of the exterior boosting circuit that makes the circuit simpler [11], [12]. From the literature study, it is clear that if the output level has been attempted to increase, that consequently makes the circuit more complex and becomes costlier to implement.
Thus, various studies were done in the literature that is significantly involved in minimizing the usage of components such as voltage sources, power semiconductor switches, and switched capacitors. For example, 13-Level -MLIs [13], comprising of 4 DC sources and 10 switches. A kite structure of ML's is developed in [14] to reduce the number of sources. A K-Type SC-MLIs presented in [15] required a single DC source, four capacitors, and 14 switching devices. Yet, the voltage boosting the ability of underlying switches, the generated total blocking voltage [TBV], the complex designing of the gate driving circuit, and the charge for each level remain as significant challenges. To address the challenges, the 13-Level ML's have been put forth. A 13-level ML Topology has been designed with only 10 switch counts comprising four capacitors and four diodes with a boosting ability of six which makes it as costeffective. To obtain better output voltage and the maximum total stored energy in the 4 capacitors and requires two more switch counts [16]. The author proposed in [17], use an Hbridge in the back end of the inverter. So, the output voltage level not be varied flexibly. A new SSC unit is proposed but it also needs two more additional isolated DC sources and if the levels are increased and the SSC switched capacitor bas- -ed inverter and it requires three more switches to reach its peak voltage [18]. In [19], the author proposes a switched capacitor-based inverter and it requires three more switches to reach its peak voltage. Recently published many topologies are presented [20] - [24]. Every structure has some issues in the performance. More active devices utilized, more blocking voltages, Continuously more stresses occurred in two switches and obtained less voltage magnitude, back to back switches and additional two capacitors are connected and the total cost is increased and not suitable for high voltage applications. To reach a peak voltage authors utilized 11 devices [25]. An H-bridge-based multilevel inverter, requires an isolated input voltage in [26] Asynchronous particle swarm optimization the genetic algorithm is very difficult to implement. In [27], the author proposes a topology with H-bridge and more voltage stress across the H-bridge. So in this research, a new effective 13S-13LMLI (13 switch -13 level) inverter topology is proposed with minimum switched capacitor and least switch count. This topology is capable to generate six times of voltage gain factor than conventional topologies through the literature. Several major features of this topology are mentioned as follows 1. It requires only thirteen switches to generate thirteen levels of synthesized voltage (Vab) 2. Each switch is limited to thrice the voltage (Vdc) ensuring a maximum blocking voltage. 3. Possessing lower THD as compared to other MLIs. 4. It requires only three Switched Capacitors that were balanced without any additional circuits and sensors. The circuit description, modes of operation of the 13-level proposed SCs MLI, and Level shifted modulation index was discussed in section II. The optimization of SHE-PWM with PSO implemented in the proposed topology has been discussed in Section III. In section IV detailed comparisons with recent topologies are tabulated with different criteria. The power loss is analyzed in Section V. Section VI portrays the result discussion. Finally, in the VII section conclusion portion is concluded. Fig. 2 depicts the 13-level multilevel structure with a switched capacitor. It comprises 13 switch counts, two diodes (D1 and D2), three capacitors (C1-C3), and four complementary switches (S1, S2, S5, and S9). Vab is the output of the inverter obtained from the source voltage Vdc.

FIGURE 2. Proposed 13 level MLIs diagram
This topology comprises three sections, left end is the source voltage along with thrice times of voltage boosting (S1, S2, S1', S2', C1, C2, and source voltage Vdc) is obtained from the voltage Tripler section.

B. OPERATING PRINCIPLE AND SC VOLTAGE BALANCING
For an inductive load, the current flow path is represented in Fig. 3 as per the switching Table I respectively. Every cycle of operations has completed the 17 operating states in the proposed topology. The entry "1" for ON state and "0" for OFF state is indicated in the switching table. In the voltage tripler section, the capacitors C1, C2 are coupled to the source voltage in parallel to charge each capacitor to the maximum rating of Vdc. These two capacitors discharged to the load along with the source voltage in a rating of 3Vdc. In this section, each capacitor can charge through the connection of source voltage parallel at the same time another capacitor can discharge to the load through the connection of series along with source Vdc. Particularly in the states of (a) & (d) from Vab=2Vdc:-During this state 2-3, by turning ON the switch as per Table I the 2Vdc is obtained in the load.
Vab=3Vdc: -During this state 4, the source voltage is coupled in series with storing devices such as capacitors C2 -C1 to charge the floating capacitor and supply the load voltage. So the capacitor C3 is in parallel with input voltage source Vdc when S3, S4, S6, S7 are ON so, the total amplitude of state 4 is 3Vdc generated.
Vab=4Vdc: -During this state 5, the capacitors C2 & C1 are joined with parallel, and capacitor C3 is in series with dc source when S3, S8, S9, S5, S7 are ON so, the received amplitude is 4Vdc on the load side.

C. MODULATION INDEX
In MLIs, the switches ON and OFF control is done by the PWM technique. For this purpose, a Phase Disposition (PD) 4 VOLUME XX, 2017  level-shifted multicarrier (PD-LS-PWM) PWM is recommended to improve the output voltage quality. In the PD, all carrier signals are in phase and the level is shifted. In the middle of the carrier signal, zero references are placed are shown as in Fig. 4. It is also suitable for lower switching frequency and higher switching frequency. Generally, for the several levels are higher, then the low switching frequency is recommended and for several levels is lower, the high switching frequency is recommended. In [8] is accepted for the modulation technique of the proposed 13 level MLIs inverter topology. Fig. 4 comprises a sinusoidal reference signal and the six triangular carriers (Vc1-Vc6) of the same frequency 2.5 kHz is compared with semi sinusoidal reference 50 Hz. The redundant states [20], is presenting a power-sharing is equally among the capacitor C1 and C2 in the symmetrical charging/discharging.

III. SHE-PWM MODULATION FOR THE PROPOSED INVERTER
The process of selective harmonics elimination plays a significant role to address lower total harmonics distortion (THD) in the voltage (Vab) waveform of the multilevel inverter. This inverter is designed to reject the harmonics For quarter-wave symmetry o a = 0 and n a = 0, the evenorder harmonics were canceled. Fourier series expression that to express the output phase voltage were given by, From the above Equation (2), the expressed term of instantaneous voltage (Vab) is as be expressed as the staircase output voltage is, On simplifying Where m is odd M= number of edges/ notches per quarter cycle In the proposed topology, the eliminating five categories of lower order harmonics in the waveforms by finding six firing angle S i.e., S-1 in the waveform of output voltage. For thirteen-level inverter topology, 3 rd , 5 th , 7 th , 9 th , 11 th harmonic order output voltage waveform has been picked for harmonic elimination. Equation (6) is used to find the firing angle 1  2  3  4  5  6 , , , , , cos(nθ ) -cos(nθ ) + cos(nθ ) -cos(nθ ) 4V V= n +cos(nθ ) -cos(nθ ) +...cos(nθ nπ ) In the output voltage waveform, 3 rd harmonics (n=3), 5 th harmonics (n=5), 7 th harmonics (n=7), and so on were eliminated.
4 cos(7 ) cos (7 ) ... cos(7 ) cos(7 ) 7 7 cos(9 ) cos(9 ) .... cos(9 ) cos(9 ) 9 9 cos (11 ) cos (11 ) .... cos (11 ) cos (11 )  11 11 To diminish the 3 rd ,5 th ,7 th ,9 th , and 11 th harmonics in outputs, the corresponding voltage has set to zero, and meanwhile (8) was employed to vary the modulation index from 0 to 1, to obtain the required angle through the inverter linear range while, As of now, the proposed work eliminates all the undesired low order harmonics from a fewer range of modulation index has been one of the significant contributions of SHEPWM. The main impartial is to become fundamental at the anticipated level for every modulation index. For a 13-level inverter, six optimized switching angles are 1 2 3 4 5 6 , , , , ,       calculated by using the above fitness function (9). A feasible modulation index with the least THD was computed by multiplying the error 1/e with its 1% of the limit. In the experimental setup, the variable modulation index was varied from 0 to 1 range with a step change of 0.01 along with the generated switching angle. The inertia weight has been varied from 0.9 to 0.4 ranges with an acceleration factor of 2. The variable of the objective function has been randomized. In a ring topology [25], the Pbest has been generalized by as much iteration by updating their velocity and angle.
The motive of the PSO algorithm is to guide the direction that paves the maximum utility. The best particle position is achieved by deploying an experiential learning model that learns from the utility gained by each particle due to its respective movement in search space. In every iteration, the particle velocity and dimension are getting updated by the following equations.

IV. COMPARISION WITH OTHER RECENT SCMLI TOPOLOGIES
The proposed cost-effective yet robust 13-level optimal MLIs was designed to generate a peak 13-level of AC output voltage efficiently. In Table II, recent topologies have been compared with the proposed model. In this proposed 13level SCIs, it is seen that the maximum voltage of all operating switches has not exceeded three times the maximum load voltage.
In [17], [18], the four-switch count on the HB and 2 switches count in [19] have to suffer from the peak load voltage. It requires two switches count series-coupled with half-rating [3Vin] for High-voltage applications. The proposed 13-level inverter topology is a symmetrical circuit comprised of a single DC source of Vdc= 60 V. For inverter configuration, the prime parameter is Total standing voltage (TSV). It is the summation of the absolute blocking voltage (maximum) across every switching device, while the same voltage stress occurs in the complementary switch count. The cost function of the 13S-13L inverter is compared to other 13 -Level MLIs, which are shown in Table III. The proposed 13S-13 level inverter topology is a symmetrical circuit comprised of a single DC source of Vdc= 60V. For inverter configuration, the prime parameter is TSV. It is the summation of the absolute voltage (MVB) across through every switching device, while the same voltage stress occurs in the complementary switch count. The Cost function of the 13S-13L inverter is compared to other 13 -Level MLIs, the voltage stress across the switches has been computed by [10], [19] - [23] Therefore, substitute (13)- (15) in (16) It is to be noted that the input voltage considered in the entire simulation and experimental hardware is 60 V and its corresponding recorded output is about 360 V. The capacitor C1 and C2 is 820 µF, which stores the energy of about 60 V whereas the capacitor C3 as 1200 µF that stores about 180 V are shown in Table IV. The simulation and hardware results are compared in terms of total harmonics distortion (THD) value of various modulation indexes are shown in Fig. 7    This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

V. ANALYSIS OF LOSSES
Generally, three losses are associated with the Multilevel Inverter i.e. a) conduction loss b) Switching loss c) Blocking loss is calculated based on [27]. Based upon the Table I the switches are triggered so each switch is changing from ON to OFF and OFF to ON. Minimum losses are occurred due to this operation. Based upon the various states as shown in Table I the switches are conducted by turning ON the position (0 to ±6Vdc). In the blocking mode, a minimum leakage current is generated and this quantity is very less because this loss occurred when switching components in OFF condition.
From the above definition, the efficiency of the inverter is only based upon the losses which are combined with conduction and switching losses. So the total losses are calculated as total switching conduction P = P + P (20) A. CONDUCTION LOSSES 13S-13L inverter topology S1-S9 & S1' -S9' are the unidirectional switches. Based upon the switching pattern with carrier signal frequency the instantaneous conduction losses have occurred, In the current path, the switches and diodes are in ON-state that period is used to determine the conduction losses by the fellow equation Z1(t) MOSFETs and the ON-State of the current path in antiparallel and diodes are forward-biased at any time is Z2(t), the fellow equation is used to find the conduction losses for the proposed topology.

B. SWITCHING LOSSES
Based upon the carrier frequency these losses are calculated with individual devices. After calculating the individual losses the total switching loss is determined by adding all switching components of the inverter topology.
The individual switch losses are calculated by applying a general approximation method.  After calculating the total losses of the inverter the efficiency is determined as follows, P out η= P + P out loss Compare to existing topologies minimum switch counts are used to design the proposed 13S-13L topology. So minimum losses have occurred. The energy stored in the capacitor is mainly due to the variation of the voltage drop, so a suitable selection of capacitor value is given in sec.5.c. The THD value for different 13-level inverters was discussed in Table VI for the modulation index of 0.9, [15] have the THD value of 19.56%, and [16] have the THD value of 17.34%, and remaining THD values were given in Table  VI.

C. SELECTION OF OPTIMAL CAPACITOR VALUE
The longest discharge time (LDT) for one full cycle of the fundamental output voltage, Vab is shown in Fig. 5, which is considered to find the switched capacitor's C1, C2, and C3 optimal value. The energy released by the switched capacitor C3 during LDT is computed by The output current (Iab) for R load in the LDT period can be given by The fundamental frequency scheme is employed to find the expressions for the time t6, t5, and t4, which are 1 Compared to [20] - [24], the 13S-13L inverter gives a low ripple value for capacitors C1, C2, and C3. The C1 and C2 have a ripple of 1.33% and C3 has ripple of 1.66% which is evaluated from simulation results shown in Fig. 8(c, d, e).

VI. RESULTS AND DISCUSSION
The simulation results are presented for 13S-13L inverter in Fig. 8. The Vab and Iab for RL load (R=50 Ω and L=60 mH) are 360 V and 5.6 A respectively as shown in Fig.  8a. For R load (R=50 Ω), the Iab is 6.9 A as shown in Fig.  8b. The simulated capacitor waveforms are shown in Fig.  8(c, d, e) for the modulation index of 0.95. For both RL load and R load, Vab and Iab for different modulation indexes are shown in Fig. 8f. THD without optimization for various modulation indexes is shown in Fig.9.
To demonstrate the significance and contribution in the proposed 13S-13L multilevel inverter, a less complex and efficient model has been built, studied, and evaluated. Discrete N-channel MOSFET 4* IRFP240PBF and 9* IXFH18N60X is used to design the proposed model that operates with an input voltage of 60 V. The PSO optimized selective harmonic elimination has been implemented by using an FPGA controller of SPARTAN 6E, where the carrier frequency is about 2.5 kHz and reference frequency or base frequency of 50 Hz.   For SHE, the generated six firing angles are given to microcontroller FPGA SPARTAN 6E to vary the angle of the carrier signal which results in low THD is given in Table V. After using the optimized angles, the THD has been reduced as shown in Fig. 10. The optimized switching angle versus modulation index plot is shown in Fig.11a and the plot for variation of harmonics versus modulation index is shown in Fig. 10b. The six-firing angle helps to minimize the THD significantly.    recorded while the voltage of capacitor C1 and C2 was 60 V and then C3 was 180 V respectively. The ripple voltage of capacitor Vc1, Vc2, and Vc3 are shown in Fig. 12f with modulation index 0.9. Initially, the Iab is 5.3 A for the R-L Load R=50 Ω and L=60 mH, after 0.04s resistance value is reduced to 30 Ω and the current is 7.7 A for the modulation index 0.9. Initially, the Iab clocks around 5.3 A for the RL Load R=50 Ω and L= 60 mH for about 0.04 sec, and thereafter the inductance is removed are shown in Fig. 12h. The experimental waveform is exhibited in Fig. 12 and the proposed topology was validated by the FPGA SPARTAN 6E controller. For the modulation index of 0.75 and Vab of 180 V results are shown in Fig. 13a and the voltage of the capacitor remains unchanged, so C1 and C2 is 60 V and the capacitor C3 is 180 V are shown in Fig. 13c. The load magnitudes like voltage and current waveforms and the capacitor voltage in the modulation index range of 0.9 and 0.75 are depicted in Fig. 12 and 13 respectively. The voltage stress of each switch is shown as in Fig. 14a of Switch S1, S1'and S2, S2' was 100 V, and their remaining switch S3-S9 is 300 V. Fig. 14b presents the current stress of switches S1, S1', S2, S2'are 2.8 A, S8 are 1.3 A and S3-S9 are 3.5 A. After finding the six-firing angle through the FPGA SPARTAN 6E controller and noting the THD value shown in Fig. 13 (h & i). As compared to another 13-level inverter [17], [20], [21], the proposed model has a better THD value as illustrated in Table VI. The TSV is clearly shown in Table II and also cost comparison with other recent 13-level inverter are discussed in Table III. Further, the switching losses and conduction losses for switches and diodes are explained in sec. V. A thermal model is built with the help of PLECS, and the simulated peak efficiency is 97.5% of the proposed topology at 2 kW. For the topology [20] is 95.9%, for the topology [21] is 96.7% and for the topology [22] is 95.5%. The proposed topology gives better efficiency than other recent 13-level inverters.

Conclusion
An efficient and novel sextuple voltage boosting 13level multilevel has been presented in this paper. The proposed topology has been designed as simplistic with a minimum of 13 switch counts, three capacitors, and two diodes with a single DC source. The SHE with PSO is employed to obtain six firing angles to minimize the lower order harmonics that cause lower THD value as the literature suggests. One of the prominent and key contributions of the model is the switched capacitor voltage could be effectively balanced by a simple series/parallel combination without any additional circuit/sensor. The Proposed 13-Level inverter has been well analyzed and studied with various multicarrier PWM and the optimal PWM was recommended in Table IV. Finally, the prominence of the proposed 13-level inverter was well established through the above-mentioned methods in terms of low THD.