Non-Isolated High Gain Quadratic Boost Converter Based on Inductor’s Asymmetric Input Voltage

This paper introduces the concept of inductors asymmetric input voltage to derive a new high voltage gain converter. The proposed converter has continuous input, positive output, and high-power density features suitable for renewable energy applications. The operating principle, steady-state performance, practical voltage gain, small-signal analysis, and efficiency of the converter are presented in this work. A comprehensive comparison is made with the high voltage gain converters available in literature in terms of component count, voltage gain, effectiveness index, voltage and current stress on the power devices, per unit switching device rating, and other features like output polarity and availability of common ground. The proposed topology possesses a higher effectiveness index and lower switching device power rating (SDP), resulting in a good form factor. To validate the performance of the proposed converter, the experiments are conducted on the 150 W laboratory prototype, and corresponding results are presented in this work.


I. INTRODUCTION
The drastic climatic changes, pollution, and depletion of fossil fuels motivated the world to work towards renewable power generation and electric vehicles. The recent developments in power electronic technology have enabled opportunities for renewable energy sources to penetrate into the modern grid and load systems, as shown in Figure 1. Power electronic technology makes the cost-effective power generation for future needs as well. Due to low voltage at renewable power sources, a high gain dc-dc converter with the continuous input is required to meet the requirement of the dc bus voltage and loads [1].
Among the primary dc-dc converters, boost and buck-boost converters have the capability to increase the voltage level. However, these converters do not give high output voltage in real-time due to the presence of parasitic elements and also have high electric stress on power semiconducting devices. To increase the voltage gain, transformer-based converters are used by adjusting the turn ratio and are widely reported in the literature [2]. But these converters have setbacks due to the cost and size of the transformer. Moreover, many applications do not need electrical isolation. The widely used method to enhance the voltage gain is voltage multiplier cell (VMC) based converters [3]- [8]. These converters make use of switched-capacitor (SC) and/or switched inductors (SL) cells; these VMC cells are applied to the conventional converters to increase the voltage gain. Despite their simple structure, a relatively low power density of the converter due to usage of more components, and instantaneous overcurrent phenomenon in SC-based converters are its setbacks. However, the over-current phenomenon in switched capacitor converters can be resolved at the cost of an additional small LC resonant circuit for energy transference. Similarly, the design and size of the SL-based converters have been significant limitations. Recently, the coupled-inductor-based converters for high voltage gain have been highly reported in the literature [9], [10], yet, they suffer from leakage inductance which causes voltage spikes at the power devices. Few attempts have been made to resolve the issue of voltage spikes by using the non-dissipative clamping circuits. However, power density has been the issue due to the additional circuits for coupleinductor-based converters.
To meet the high voltage gain requirement, quadratic converters have taken significant attention due to their practical feasibility. The quadratic converters can produce high voltage gain with a lower value of duty ratio. The family of quadratic converters is devised using the concept of component selection approach [11], reduced redundant power processing [12], flux-balance principle [13], X-Y type converters [14]. However, the voltage gain of these converters is limited, and few converters have the disadvantage of discontinuous input current, as continuous input is desired for renewable applications. In [15], a new quadratic buck-boost converter is proposed for a wide conversion ratio, but it has negative output polarity. Another quadratic buck-boost converter is proposed [16] for zero output ripple; however, this converter uses higher voltage rated capacitors and produces inverted output. A family of continuous input and continuous output enhanced gain buck-boost converters is proposed [17], but the converter has limited upper voltage gain; besides, the converters use more passive components. In [18], the high gain quadratic boost converter uses a higher component count. For increased voltage gain, a switched capacitor network is connected to the modified cascaded converter [19]. Although this converter provides the high voltage gain with continuous input, there is no common ground between input and output terminals and uses more components. A switched capacitor-inductor network-based dc-dc converter for high gain [20] uses a higher number of semiconducting power devices, and the controller design is complex as the converter order is very high. A new quadratic buck-boost converter is proposed to achieve the continuous input and high voltage gain [21]. Despite the wide conversion ratio, it has a drawback of inverted output. Recently, another quadratic buckboost converter [22] produced a very high voltage gain with continuous input but exhibited poor power density due to more passive components (4 inductors and five capacitors). Thus, the controller design is complex as the small-signal order of the converter is high. A new quadratic converter is introduced [23] for high gain by connecting switched capacitor cell to the single switch conventional quadratic boost converter. However, it produces high gain higher-order passive components (3 inductors and four capacitors) and lacks common ground between input and output ports.
Various attempts have been made to derive the new quadratic converters for high voltage gain. In [24], a singleswitch converter is proposed by cascading the modified quadratic boost, switched capacitor, and non-inverting cell. Although the converter has high voltage gain, the poor power density due to the higher number of circuit elements and lack of common ground has been its drawbacks. A new single-switch converter with switched-inductor-network is proposed [25] for high step-up gain. However, the converter has the drawback of limited upper gain, discontinuous input current, lack of common ground, and requirement of a higher-order control circuit. A modified Luo converter for the extendable gain converter is proposed [26]; despite the high voltage gain, the converter lacks common ground between input and output terminals. In addition, the controller design becomes complex with the presence of three inductors and five capacitors, respectively. Recently, an active switchedinductor network-based high gain quadratic boost converter is proposed [27] with a high voltage conversion ratio, continuous input, positive output. However, it requires three active switches, and there is no common ground between input and output terminals.
In addressing the above shortcomings, in this work, the concept of asymmetric input voltage to the inductor is introduced and applied for the first time to improve the converter's gain. In general, to get quadratic boost gain, two conventional boost converters will be connected in cascaded nature, where one converter output is fed to another converter, as shown in Figure 2(a). Here, the load side cascaded converter's inductor experiences V C1 and V C1 -V O during ON and OFF states, respectively. In the proposed converter, the circuit is configured to enable inductors to experience 2V C1 and V C1 -V O during ON and OFF states to improve the voltage gain using the capacitor-diode cell, as shown in Figure 2(b). The converter derived has the gain of (1+D)/(1-D) 2 with minimum components, which is better than the existing topologies. Further, the converter has a low switching device power rating (SDP), continuous input current, positive output voltage, and higher power density. These features are much suitable for applications like renewable power generation, electric vehicles, and avionics.

II. ANALYSIS ON CONVERTERS GAIN FOR INDUCTORS ASYMMETRIC INPUT VOLTAGE
Considering the conventional quadratic boost converter, the output of the primary converter is fed to the secondary converter, as shown in Figure 2(a). The output of the primary boost converter is V C1 , which is equal to 1/(1-D) times of input voltage, V in . The voltage across the inductor L 2 of the secondary boost converter during its ON-state and OFF-state is V C1 and V C1 -V O , respectively. The output of the secondary boost converter is equal to 1/(1-D) times of V C1, and hence, the total gain of the converter is 1/(1-D) 2 times of input voltage, V in . In this work, an attempt is made to study the impact of diverse input voltage in the ON and OFF states of secondary converter on voltage gain.
The diverse input voltage in the ON and OFF state of the secondary converter can be achieved using an additional capacitor, C 2, and diode, D 2, as shown in Figure 2 Here, the configuration enables the capacitor C 2 to maintain the voltage same as capacitor C 2, i.e., V C2 = V C1 . Further, if the converter configuration supports the capacitor in aiding the input voltage to V C1 +V C2 (=2V C1 ) across the secondary inductor L 2 of the converter during the ON state. The voltsecond balance equation and the secondary converter voltage gain is given below: Similarly, if the configuration is modified such that the capacitor C 2 aids the input voltage to V C1 +V C2 (= 2V C1 ), the total voltage across the secondary inductor L 2 of the converter during the OFF state becomes 2V C1 -V O . The volt-second balance equation and the secondary converter voltage gain are as follows.
The secondary converter gain of the conventional and gains derived in (1) and (2) at different duty ratios are shown in Figure 3. From the figure, the gain derived using capacitor-diode cell in aiding the input voltage during ON-state yields wide voltage gain as compared to the other cases. In this work, the above concept is adopted to derive a new high gain quadratic boost converter.

III. PROPOSED CONVERTER
The proposed converter shown in Figure 4 is derived utilizing diverse input voltage in the ON and OFF states of the secondary converter by integrating the diode-capacitor cell to the conventional quadratic converter. The proposed converter consists of two synchronously operated active power semiconducting switches (S 1 and S 2 ), three diodes (D 1 , D 2 , and D 0 ), two inductors (L 1 and L 2 ), three capacitors (C 1 , C 2 , and C 0 ), and finally, the load resistance (R). This topology supports capacitor C 2 in aiding the input voltage to 2V C1 across the secondary inductor L 2 of the converter during the ON state.

A. OPERATION OF PROPOSED CONVERTER IN CCM
The assumptions for circuit operation are, all the components used in the circuit are ideal, the capacitors are large enough to maintain output voltage constant, and the converter is operating in continuous conduction mode (CCM). The proposed converter has two modes of operation. The power flow in Mode-I and Mode-II of the proposed converter is represented with red lines, as shown in Figure 5.
In mode-I (0 < t < DT), the two active switches will be turned on simultaneously, and the three diodes will be reversed biased. In mode-I (0 < t < DT), the two active switches will be turned on simultaneously, and the three diodes will be reversed biased. In this mode, inductor L 1 will be energized with the help of the input voltage source; and the inductor L 2 will get energized with the total voltage supplied by the capacitor C 1 and additional capacitor C 2 . The output capacitor is large enough to support the load current during this mode, and the corresponding power flow is shown in Figure 5(a). The dynamic equations of the proposed converter during mode-I are given below.
In mode-II (D < t <T), the two active switches will be turned off, and the three diodes will be in conduction as they are forward-biased. The inductors will be demagnetized, and capacitors will get charged in this mode, and the corresponding power flow is shown in Figure 5(b). The dynamic equations of the proposed. The dynamic equations of mode-II operation are given below The time-domain steady-state waveforms of the proposed high gain quadratic boost converter when it is operating CCM are shown in Figure 6.

IV. STEADY-STATE ANALYSIS IN CCM
This section gives the steady-state analysis of the proposed converter operating in CCM. In general, steady-state analysis refers to the derivation of the voltage gain of the converter, computation of electric stress experienced by the power devices, designing of passive components, computation of practical voltage gain, and efficiency calculations. A detailed explanation of each of the above-mentioned analysis is presented below.

A. VOLTAGE CONVERSION RATIO
From Figure 5, the voltage gain of a dc-dc converter can be derived using the volt-second balance equations of the inductors L 1 and L 2, and are given below: By solving the above equations, the steady-state voltage expression of capacitors is given below.
The equations (5), (6) help to derive the voltage conversion ratio of a proposed high voltage gain boost converter and is given below.
Similarly, the current gain of a converter can be derived by using the ampere-second balance principle of a capacitor. From (3) and (4), the expressions for average inductor current and current gain are given below.
The above derived steady-state expressions will be further helpful to analyze the electric stress on power devices, design of circuit parameters, and efficiency calculations.

B. ELECTRIC STRESSES ON POWER DEVICES
The electric stress of a converter can be defined as the voltage and current stress experienced by a power semiconducting device over a switching time. It is one of the performance indices of a dc-dc converter, which is used to analyze the efficiency and reliability of a converter.
The voltage stress experienced by semiconducting power devices can be defined as the blocking voltage capability of the power device when it is in OFF state. The expressions of voltage stress of each power device can be derived from the steady-state waveforms and aforementioned steady-state equations (6)- (8), and are given below.
Similarly, the current capability of the power device during its conduction state is called as current stress, and can be derived as follows.
The expressions for RMS current flowing through the circuit components given in equation (11) are necessary to determine the power losses of a particular component.

C. DESIGN OF PASSIVE COMPONENTS
A dc-dc converter's design process starts with defining the expression of a duty cycle in terms of voltage gain. By using equation (7), the duty cycle of two active power switches, S 1 and S 2, is defined as To validate the performance of the proposed converter in continuous conduction mode, proper designing of the passive components is desired. In general, the inductors (L 1 , L 2 ) and capacitors (C 1 , C 2 , and C 0 ) values can be expressed using dynamic equations (3) and (4) and are shown below.
By using the above equation (13), the value of inductors and capacitors is selected based on the given ripple specifications and the power rating of the converter.

D. EFFECT OF NON-IDEALITIES ON VOLTAGE GAIN
Practically, all the power electronic devices and passive components consist of some non-idealities. These non-idealities influence the performance of a converter, especially in the case of voltage gain and efficiency of the converter. The equivalent circuit of the proposed converter, including all the non-idealities shown in Figure 7, is used to analyze the practical gain and efficiency. In this figure, R S1 , R S2 are switch ON-state resistances, R D1 , R D2 , R D0 are the forward diode resistances, V D1 , V D2 , and V D0 are the forward diode voltages. R L1 , R L2 is the equivalent series resistance of inductors, and R C1 , R C2 , and R C0 are the equivalent series resistance of capacitors.
The effect of non-idealities on the voltage gain can be derived by applying the volt-second balance principle to the converter shown in Figure 7. The dynamic model equations during the two active switches are at ON state. The dynamic model equations of the converter are given below when the switches are OFF and diodes are at ON state.
By applying the volt-second balance principle to the inductors, the practical voltage gain of the proposed converter can be derived and is given below: Among all the non-idealities, the equivalent series resistance of the inductor will significantly affect the ideal voltage gain, shown in Figure 8. From the figure, it is clear that the per-unit ESR of the inductor has to be less to achieve the higher voltage gain.

E. POWER LOSSES CALCULATION AND EFFICIENCY
The non-idealities of circuit components cause the power losses in the converter. The computation of the power losses is necessary to verify the performance of the converter in real-time applications. To simplify the analysis, the inductor current ripple and capacitor voltage ripple are neglected. The power losses of the dc-dc converter comprise the losses due to switches, diodes, inductors, and capacitors.
The power losses in the switches are due to conduction and switching losses. The on-state resistance of a switch is responsible for conduction losses, and the turn-on and turnoff times are responsible for switching losses in a power VOLUME 9, 2021 switch. The total power switch losses are obtained as The power losses of two switches S 1 and S 2 expressed in terms of output power as In the diode, the forward resistance and forward voltage drop are the reasons for the power losses and can be obtained as The power losses of three diodes D 1 , D 2, and D 0, can be written in terms of output power as follows The equivalent series resistance of passive components (inductors and capacitors) is responsible for power losses, as given in equation (21).
The power losses in the inductors and capacitors are expressed in terms of output power as follows The total power losses of the proposed converter can be summarized as P total = P S1 + P S2 + P D1 + P D2 + P D0 +P L1 + P L2 + P C1 + P C2 + P C0 (23) The efficiency of the proposed converter can be derived with the help of output power and total power losses, as given below The output power is calculated using the practical voltage gain, and then the total losses are computed using equation (23). The theoretical efficiency of the proposed converter when it is operated at different duty ratios and load resistance is shown in Figure 9. The parameters considered for the efficiency analysis are V in = 12 V, L 1 = 0.5 mH, L 2 = 1 mH, C 1 = C 2 = 25µF, and C 0 = 20µF. It is clear from the figure that the proposed converter has promised good efficiency over the range of wide duty ratio and load resistance.

V. DISCONTINUOUS CONDUCTION MODE
The discontinuous mode operation of the proposed converter is considered when one of the inductor currents is reached to zero value. In this section, boundary condition mode and boundary condition between CCM and DCM are also explained.

A. OPERATION OF PROPOSED CONVERTER IN DCM
The DCM of the proposed converter has three modes of operation, and corresponding time-domain waveforms are shown in Figure 10.
In mode-I (0 < t < DT s ), the two active switches are turned ON. The DCM operation is the same as CCM in this mode, and the equivalent circuit is shown in Figure 5(a). The inductor L 1 is magnetized with the input voltage source, whereas inductor L 2 is magnetized with the total voltage of capacitor C 1 and additional capacitor C 2 . The currents of both inductors rise from minimum (zero) to maximum (I Lp ) value. The peak values of inductor currents are expressed as In mode-II (DT s < t < D 1 T s ), the two active switches are turned OFF, and three diodes are forward biased as similar mode-II in CCM. In this mode, the inductor current reaches its zero value in the D 1 T s interval, as shown in Figure 10. The peak current of the inductor can be expressed in terms of D 1 as In mode-III (D 1 T s < t < T s ), the inductor currents will be zero, and all the power devices will be at an OFF state.  The output capacitor feeds the load current; the equivalent circuit of the proposed converter in this mode is shown in Figure 11. By using the equations (25) and (26), the D 1 can be represented as The average output capacitor current, I C0 , value can be expressed as Substitute the equations (26) and (27) in (28), then, I C0 can be expressed as The voltage gain of the proposed converter in DCM, M DCM can be derived by further simplification of equation (29), given below.
where τ L2 is the inductor L 2 time constant, it is equal to L 2 f s 2R .

B. BOUNDARY CONDITION BETWEEN CCM AND DCM
Defining the boundary conditions is necessary to understand the operating mode of a converter. Generally, the boundary condition of a converter is defined as where the peak inductor current ripple ( i L ) equals twice the inductor average current (I L ). The normalized inductor time constants can be defined as From equation (8), the boundary conditions of the two inductors L 1 and L 2 of the proposed converter can be expressed as Using the above equation, the relationship between the inductor time constant and the duty ratio is plotted in Figure 12.

VI. SMALL-SIGNAL ANALYSIS
This section analyzes the low-frequency behavior and smallsignal dynamics of the proposed quadratic boost converter with the help of a state-space averaging-based small-signal model. The inductor currents and capacitor voltages are considered as the state variables of the system. From the previous steady-state analysis, the capacitor C 2 is analogous to C 1 as they experience the same operating voltage and current at any time. Therefore, the system is reduced into the fourth order from the fifth order [21]. Applying the state-space averaging to the dynamic equations (2) and (3) is given below. C0 and v in designate the averaged values of the i L1 ,i L2 ,v C1 ,v C2 ,v C0 , and v in , respectively, and d indicates the duty cycle. Here, the uppercase letters of these voltages and current reference to the steady-state value of the parameter. To linearize the system, the slight deviation (denoted with cap) in these parameters is considered. However, the deviation is negligible as compared to its average value, as mentioned below. Assuming that product of two small signal variables and average steady-state variables are equals to zero. Substitute the equation (34) in (33), then a small signal model of the proposed converter can be attained, shown in Figure 13. By taking Laplace transformation to a small-signal model, the transfer functions of input-to-output and control-to-output are given below.
By using the above equations, the small-signal dynamic behavior of the proposed converter can be analyzed. It is clear from equation (35) that the proposed converter has three right-hand side zeros, making the proposed converter a non-minimum phase system. However, the system poles are located at the left side of the s-plane, which means the proposed converter is stable. The frequency response of the proposed converter is analyzed with the help of a bode plot of derived transfer functions, as shown in Figure 14.

VII. COMPARATIVE ANALYSIS
This section compares the proposed quadratic boost converter with other high voltage gain converters available in the literature. The comparison is in terms of the voltage gain, steadystate electric stresses on circuit components, switching device power rating, and other features. Figure 15 shows the comparison of proposed converter voltage gain with a quadratic buck-boost converter [16], the enhanced gain buck-boost converter [17], a new quadratic following boost converter [18], a negative output buck-boost converter [15], a continuous input quadratic buck-boost converter [21], and a switched capacitor-inductor network-based boost converter [20], a high gain quadratic buck-boost converter [22], a switched capacitor cell extended modified cascaded converter [19], and single-switch high gain quadratic   boost converter [23]. Figure 15 shows that the proposed converter has a higher voltage gain than other converters except for the converter in [22]. Although the converter in [22] has better voltage gain, it uses a higher number (fourteen) circuit components. The effectiveness index (EI) is another performance indices that is measured by taking the ratio of voltage gain and the total number of components used in the converter and is used to evaluate the power density of the power electronic converter [22]. From Table 1, the EI is calculated at different duty ratios for all the high gain converters and is depicted in Figure 16. From the figure, the proposed converter has the highest effectiveness index compared to the remaining converters due to the capability to produce the highest voltage gain with the lower number of circuit components.   The detailed steady-state performance comparison is given in Table 1. To improve the efficiency and reliability of the converter, the electric stresses on the power devices have to be a minimum. Understandably, the voltage stress across the output switch S 2 and diode D 0 of the proposed converter is high due to its high voltage output with a lower number of components Figure 17 shows the comparison of the total voltage stress across the power devices versus voltage gain. Despite high voltage gain, the proposed converter has less voltage stress on power semiconducting devices than converters in [16], [17], and [21]. However, the total voltage stress (TVS) of the proposed converter is less for the given voltage gain as compared to the other converters given in Table 1 and therefore results in good form factor with high power density. The total switching device power rating (SDP) is another important performance metric in the power electronic converter [28]. To quantify the cost of the system in terms of electric stress on power devices, the following expression is used.
V si and I si are the voltage and current stress of the power device, respectively, and 'n' is the total number of power devices present in the converter. The SDP of the proposed converter and other high gain converters can be calculated with the help of Table 1.
The per-unit SDP comparison of the proposed converter and other converters is plotted and shown in Figure 18. The figure shows that the per-unit SDP is lower than a few other converters despite its high voltage gain capability. In addition, the proposed converter gives the positive polarity output along with continuous input current and is very much essential for renewable energy and electric vehicle applications.

VIII. EXPERIMENTAL VERIFICATION
To validate the performance of the proposed high gain quadratic boost converter, experiments are conducted on the 150 W laboratory prototype, which is shown in Figure 19. The schematic of the hardware implementation of the control circuit of the proposed converter is given in Figure 20. The PWM pulses for two synchronously operated active switches are generated with the SPARTAN 6 FPGA controller. The HCPL 3120 optocoupler-based driver circuit is used to drive the switches and to isolate the control circuit from the power circuit. The corresponding experimental specifications are given in Table 2. Figure 21 shows the experimental waveforms of the proposed high gain quadratic boost converter considering the load resistance of 100 . Figure 21(a) shows the input voltage, capacitor C1, output, and input inductor L1 current. The input voltage of 12 V is applied to the converter and is operated at the 0.5 duty ratio. As per equations (5) and (6), the capacitor C 1 voltage, the output voltages are 24 and 72 V, respectively. From Figure 21(a), the experimental values are 23 and 69 V, respectively. The deviation between the theoretical and experimental values could be due to the non-consideration of contact and soldering resistance. Figure 21(b) shows the capacitor C 2 voltage, and the diode D 2 voltages. The voltage across capacitors C 1 and C 2 are equal. The measured S 1 , D 1 voltages, and S 2 , D 2 voltages are shown in Figure 21(c) and Figure 21(d), respectively. From the figure, the measured values are in agreement with the theoretical findings. The inductors currents are depicted in Figure 21(a) and Figure 21(d); it is clear that measured inductors (L 1 and L 2 ) current and its ripple are in the specified design limits.
Further, the dynamic response of the proposed converter for the change in input voltage, duty ratio, and load is shown in Figure 22. In this figure, initially, the converter is operated at 10 V of input voltage, 0.4 duty ratio, the load resistance of 100 , and corresponding output voltage and current are 60 V and 0.6 A, respectively. Then, the input is changed from 10 V to 12 V at 1.5 seconds. At this point, the output voltage is changed from 60 V to 70 V, and the load current is changed from 0.6 A to 0.7 A. Then, the duty ratio is changed to 0.5 from 0.4 at 3 seconds, and the input voltage is kept constant at 12 V; then, the output voltage is changed to 46 V from 70 V, and the load current has changed to 0.46 A from 0.7 A. Further, the load resistance has changed from 100 to 75  The experiments were performed to obtain the practical voltage gain at different duty ratios and are compared with   ideal and non-ideal theoretical voltage gain calculated using equations (6) and (16), respectively. The voltage gain comparison is given in Figure 23; the practical voltage gain is very close to the non-ideal theoretical voltage gain and validates the superiority of increased input voltage contribution across the inductor even asymmetrically.
The experimental efficiency of the proposed high gain quadratic boost converter is measured. The converter operates at different power ratings by varying the duty ratio for fixed load resistance shown in Figure 24. The figure shows that the proposed converter efficiency is poor at lower duty cycles and is maximum at 0.5 duty ratio. Beyond the 0.5 duty ratio, an increase in duty cycle leads to a decrease in efficiency due to the higher value of load currents. The breakdown of power losses in the circuit components of the proposed converter is shown in Figure 25. The efficiency and power losses are measured when the proposed converter is operated at 12 V input voltage, 0.5 duty ratio, and load the resistance of 100 . The figure shows that the diodes contribute significantly to losses compared to other components and proposed converter promising efficiency.

IX. CONCLUSION
This paper illustrates the advantage of utilizing inductors' asymmetric input voltage for the first time, and the concept is adopted for developing a new high gain quadratic boost converter. The steady-state and small-signal analysis of proposed converter exhibits the features of reduced electric stress and good dynamic response, respectively. A comprehensive comparison of the proposed converter has shown promising superiority in terms of voltage gain, effectiveness index, the total voltage stress on power devices, per-unit SDP. In addition, the proposed converter has continuous input, provides the positive output and common ground; therefore, the converter is well suited for renewable energy generation, electric vehicles, avionics, and dc microgrid applications. Moreover, the proposed methodology can be further investigated to derive new high gain dc-dc converters.