Novel Multiple-layer Stack Capacitor and its application in the IRPFA Readout Circuit

In this paper, a kind of four-layer stack capacitor is proposed, which has realized the compatibility with the conventional standard 0.5μm CMOS technology. The effective capacitance per area of the proposed stack capacitor is about three times larger than that of the mono-layer MOS capacitor. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the presented four-layer stack capacitor has been also established with considering the fringe effect. The results show that the root mean square error of the proposed SPICE model is less than 2%. The model has been applied in the simulation design of the infrared focal plane array readout circuit (IRFPA ROIC) successfully. Based on the improved 0.5μm CMOS process with four-layer stack capacitor, an IRFPA ROIC with 640×512 array has been implemented and the dynamic range is improved from 73db to 78dB.


I. INTRODUCTION
Infrared focal plane arrays have a wide range of industrial, medical, and scientific applications. The infrared focal plane array readout circuit (IRFPA ROIC) [1][2][3], as the critical part of the dynamic range, can deal with the weak electrical signal sensed by the detector. Generally, the infrared detector can generate numerous carriers once it receives the photons, the generated carriers will be saved into the integrating capacitor and then transformed into the output voltage signal by the ROIC. Dynamic range is an important parameter in image sensors, and the large dynamic range requirement is the most challenging aspect in modern CMOS process [4]. Generally, methods of extending dynamic range can be divided into three categories. One uses logarithmic pixels response to extend dynamic range as in [5], one group accepts multiple exposure-times to expand the dynamic range as in [6], and the other one applies lateral overflow capacitors to improve operation range [4,[7][8]. From aspect of device design, enhancing the capacitance of integrating capacitor is the most direct way. In addition, the ROIC's uses a capacitor along with active elements for signal integration and processing, the amount of charge collected is defined by the charge handling capacity and limited by the size of integrating capacitor. Capacitance with smaller size can reduce the overall chip area and promote the development of product miniaturization. Meanwhile, larger capacitance values can store more charge and electrical information in IRFPA ROIC, which provides more pixel information on image processing. In CMOS technology, improving the capacitance value per unit area by means of optimizing device structure design is a research of great engineering value. Therefore, enhancing the capacitance of integrating capacitor at the limited pixel cell area is the most effective way to improve the performance of the dynamic range.
In this paper, a kind of stack capacitor is proposed, which has realized the compatibility with the conventional standard 0.5um CMOS technology process. Compared with mono-layer MOS capacitor [9][10], it can largely enhance the capacity of integrating capacitor at the limited pixel cell area. Obviously, this four-layer stack capacitor is more competitive to balance the relationship between the capacitance of integrating capacitor and the occupying space.
Moreover, it is noted that the Simulation Program with Integrated Circuit Emphasis (SPICE) model is the link between the physical world and the design world of the semiconductor industry. But until now, no any SPICE model is established to describe the electrical characteristics of the stack capacitor. In this paper, the SPICE model of the four-layer stack capacitor has been established, the considerable accuracy and general applicability of the proposed SPICE model have guaranteed the successful simulation design of the IRFPA ROIC. Finally, based on the improved 0.5μm CMOS process, a kind of IRFPA ROIC with 640×512 array has been implemented, and the test results show that the enhanced capacity of the integrating capacitor has improved the performance of the dynamic range effectively.

A. THE STRUCTURE OF CAPACITOR
The conventional 0.5μm CMOS technology platform [11] owns a full suite of devices, including industry compatible 5V CMOS, free bipolar, precision resistors and capacitors. Based on the 0.5μm CMOS technology platform, we have implemented a kind of four-layer stack capacitor by only adding two MCT layers, as shown in Fig.1. The schematic cross section of the presented four-layer stack capacitor has been shown in Fig.2. It is noted that MOS capacitor is formed by an NMOS device, Poly-Insulator-Poly (PIP) capacitor is fabricated between two poly layers, MIM (Metal-Insulator-Metal) cap.1 is between Aluminum layer 2 (A2) and Aluminum layer 3 (A3), MIM cap.2 is between Aluminum layer 3 and Aluminum layer 4 (A4). All of them are connected in parallel.  As shown in Fig.3, when the MOS capacitor part of fourlayer stack capacitor is under accumulation region, the total capacitance of stack capacitor is 7.6pF, which is larger than that under-inversion region (5.5pF). This is because, the MOS capacitor under accumulation region mainly contains the gate oxide layer capacitor, while the MOS capacitor under inversion region is formed by the gate oxide layer capacitor and semiconductor layer capacitor in series. Therefore, in the practical application, the stack capacitor is normally set on the state that its own MOS capacitor works in accumulation region, so as to acquire more larger capacitance value. GT   In addition, other measurement results can be also shown in Fig.3. For modeling and comparison, capacitors with the same size of 30μm×30μm area were designed. In the same area, the four-layer stack capacitor is 7.6pF, while only 2.5pF for mono-layer MOS capacitor, 2.1pF for mono-layer PIP capacitor and 1.8pF for mono-layer MIM capacitor. The effective capacity of the stack capacitor is more than 3 times larger than that of any other mono-layer capacitor. This can prove that the stack capacitor owns larger capacitance in less occupying space, which verifies great advantage in the charge storage capability and the occupying space comparing with the mono-layer MOS capacitor, MIM capacitor and PIP capacitor.

B. THE SPICE MODEL OF MOS CAPACITOR
The idea of the four-layer stack capacitor SPICE model has been shown in Fig.4. The SPICE models for the MOS capacitor, PIP capacitor and MIM capacitors will be established respectively.
In this paper, the charge-thickness model (CTM) [12][13], as a classical charge-based model, has been established to describe the characteristics of MOS capacitor, as shown in Fig.5.
The MOS capacitor has been regarded as C ox and C cen in series, which can be expressed by where C ox is unit-area capacitance of gate-oxide capacitor, C cen is unit-area capacitance of charge-thickness capacitor. Respectively, C ox and C cen can be expressed by where ε ox is permittivity of gate oxide and ε Si is permittivity of silicon, T ox is the gate-oxide thickness and X DC is the DC charge thickness. It is observed that C ox and ε Si are both constant, and we just analyze the only variable of them, X DC . Based on numerical self-consistent solution of Schrodinger, Poisson and Fermi-Dirac equations, the universal and analytical X DC model has been discussed.  The DC charge thickness in the accumulation and depletion regions can be expressed by where X DC is in the unit of cm, (V gb -V fb ) / T ox has a unit of MV/cm, acde is exponential coefficient for the charge thickness in accumulation and depletion regions, N sub is the channel doping concentration, and V fb is the flat-band voltage.
Respectively, the Debye length L debye and the flat-band voltage V fb can be expressed by where v τ0 is the thermal voltage at test temperature, K 1ox is the first-order parameter for the body effect coefficient, φ s is surface potential, V bseff is the effective body bias. But for numerical stability, Equation (4) is replaced by Equation (7) = − 1 2 ( 0 + √ 0 2 + 4 ) where 0 = − − (8) and The inversion charge layer thickness can be formulated as where V gsteff is effective gate voltage, V th is the threshold voltage, and φ B is the effective interface contact potential.

C. THE SPICE MODELS OF MIM CAPACITOR AND PIP CAPACITOR
Both MIM capacitor and PIP capacitor are parallel-plate capacitors. Thus, we can establish one kind of model for both.
The surface field lines those are in the interior of parallelplate capacitor are uniformly distributed, which are shown as the solid lines in Fig.6. Thus, we can express the unit-area capacitance for this part by VOLUME XX, 2017 9 = 4 (11) where ε r is the dielectric constant of the parallel-plate capacitor, k is the electrostatic constant and d is the distance between the two electrodes. However, when the distance d is small, the shapes of electric field lines in peripheral parts vary from parallel to outward arc [14][15], as shown in Fig.6. Therefore, the fringe effect will not be negligible and the traditional result (Eq. (11)) is not applicable for the peripheral capacitor. Equation (12) is the expression for the peripheral capacitor and Equation (13) is the expression for v fac in Equation (12). = * * (12) = 1 + 1 * 1−2 + 2 * 1−2 2 (13) where C edg is the unit-length capacitance of the peripheral capacitor, P ER is the perimeter of the parallel-plate capacitor, v fac is the voltage impact factor for fringe effect, p vc1 is the first-order voltage fitting parameter, p vc2 is the second-order voltage fitting parameter and V 1-2 is the effective voltage between the two electrodes.
The temperature parameter of the parallel-plate capacitor can be expressed by = − 25 (14) = 1 + 1 * + 2 * 2 (15) where t emp is test temperature and in the unit of ℃, d temp is the temperature difference between test temperature and room temperature and in the unit of ℃, p tc1 is the first-order temperature parameter, p tc2 is the second-order temperature parameter, t fac is the temperature impact factor for the parallel-plate capacitor.
In conclusion, the formula model of the parallel-plate capacitor including fringe effect and temperature impact factor can be expressed by: where C 0 is the capacitance for the interior part of the capacitor, Area is the area of the parallel-plate capacitor, C 1 is the capacitance for the peripheral part of capacitor and C MET is the total capacitance of the parallel-plate capacitor.

D. THE VERIFICATION OF SPICE MODELS
Three completely different stack capacitors have been selected to verify the accuracy and applicability of stack capacitor SPICE model. The structure parameters of the three stack capacitors can been seen in Table1.  In order to evaluate the accuracy of the proposed model, the root mean square (RMS) is calculated by: where the mea i is the measured data per point, the sim i is the model prediction data per point, and the N is the total numbers of all points. As shown in Fig.7, the RMS values of the three capacitors are 0.93%, 1.53%, and 1.37% respectively, so we can confirm the RMS based on the proposed stack capacitor model are all less than 2%, which confirm the considerable accuracy and general applicability of the stack capacitor SPICE model.

A. THE STRUCTURE OF INFRARED READOUT CIRCUIT
In this section, a high performance, 640×512 pixels, readout integrated circuit (ROIC) with snapshot mode integration is proposed and described. Typically, the ROIC consists of charge integration, charge to voltage conversion, pixel voltage multiplexing, signal transfer and amplification stage [16][17][18]. In our work, the block diagram of the readout structure consists of the block diagram of the readout structure plotted in Fig.8 including logic circuit, row select circuit, column select circuit, pixel unit array, column path, output buffer, and all parts are marked in Fig.8.
Pixel cell design is one of the most important designs of ROIC. In this paper, proposed novel multiple-layer stack capacitors are used in pixel unit and the pixel unit uses direct injection (D I ) structure. The D I structure has the characteristics of small occupied area, simple circuit structure and containing large integral capacitance. When the ROIC operates in the I WR readout mode, whenever the frame signal arrives, the pixel unit will sample the voltage from the C int to the C sh , then the C int will be reset and integrating next frame signal. However, when the ROIC operates in the I TR readout mode, sampling tube is in constant Open state so that C int and C sh will be integrated together. As a result, the integral capacitor becomes larger in this mode so that greater charge handling ability can be obtained. Fig.9 shows the block diagram of pixel unit circuit. The dynamic range can be defined as the ratio of the maximum unsaturated input signal (i max ) to the minimum measurable input signal (i min ), the minimum measurable input signal is usually defined as the noise equivalent current without illumination. It is shown in Formula (19), id represents the sum of dark current and background current. Q noise is the sum of equivalent noise charges of IRFPA, and Q max is the maximum charge storage capacity.
Therefore, when the structure of the detector and pixel unit is relatively fixed, increasing the charge storage capacity of the integral capacitor is the most effective solution to increase the dynamic range. Increasing the charge storage capacity means increasing the integral capacitance. So in this design, we use the multiple-layer stacked capacitor as the integral capacitance of the pixel unit. Fig.10 shows the layout of pixel cells. Since there are only 6 layers of metal, the 4 and 5 layers of metal need to be used as control signal wiring, and the top layer of metal is used to connect the detector interface. Therefore, only one MIM capacitor is stacked on the integral capacitor. The integral capacitance of this design is about 0.9pf (C in + C sh ). Fig.11 shows the simplified architecture of the column path [19][20]. The column path starts with source follower, composed of charge amplifier, a sample-and-hold circuit, column buffer and output buffer. Row and column address are controlled by the row select circuit and column select circuit. Whenever all the pixels of the row have been readout, the column path will be reset.  Fig.13 shows the waveform of the full window and four output at the clock frequency of 5MHz. As showed by Fig.14, the output reference voltage is 1.6V, the maximum output voltage is 4.8V. The output noise is about 400uV, thus the dynamic range is 78dB. This ROIC is fabricated using CSMC 0.5um double poly, six metal process that utilized high-speed CMOS transistors and the whole chip area is 17.5×16.5mm 2 . Fig.15 shows the sample of the chip and the imaging results of readout circuit with detector.  Table II shows the main performance parameter of the ROIC. Compared with the reported work [21] and the previous design using mono-layer MOS capacitor. The dynamic range is increased from 73db to 78dB by using multiple-layer stacked capacitor as integral capacitor.

V. CONCLUSION
In this paper, a kind of four-layer stack capacitor is proposed, which has realized the compatibility with the conventional standard 0.5μm CMOS technology. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the presented four-layer stack capacitor has been also established with considering the fringe effect. The results show that the root mean square error of the proposed SPICE model is less than 2%. The model has been applied in the simulation design of the infrared focal plane array readout circuit (IRFPA ROIC) successfully. Based on the improved 0.5μm CMOS process with four-layer stack capacitor, an IRFPA ROIC with 640×512 array has been implemented. Compared with the previous chip, the dynamic range is improved from 73dB to 78dB. At the same time, the chip and detector are packaged together, and the infrared imaging is successful.