Research on Synchronous Rectification Driver Technology of High-Frequency DC-DC Resonant Converter Based on GaN Devices

With the increase of switching frequency to tens of MHz, the synchronous rectification faces many new challenges, among which a significant one is the design of the driver circuit for the synchronous rectification with wide bandgap gallium nitride (GaN) devices. According to the self-resonant driving theory, this paper proposes an in-phase feedback synchronous rectification driver circuit (SRDC) based on GaN devices and the driver chip. In this SRDC, the nonlinear parasitic capacitors are replaced with external capacitors, and the synchronous driving signal is in-phase with the excitation source. The new scheme can provide precise driving timing, stable driving amplitude and flexible phase-shifting characteristics for the synchronous rectification of a high-frequency DC-DC resonant converter (HFDRC) based on GaN devices. In this paper, a detailed parameter design method is introduced by analyzing the characteristics of the feedback network. The feasibility and effectiveness of the proposed SRDC are verified on a 20 MHz prototype with 18 V input and 5 V / 2 A output.


I. INTRODUCTION
Increasing switching frequency of converters can significantly reduce the volume and weight of passive components, increase the power density and the dynamic response [1]- [4]. Recently, the application of wide bandgap devices [5], [6] has enabled the operating frequency of DC-DC power converters to tens of MHz. Among them, the high-frequency DC-DC resonant converter (HFDRC) has received much attention.
The HFDRC generally includes three parts: the inverter, the matching link, and the rectifier. At present, diodes are usually utilized in the rectifier of the HFDRC at dozens of MHz, causing significant power loss [7]. To solve this problem, synchronous rectification technology can be utilized.
The biggest challenge to introduce synchronous rectification technology into the HFDRC is the driving control of the synchronous rectifier (QSR). When synchronous rectification based on Si MOSFET is adopted, the driving modes mainly include square wave driving mode and resonant driving mode [8]. The loss of square wave driving mode is directly proportional to the operating frequency. As the operating frequency increases to tens of MHz, the loss of driver circuit will rises rapidly, making it difficult to apply in such a high frequency region. To reduce the driving loss, the QSR can be driven by a resonant driver circuit. There are two main types of resonant driver circuits: external resonant driver circuit and self-resonant driver circuit. Reference [9] introduced a two-way complementary external resonant driving mode for push-pull circuit. In a resonant converter operating at tens of MHz, the timing relationship between the main switch (Qmain) and QSR is not necessarily complementary; and it depends on the circuit parameters. Therefore, the resonant driving mode mentioned in [9] is not appropriate for synchronous rectification at high-frequency region.
To overcome the difficulty of controlling the timing between the Qmain and QSR, some scholars have proposed two self-resonant SRDC schemes for Si MOSFET. Reference [10] mentioned a self-resonant SRDC, whose excitation source is from the auxiliary winding of transformer. The auxiliary winding can realize electrical isolation and achieve a satisfactory driving effect. Nevertheless, this method requires additional auxiliary winding, increasing the volume and design difficulty. Reference [11] illustrated a self-resonant SRDC in which the excitation source is the drain-source voltage of QSR. The parasitic capacitor of QSR is applied to transmit the signal, whereas the amplitude and phase of the driving signal is adjusted by changing the parameters of other components in the feedback network. Due to the nonlinearity of the parasitic capacitor of the QSR, the driving signal is unstable. If the gate source or drain source of QSR was paralleled with capacitors to obtain a stable driving signal, the working state of QSR would be affected. Thus, this self-resonant SRDC greatly limits the stability of the driving signal and the freedom in the feedback network design.
All the aforementioned researches mainly focus on the SRDC with Si MOSFET. Compared with Si MOSFET, GaN devices possess the advantages of low on-resistance, small gate charge, excellent switching performance, high current density, and high power density [12], [13]. Therefore, GaN devices are suitable for high-frequency applications at ten MHz and above [14]- [16].
As for power converters based on GaN devices, a reliable GaN driver is critical for maintaining stable operation [17], [18]. In recent years, many scholars have proposed new ideas or designs in response to the challenges of GaN drivers, such as the stringent gate-source voltage limit, fast dv/dt behavior and high voltage drop during reverse conducting. Reference [19] introduced a synchronous gate driver with an adaptive detection function to ensure that the circuit achieves ZVS. Reference [20] proposed a highvoltage-level shifter with differential-mode noise blanking scheme, which can effectively improve the driving reliability of the converter in high-voltage and highfrequency occasions. Besides, reference [21] introduced a bipolar and a three-level gate drive voltage scheme, achieving a robust switching as well as low power losses during reverse conduction of the GaN device.
Currently, GaN devices are rarely used in MHz-level synchronous rectification circuits. However, with the advancement of wide bandgap devices and the increase in frequency and capacity, research in this area is urgently needed. Literature [22] reported an SRDC that combines the driver chip LM5114 with the second-order RC filter feedback network. A special phase shift is required in the feedback network to compensate for the long delays in the driver chip (typically 14 ns) and the comparator (9 ns). Nevertheless, this not only limits the switching frequency, but also increases the design complexity and reduces the flexibility of the feedback network design.
This paper proposes an in-phase feedback synchronous rectification driver circuit (SRDC) with external capacitors for GaN devices. Compared with the previous work, the proposed SRDC shows several advantages. Firstly, the sampling capacitors are separated from QSR, so that driving performance of the rectifier stage will not be affected when adjusting the amplitude-frequency characteristics of the feedback network. Secondly, the SRDC keeps the excitation source signal and the synchronous driving signal, vS, in-phase, which greatly improves the flexibility of the feedback network design to adjust the amplitude-frequency characteristics of vS. Thirdly, the SRDC drives GaN devices efficiently and makes the on-resistance low. According to the data sheet of the GaN device we use, the gate-source voltage needs to be controlled between 4.5 V and 5.5 V during the on-time to ensure extremely low on-resistance [23]. While the proposed SRDC can output a square wave signal stabilized above 4.5 V by comparing vS with the threshold voltage.
This paper is structured as follows. In Section II, the control method of the HFRDC and the applied rectifier are introduced; and the traditional SRDC is presented. The proposed SRDC is detailed in Section III. Section IV shows the experimental results based on the SRDC. Finally, the conclusion is presented in Section V.

A. CONTROL MODE OF HFDRC
For general power converters, the closed-loop control of the system is usually realized through pulse width modulation (PWM) [24] or pulse frequency modulation (PFM) [25], but neither of them is suitable for the HFDRC working at tens of MHz. The soft-switching characteristic of the HFDRC is achieved with a certain duty cycle. Under the PWM control method, the duty cycle of the switch is variable, causing the deterioration of the soft-switching characteristic and greatly increasing the switching loss. For the PFM control method, the frequency change of the system at high frequency requires an extremely fast response of the control system, which can be hardly fulfilled. Therefore, these two control methods are not suitable for HFDRCs.
The common control method for the HFDRC is hysteresis (ON-OFF) control [26], [27], which controls the enablement of the high-frequency driving signal through a low-frequency signal. Fig. 1 illustrates the operating principle block diagram of the HFDRC used in this paper, and Fig. 2 shows the main waveforms of ON-OFF control.  Its operating principle can be described as follows: the voltage dividing network samples the output voltage VO, and then compares VO with the reference voltage Vref with the high-speed comparator. When VO reaches the upper limit voltage VOH set by ON-OFF control, the control signal vctrl output by the comparator flips from high to low. On the one hand, vctrl can control the driver chip of Qmain with the high-speed optocoupler to prohibit the inverter from working. On the other hand, vctrl makes QSR turn off synchronously by controlling the SRDC. When VO decreases to the lower limit voltage VOL, vctrl changes from low to high. Then, the inverter and rectifier are re-enabled to work normally at 20 MHz and at the optimal working point to ensure that the converter works in the optimal resonant state, which is the prominent advantage of the ON-OFF control.

B. RECTIFIER OF HFDRC
In the HFDRC, the rectifier is designed to work in a resonant state to achieve zero-voltage-switching (ZVS) conditions for QSR. The rectifier in this paper adopts the current-source Class E rectifier [28], as shown in Fig. 3. Here, Iac is the input current source; LR is the resonant inductor; CR is the resonant capacitor, which absorbs the parasitic capacitor of QSR; CO is the output capacitor; and RL is the load resistor. The operating mode of the rectifier can be divided into two different parts. When QSR is on, all other components in the rectifier stage can be treated as short-circuited, so the equivalent impedance of the rectifier stage (Zrec) can be seen as zero. When QSR is off, the load and the filter capacitor are regarded as a constant voltage source, which can be regarded as short-circuited when analyzing Zrec. At this time, Zrec can be considered as a branch that LR and CR connected in parallel [29].

C. TRADITIONAL SRDC
The traditional SRDC based on Si MOSFET devices is shown in Fig. 4. The excitation source utilizes the drainsource voltage (vds) of QSR, and the way to sample vds uses the parasitic capacitors Cgd and Cgs of the corresponding QSR directly. Fig. 5 presents the time-domain relationship between vds and the gate-source voltage (vgs) of the traditional SRDC, and vds is in opposite phase with vgs. Besides, the duty cycle of QSR can be flexibly changed by adjusting the Vbias.
The transfer function of the traditional SRDC can be summarized as the following equation: By substituting the designed parameters in [30] into (1), the bode diagram can be plotted, as shown in Fig. 6.
According to the transfer function and bode diagram, it can be seen that vgs and vds exhibit opposite phases so that the operating frequency of the circuit is in front of the resonant point. Moreover, vgs needs to be maintained at a large amplitude to ensure low on-resistance for QSR.   For Si MOSFET operating at MHz level, the gate-drain capacitance Cgd is usually not large. For example, QSR SI7454DP used in [30] holds Cgd = 72 pF. If paralleling capacitor is added to the gate drain of QSR to improve the driving capability, the gate-drain impedance will be reduced. Thus, the risk of coupling vds to vgs will increase when QSR turns on, resulting in a large loss in the driver circuit, unstable vgs, and decreased switching speed. In addition, Cgd and Cgs vary non-linearly with the change of vds. As vds resonates, the unstable Cgd and Cgs will bring instability to the feedback network. Therefore, the best choice would be adjusting the gain and phase shift of the feedback network by changing Lg. Nevertheless, a small difference of Lg will lead to a drastic change in the amplitude and phase of vgs before the resonant point. To obtain the required phase of vgs by adjusting Lg will likely cause drastic changes in the amplitude of the vgs, which is not allowed for GaN devices. Moreover, driving GaN with a sinusoidal signal will not only increase the risk of breakdown, but also fail to keep the device in a low onresistance state during the on-time.

III. ANALYSIS ON PROPOSED SRDC
In the HFDRC, the switching timing of QSR needs to be strictly matched with the resonant state of the rectifier to achieve ZVS. The accurate switching timing of QSR is obtained through careful design of the feedback network.

A. OPERATING PRINCIPLE OF PROPOSED SRDC
Aiming at the problem that the design flexibility of the feedback network in the traditional SRDC is limited by the parasitic parameters of QSR, this paper proposes an in-phase feedback SRDC with external capacitors. The circuit structure is demonstrated in Fig. 7. It consists of a driver chip LMG1020 and a feedback network that is composed of external capacitors CS1 and CS2, inductor LS, resistor RS, and DC bias source Vbias, where no additional comparator is required. Fig. 8 presents the time-domain relationship among the drain-source voltage of QSR (vds_SR), vS, and the gate-source voltage of QSR (vgs_SR). Among them, ton_delay and toff_delay represent the turn-on delay and turn-off delay of the driver chip (typical 2.5 ns), respectively; and VL and VH are the low-level threshold and high-level threshold of the driver chip, respectively.  The operating principle of the proposed SRDC is described as follows: the excitation source vds_SR generates vS through the function of the feedback network. And vS goes to the inverting input of the driver chip, making vS inphase with vds_SR, so that the operating frequency band is located after the resonant point. Meanwhile, the noninverting input of the driver chip is enabled by the control signal vctrl of the ON-OFF control system. The driving timing of QSR is determined by vS. As vS decreases from high to VL, QSR turns on after ton_delay; and as vS rises from low to VH, QSR turns off after toff_delay. The driver chip's output, vgs_SR is close to a square wave, which ensures the low on-resistance of the GaN devices during the on-time.
In this work, Vbias is generated by the voltage regulator chip LP3878MR-ADJ, which provides DC bias for vS to realize a flexible duty-cycle adjustment. The part-to-part variation of the driver chip can be compensated via finetuning Vbias. It is important that the amplitude of the Vbias must be higher than VL. Otherwise, vS will always be lower than VL, making QSR straight on.

B. FEEDBACK NETWORK OF PROPOSED SRDC
To get the transfer function of vds_SR and vS, Vbias is set to zero in Fig. 7 to get the AC signal feedback network shown in Fig. 9. The transfer function of vds_SR and vS in Fig.9 can be derived as: The phase of the transfer function given in (3) can be expressed as: It can be seen from (3) and (4) that LS, CS1, CS2, and RS influence the characteristics of the feedback network. The following is the analysis of the detailed effect of these parameters. Fig. 10 shows the bode diagram of the feedback network with different LS. vds_SR and vS have an in-phase feedback relationship. The operating frequency band locates after the resonant point. And the advantage is that the amplitude of vS is not oversensitive to the changes in LS. As can be seen from Fig. 10, vS can maintain a high and steady amplitude, whereas the phase shift becomes obvious as LS changes in a relatively large range. By adjusting LS, the phase of vS can be flexibly adjusted without causing drastic changes in amplitude. Fig. 11 presents the bode diagram of the feedback network with different CS1. It can be found that the amplitude of vS increases with the growth of CS1, but the phase is almost unchanged. Therefore, we can fine-tune CS1 to adjust the amplitude of vS in a small range without changing the phase shift. Fig. 12 provides the bode diagram of the feedback network with different CS2. Obviously, CS2 has a vital impact on the amplitude of vS. The larger the CS2, the lower the amplitude and the smaller the phase shift.     Theoretically, the proper phase can be obtained by adjusting RS. But the growth of RS also increases the driving loss. Hence, RS in series should not be too large.
From the above analysis, it can be seen that compared with the traditional SRDC, the sensitivity of vS to the components of the feedback network is greatly reduced. Proper amplitude and phase of vS can be realized by adjusting LS, CS1, CS2, and RS. This makes circuit calibration so much easier.

C. PARAMETER DESIGN METHOD
The transmission gain of the feedback network can be obtained by substituting By sorting out (4), the identity can be derived as follows: The expression of LS can be derived by substituting (6) into (5): Combining (6) and (7), the expression of RS becomes as follows: From (6) and (7), it becomes obvious that for the determined gain and phase shift, LS and RS can be calculated when CS1 and CS2 are given.
At tens of MHz frequency, the capacitance and inductance are as low as pF and nH level, respectively. The parasitic parameters of traces and devices are in the same or close orders of magnitude. Therefore, it is important to minimize the loop area of the gate driver and pay attention to the grounding in PCB layout. For this reason, circuit debugging requires precise theoretical design guidance.
In addition, the chip used in the design has extremely low latency; and the comparator is eliminated. As the result, the converter can operate at very high frequency, while the chip delay can be compensated by fine-tuning the component parameters, which ensures the flexibility and convenience of the design.

IV. EXPERIMENTS
To verify the the theoretical analysis, a 20 MHz prototype with 18 V input and 5 V / 2 A output is built. As shown in Fig. 14, the converter topology [31] contains an isolated Class Φ2 inverter and a current-source Class E rectifier, where GaN devices are used at both Qmain and QSR. The aircore planar transformer [32] and the air-core inductor are also introduced. Qmain chooses the external driving mode, and QSR adopts the in-phase feedback SRDC with external capacitors. The experimental prototype is shown in Fig. 15. The parameters of the SRDC are calculated with the proposed method in Section III C. The result is presented in Table 1. Table 2

exhibits the part numbers of Qmain and QSR.
And the values of the main circuit components are shown in Table 3. Among them, L11, L22, and k are equivalent Tmodel parameters of the transformer, which are obtained by finite element simulation. Cds is the parasitic capacitor of Qmain.

Component Part number
Qmain GS61008T QSR EPC2015C Fig. 16 shows the drain-source voltage of Qmain (vds_main), the gate-drain voltage of Qmain (vgs_main), and the control signal (v'ctrl) output by optocoupler under ON-OFF control cycle at full load. Fig. 17 shows vds_SR, vgs_SR, and vS under ON-OFF control cycle at full load. The ON-OFF control frequency of Qmain and QSR in these figures are both about 41 kHz, which means that Qmain and QSR cooperate well.
The non-inverting input of the driver chip is enabled by vctrl. When vctrl is low, the driver chip no longer drives QSR; and the converter turns off. Meanwhile, vds_SR gradually reaches the output voltage (5V). When vctrl is high, the driver chip is re-enabled and QSR continues to work at 20 MHz. Then, the converter turns on and quickly enters a steady state.    18 shows vds_SR, vgs_SR, and vS within switching cycle. It can be seen that the delay of the driver chip is compensated by the feedback network. vS is well-matched with the phase of vds_SR to control the driving timing, making QSR turn on and turn off accurately and maintain its soft-switching characteristics. The switching of QSR under ON-OFF control requires fast dynamic response to establish a normal driving timing of soft switching. Fig. 19 and 20 show the waveforms of vds_SR, vgs_SR, and vS when the converter is at start-up and shut-down, respectively.  It can be seen that the time from the resonant working state to the steady-state working state is about 100 ns during the start-up process of the converter. When the converter shuts down, the whole process takes about 350 ns. After entering the steady state, the driving timing sequence is accurate to keep an efficient and reliable operation of the rectifier.
In the construction of an isolated power converter operating at MHz, the design of the inverter is based on the feasibility of the rectifier. Only when the rectifier and its driver circuit are reasonable and effective, the inverter and the whole prototype can work normally. Fig. 21 shows the output voltage waveform of the prototype at full load. The output voltage of the prototype is stable at 5 V. The ripple peak-to-peak is approximately 300 mV. The prototype can work steadily under ON-OFF control.  Table 4 depicts the property comparisons of some typical high frequency topologies. It can be seen that the proposed converter has the lowest switch drain-source voltage stress. Even working at such a high frequency and at such a large input-to-output voltage ratio, the converter still possesses a satisfactory efficiency.

V. CONCLUSION
Due to the shortcomings of oversensitive parameter adjustment and unstable feedback network, the traditional SRDC is not suitable for synchronous rectification based on GaN devices at tens of MHz. This paper proposes a novel in-phase feedback SRDC with external capacitors which is suitable for GaN devices. The SRDC uses the external capacitors to sample the excitation source, and provides a stable and reliable driving signal by combining the selfresonant feedback network with the driver chip. Meanwhile, the operating frequency band is set behind the resonant point, which gives the feedback network plenty of gain margin and phase margin. This paper thoroughly analyzes the operating principle and characteristics of the feedback network, and provides the detailed parameter design method. The experiment is carried out on a 20 MHz prototype with 18 V input, and 5 V/2 A output. The experimental result demonstrates that the proposed scheme can provide reliable and stable driving signal for synchronous rectification based on GaN at 20 MHz; and the prototype can work stably, which verifies the feasibility and effectiveness of the designed SRDC.