A PWM Nie-Tan Type-Reducer Circuit for a Low-Power Interval Type-2 Fuzzy Controller

A novel Type-Reduction/Defuzzification circuit architecture for an analog interval type-2 fuzzy inference system is proposed. Based on the Nie-Tan type-reduction method, the circuit operates with current-mode inputs, representing the firing intervals of the rules created by the inference engine, and generating a PWM output. It is demonstrated that by selecting an appropriate number of consequents it is possible to create the PWM output directly, without the need for analog multiplier/divider circuits. This feature makes the circuit very simple, aiding in the design process, while the PWM output makes it suitable for controlling DC-DC converters, maximum power point trackers (MPPT) for energy generators, or other switching applications. It is designed to achieve very low power consumption, allowing its use in power restrained environments, such as energy harvesting systems. The circuit was designed using TSMC 0.18μm technology, in CADENCE Virtuoso software, and simulated for different combinations of input values, demonstrating its capabilities. It was also simulated as part of a type-2 fuzzy inference system with two inputs, nine rules, and firing intervals represented by currents within 0 and 10μA. The circuit was prototyped, and the experimental average power consumption was only 53.8μW, validating its low power consumption characteristic.


I. INTRODUCTION
Many low-power applications require non-linear control systems with enough robustness to work in the presence of uncertainties. Those applications can rely on fuzzy logic for a compact and relatively simple representation of complex relations. Several fuzzy inference systems have been proposed to control DC-AC inverters [1], DC-DC converters [2]- [5], active power filters [6], maximum power point trackers (MPPT) for wind energy conversion [7], solar photovoltaic generators [8]- [10], and energy harvesting systems [11], for example.
Depending on the application, however, a hardware implementation of such controllers must present a very low power consumption, especially in the case of the MPPT for energy harvesting, in which the efficiency of the whole system can be directly affected by the power consumption of the control circuit. One type of implementation that can fulfill this role, presenting great tolerance to uncertainties and the potential for low power consumption, is an analog interval type-2 fuzzy controller. An interval type-2 fuzzy inference system usually consists of five blocks: The Fuzzifier, the Inference Engine, the Rule Base, the Type-Reducer, and the Defuzzifier [12].
Previous studies demonstrated the potential of this kind of controller, presenting greater robustness to uncertainty [13] and being capable of representing systems with a smaller number of membership functions and rules when compared with an equivalent type-1 fuzzy inference system [12]. This is especially important to reduce total power in an analog implementation, given that fewer membership functions and rules mean fewer hardware components required to generate those functions [14]. This could mean a significant advantage for type-2 hardware implementations in terms of power. The use of analog hardware also presents the benefit of not requiring A/D and D/A converters, as would be the case in a digital implementation, further assisting in the reduction of power consumption. There is, however, the difficulty of an increased computational cost associated with the typereduction/output processing, that can spoil any obtained power gain, preventing practical implementations.
A method of type-reduction for interval type-2 inference systems, proposed as a closed-form alternative to the iterative algorithms (such as the Karnik-Mendel [15] and Wu-Mendel methods [16]), is called the Nie-Tan method (NT) [17] and is particularly well suited for analog hardware implementations. The accuracy of the NT method has been demonstrated [18], and while some analog controllers have already employed it using current-mode multiplier/divider circuits [19]- [21], the design process of multiplier/dividers must deal with several non-linear effects, such as mismatch and channel-length modulation, that can degrade the performance of the circuit.
Given the need for low-power controllers in switching applications, such as energy harvesting systems, the circuit proposed in this work aims to demonstrate that it is possible to conceive a simple analog architecture capable of implementing the complete expression that represents the NT type-reduction with current-mode inputs (representing the firing levels from the inference engine), directly creating a PWM output without multiplier/divider circuits or other additional components.
The paper is organized as follows: Section II presents the Type-Reducer analog hardware considerations and the proposed architecture is discussed. Section III presents the simulation results under different conditions, including the results as part of a complete type-2 fuzzy inference system. The experimental results which were obtained with the prototyped IC are shown in Section IV, followed by the conclusion in Section V.

II. TYPE-REDUCTION PWM ARCHITECTURE
The standard type-reduction method, known as the Karnik-Mendel method (KM) is an iterative algorithm that aims to obtain both the smallest and the largest centroids of the embedded type-1 fuzzy sets and considers the average of both values as the crisp, defuzzified output [15].
Other methods have been proposed to improve the algorithm's performance, such as the Wu-Mendel (Extended Karnik-Mendel) method [16] and the Uncertainty bounds method [22], but the main issue remains that real-time and embedded systems may not have enough speed to depend on an iterative or mathematically complex process to decide the output value [23]. Also, very low-power applications need an implementation that is accurate enough to operate properly, but as simple as possible to minimize power consumption. One possible approach to achieving this goal is through analog hardware. The representation of fuzzy values by analog variables is a natural choice, since they are continuous, by definition. The inherent ambiguity of fuzzy logic offsets the accuracy limitations of an analog implementation [24].
Analog computations, however, are only feasible if in a closed form, i.e. not an iterative process. For that, the NT method is especially well-suited, since it provides a simple, closed-form expression, dependent only on the rules' activation levels and the consequents' centroids. The Nie-Tan method consists of taking the average of the upper and lower firing levels associated with each consequent before performing a center of sets or zero-order TSK defuzzification [17]. Mathematically, this corresponds to applying (1) to each firing interval obtained by the inference engine and then performing the operation in (2).
The variable u(x) represents the crisp output of the system, while ( Analog type-2 fuzzy controllers found in the literature generally implement the expression in (3) with multiplier/divider circuits operating in current-mode [19], [20]. Equation (3) is very similar to a Center-of-Sets defuzzification, and most type-1 analog defuzzifiers also operate with multiplier/divider circuits in current-mode [25], [26], voltage mode [27], and some with current-input and voltage-output circuits [28]- [30]. The current-mode implementation has the advantages of a higher dynamic range and simpler implementation of the addition operation. Multiplier/divider circuits operating in current-mode and with MOS transistors in the saturation region depend on the geometric-mean/squarer circuits to generate the result, which can be very susceptible to mismatch, channel length modulation, and other effects that disturb/modify the quadratic model, thus complicating the design process. Multiplier/divider circuits that operate in weak-inversion have been proposed [31], and though they have low-power consumption, they are even more prone to suffer from mismatch and also tend to present lower speeds [32]. A different approach could be useful to facilitate the use of fuzzy inference systems in practical power-constrained systems.
Many applications, such as the MPPT and DC-DC converter examples cited in the Introduction, use a PWM signal to control the system. In order to use existing analog type-reducer/defuzzifier architectures in fuzzy controllers for this kind of system (in which the output of the fuzzy inference system represents the duty cycle of the PWM signal), additional circuits would be necessary to convert a current/voltage into a PWM equivalent. By making the output processing stage of the fuzzy system generate a PWM signal directly, without the need for additional components, both a power reduction and a circuit simplification can be achieved. The idea of using PWM signals directly during the fuzzy inference process has been applied by Tombs et al. [33] in an architecture where the membership values of type-1 fuzzy sets, represented by currents, are converted to PWM signals by comparing the integrated voltage with a fixed reference ramp. The inference engine in that architecture is significantly simplified, being performed only by AND gates that effectively implement the minimum operation. The main disadvantage in doing this is that defuzzification becomes too complex. A transconductance amplifier and an integrator are used for multiplication, and a successive approximation logic circuit and D/A converter are used for division, in a strategy that is not suitable for low-power implementations. Also using PWM signals, the work by Alarcon et al. [34] creates a PWM output for a type-1 defuzzifier by implementing the division between two currents, and it assumes the multiplications between the currents that represent the firing levels and the consequents are performed by a previous multiplier circuit.
In this context, the architecture for the typereducer/defuzzifier stage of a type-2 fuzzy controller proposed in this work receives the firing intervals coming from the inference engine in current-mode and makes the conversion directly into a PWM output signal. It is demonstrated that, for a given number of consequents, a simple structure can implement the complete equation in (3) without any multiplier/divider circuits. This is a reasonable design choice, given that controllers with a small rule-base are easier to design, entail simpler hardware (low power), and also present good performance, sometimes even better than systems with a larger rule-base [12], [35], [36].
The operating principle of the proposed architecture is based, as in [34], on the implicit division present in the PWM conversion process. Section A explains this process while Section B shows how, under certain conditions, it can be used to yield the complete type-reduction/defuzzification expression. Section C details the circuit designed to implement the proposed strategy.

A. PWM DIVISION
Usually, a PWM signal is generated by comparing the variable with a fixed reference ramp. If this reference is also dependent on a second variable, the PWM signal can represent the result of the division operation between these two variables, coded in the fraction of the total cycle time spent on the high level. The variables of interest in this implementation are assumed to be currents representing the firing intervals associated with each consequent of the type-2 fuzzy inference system. Therefore, a division between two analog currents is necessary and can be performed by integrating the two currents in sequence and comparing the voltages as illustrated in Fig. 1.

FIGURE 1. PWM division of two currents by integration and comparison of voltages.
Assuming that the currents change little during each period, i.e. they remain approximately constant, the expression for crossover voltage v can be written as a function of two currents i1 and i2, as shown in (4) and (5).
The capacitance for both integrators is C, the period is T and the time between the beginning of the second current integration and the voltage crossover is Δt. Combining (4) and (5) into (6), the division between i1 and i2 is encoded in the time fraction Δt/T.
The fact that this result is available for half of the total time required to obtain it is used in favor of the architecture, as explained in Section B.

B. TYPE-REDUCER/DEFUZZIFIER
If one makes the assumption that three consequents are used in the system (aiming at an inference process with a nine-rule MacVicar-Wheelan rule-base [36]) and named N, Z, and P, then the complete NT Type-reduction/defuzzification expression in (3) can be written as in (7).
Rewriting the term corresponding to the consequent Z and grouping upper and lower consequents, as in (2), an equivalent expression is obtained, as shown in (8) (8) If the consequents' values yN, yZ, and yP are chosen to be 0, 0.5, and 1, to reflect the full range of possible duty cycle values, then the output becomes (9).
Expression (9) can be implemented as a PWM signal by combining two waveforms in sequence, as in Fig. 2. It corresponds to the division associated with the N consequent, from 0 to T, and with the P consequent from T to 2T.
Time intervals tN and tP are obtained by PWM division, as described in Section A, and therefore have the values described by (11) and (12), respectively.
At each period T, individual currents iN and iP are compared to the sum of all currents representing the firing intervals, and the results are intercalated at the output, with an inverted signal for the N portion of the signal. Combining  The expression obtained in (13) is equivalent to (9), given that currents iN, iZ and iP represent the sum of upper and lower firing levels of each consequent as determined by the inference engine. To form the desired PWM output, with the two periods associated with consequents N and P, the division process detailed in Section A is performed as shown in Fig. 3.   Table 2

. (a) Output with 0% Duty Cycle. (b) Output with 25% Duty Cycle. (c) Output with 50% Duty Cycle. (d) Output with 75% Duty Cycle. (e) Output with 100% Duty Cycle. (f) Control signals EN and RST
Voltages VN, VP, and VS are obtained respectively by the integration of the currents iN, iP, and of the sum of all currents (iN+iZ+iP). The control signals required to set the period T (EN) and to reset each of the capacitors at the appropriate time (RST, RN, and RP) are also shown in Fig. 3.

C. CIRCUIT ARCHITECTURE
The proposed architecture requires three independent capacitors to integrate each current. Wide-swing current mirrors are used to feed the integrators, and transmission gates control which currents are injected during each part of the cycle. Simple voltage comparators are used to implement the division corresponding to each half of the period, and transmission gates switch between them to create the output signal. Fig. 4 illustrates the proposed circuit architecture. Signals EN and RST are control inputs, and signals RN and RP are generated internally as /EN&&RST and EN&&RST, respectively. While EN is in the HIGH state, the capacitors CN and CS are charging, whereas the capacitor CP is not. Its voltage VP is held constant and is compared with the voltage VS to generate the part of the output signal associated with consequent P. When EN switches to the LOW state, capacitors CP and CS reset and start charging again, while capacitor CN maintains its voltage VN constant, to be compared with VS, generating the other part of the output, associated with consequent N. When EN switches back to HIGH, capacitors CN and CS reset, and the cycle restarts. The voltage comparators are high-gain differential amplifiers, designed to work with low voltage and low bias current in order to achieve low power consumption.

III. SIMULATION RESULTS
The proposed circuit architecture was designed with TSMC 0.18µm technology and simulated using Cadence Virtuoso software. The parameters common to all tests are specified in Table 1. To verify the operation in the range of possible duty cycles, from 0 to 100%, different combinations of input currents were tested, as described in Table 2. The average power consumption obtained for each case is also displayed in Table 2 and the simulation results are as shown in Fig. 5. For each input combination, the voltage integration signals VN, VP, and VS are also shown. The waveforms are according to the designed behavior explained in Section II and illustrated in Fig. 3. Importantly, as shown by the simulation results, the charge injection effect could be neglected in this implementation due to the fact that the load capacitances are much larger than the gate to drain capacitances of the devices used in the switches.  To guarantee the robustness of the circuit against process variations, a corner analysis was performed for different corners under different temperature conditions. The output results for the cases with duty-cycle equal to 25% and 75% are shown in Fig. 6. These two cases present the largest error, up to 3.5%, which is certainly small enough for practical fuzzy implementations, where this and other sources of uncertainty can be treated by adjusting the input membership functions accordingly.   Table 2. The plot groups the error to the nominal case in bins with a size equal to 0.1%. The average error is 0.22% and the standard deviation is equal to 0.51%. Both Corner and Monte Carlo results reflect the robustness of the circuit against process variations.
In order to verify the circuit's immunity to power supply noise, a simulation was performed to obtain the gain at the output for different frequencies (ranging from 10Hz to 10MHz).  (10Hz to 10MHz). Fig. 8 shows that the power supply noise is attenuated by about 10dB with respect to the output terminal, demonstrating that the circuit is capable of dealing with power supply noise.
Another simulation was conducted, this time taking into consideration a complete type-2 fuzzy inference system. It was implemented in order to test the proposed output stage operating in a system with a MacVicar-Wheelan Rule Base. Assuming a system with two inputs, each one associated with the proposed type-2 membership functions shown in Fig. 9, and with the rule-base described in Table 3 (with  antecedents N1, Z1, P1, N2, Z2, and P2, and consequents N, Z, and P), it is possible to mathematically find the ideal output of an NT type-reducer/defuzzifier.   The inference process uses MIN/MAX operators as tnorm and t-conorm, respectively. Fig. 10 shows the ideal output in terms of the duty cycle as a function of the two inputs.  Considering an inference engine that outputs the firing intervals of the consequents in current-mode, in the range [0,10µA], such as in [14], [19], [37], it is possible to simulate the response of the proposed circuit and similarly plot its output as a function of the two inputs of the system. The result is shown in Fig.11, as well as the error when compared to the ideal case.
The power consumption corresponding to the output surface was simulated as well, and the result was plotted in Fig.12. The average power consumption was equal to 51.4µW, the comparator circuits are responsible for about 10% of that value (5.5µW), while the current mirrors feeding the capacitors during the charging process are responsible for the remaining 90%. In the worst case, the maximum power was equal to 81.6µW.

IV. EXPERIMENTAL RESULTS
The type-reduction/defuzzifier circuit with PWM output, as described in Section II and simulated in Section III, was manufactured using TSMC 0.18µm technology, in cooperation with IMEC, in a multi-project wafer (MPW) run, which is part of the mini@sic program of Europractice-IC. The layout of the proposed circuit and the micrograph of the testing chip are shown in Fig.13. Common analog layout techniques (such as interdigitation in the current mirrors) were employed to prevent mismatch and other non-ideal effects [38]. Measurements were performed with the same input current values as in Table 2. The output results have duty cycles as shown in Fig. 14, which are consistent with the values expected from Table 2. The duty cycle was also measured considering a complete type-2 fuzzy inference system (i.e. the output duty cycle for each combination of the input pair of the complete system), by feeding the firing intervals of the inference engine as described in Section IV to the output processing circuit. Those results were plotted in Fig. 15. The experimental error is also plotted in Fig. 15(b), showing that the corresponding root mean square error is equal to 1.4%, and in the worst case the error is smaller than 4%, which is within the expected margin and certainly acceptable in a practical implementation of a fuzzy system.
The power consumption corresponding to the output surface was also measured, and the result was plotted in Fig.16. The measured average power consumption was equal to 53.8µW, and the maximum power was equal to 86.5µW. The experimental power was about 3µW larger than the simulated values due to a larger output capacitance. The results demonstrate the proposed circuit's capability to operate as an NT Type-reducer/defuzzifier for PWM applications with a simpler architecture and with small power consumption, even smaller than the individual power consumption of analog multiplier/divider circuits, such as [39] with 120µW and [40] with 60µW, as shown by the comparison in Table 4.
This comparison must also take into account the fact that at least two current-mode multiplier/divider circuits and a PWM generator circuit would be needed to create an output equivalent to the one generated by the proposed architecture. Table 4 also includes the analog type-2 fuzzy controllers in the literature that implement the Nie-Tan type-reduction method, as well as three type-1 analog fuzzy circuits, emphasizing the low power feature of the proposed architecture.

V. CONCLUSION
A novel architecture for a type-reduction/defuzzifier circuit was proposed that generates a PWM output from currentmode inputs and does not depend on analog multiplier/divider circuits, thus greatly simplifying the design process and facilitating the use of analog type-2 fuzzy inference systems in real applications. The type-reduction stage of a type-2 fuzzy inference system is usually a computationally-intensive process, presenting many challenges for an analog implementation. The Nie-Tan method presents a simple, closed-formed expression, that facilitates its realization in analog hardware. It was demonstrated that appropriately choosing the number of consequents allows the creation of a circuit that produces the output of the fuzzy system directly as a PWM signal. The circuit was tested as part of a complete interval type-2 fuzzy inference system, presenting an output error smaller than 4%. The fact that the proposed architecture does not require multiplier/divider circuits also reduces power consumption, as is demonstrated by the simulated and experimental results. The circuit was prototyped, presenting a measured power consumption of 53.8 µW with a power supply of 1.2V. The consumption is even smaller than that of a single analog multiplier/divider, of which at least two would be required, along with a PWM generator, to produce an equivalent output.
The PWM output makes the integration with DC-DC converters and other switching applications quite simple, and the low power consumption presented makes it suitable for small, embedded applications such as an energy harvester's MPPT system.