Dual Active Compensation for Voltage Source Rectifiers Under Very Weak Grid Conditions

DC subgrids consisting of modern active loads (ALs) and local dc distributed generation (DG) units are normally interfaced with the main ac grid by utilizing bidirectional voltage source converters (VSCs). Under the very weak grid (VWG) conditions, the integration of voltage-oriented controlled (VOC) VSCs in the inversion mode becomes very challenging and therefore undamped oscillations in the power and angle responses are yielded. Most of the existing works address this issue for VSCs in the inversion mode of operation. However, integration of VSCs in the rectification mode with the consideration of the outer loop controllers into the VWGs has not been reported. To fill up this gap, a state-space model of the bidirectional VSC-to-weak grid (VSC-WG) system is developed in this work with an emphasis on the rectification mode of operation. A modal-sensitivity analysis is then utilized to evaluate small-signal stability of the system, identify the dominant modes, and investigate the system states that have a major influence on these modes. The results reveal two pairs of unstable complex modes that are correlated with the dynamic interaction between the VOC-based VSCs and the VWG impedance. It is also shown that the stability margin of VSCs in the rectification mode is less than that of the inversion mode under the same VWG conditions. To enhance the integration of the VSCs in the rectification mode, a dual-active compensation (DAC) scheme is proposed to mitigate the instabilities under VWG conditions. Several time-domain simulation results are presented to verify the validity of the small-signal model and demonstrate the effectiveness of the DAC scheme under the VWG conditions. Finally, hardware-in-the-loop (HIL) real-time experimental results are presented to validate the simulation results.


I. Introduction
Power electronic converters (PECs) are used to interface many types of clean and renewable resources of energy such as photovoltaic panels and fuel-cells to the ac power grid registering them as distributed generations (DGs) [1]. There are many types of loads such as battery banks, data centers, LEDs, induction motors drives, and plug-in electric vehicles all over ac grids that are connected to the grid via PECs. Moreover, PECs can operate as bidirectional interfaces between the main ac grid and dc subgrids, such as high-voltage dc (HVDC) or dc microgrid (dc MG) systems, managing the power flow between the two sides.
One of the most commonly used PECs in DG applications is the voltage source converter (VSC) [2]− [5] and, among them, the two-level VSC structure is the dominant block in medium and high-power applications [5]. A widely accepted control strategy in the industry for VSCs is the voltage-oriented control (VOC) method [6] (or current-mode control [5]). In the VOC method, the inner current control loops (CC) with fast dynamics, and outer control loops, including dc voltage control (DVC), ac voltage control (AVC), and phaselocked loop (PLL), with slower dynamics, are established in the direct-quadrature (dq) reference frame (dq-RF) which is synchronous with the grid voltage vector at the point of common coupling (PCC). If the VSC is connected to a stiff grid (SG), where the grid equivalent impedance is negligible, the variation in the PCC voltage magnitude and frequency can be neglected. Hence, the VSC output currents in the dq channels are proportional to the instantaneous active and reactive power exchanged between the VSC and the grid, respectively. Therefore, the design of the VOC becomes independent of the rest of the grid.
In certain cases, such as rural areas, islands, and charging stations for electric vehicles, the loads might be far away from the PCC [7]. Similarly, DG systems such as photovoltaic units and wind farms are usually located in distant places with respect to the center of loads [8]− [11]. Moreover, VSC-based HVDC systems and DC MG can be connected to highimpedance ac grids [12]− [14]. All these examples show that there can be long distances between the interfacing VSCs and the main ac grids. Therefore, the grid equivalent series impedance cannot be ignored. In these cases, the grid is known as a weak grid (WG) and the stability of the VSC-to-WG system (VSC-WG) becomes very challenging. The voltage at the PCC in WGs features large fluctuations especially during transients because the PCC voltage is a function of the VSC output current and power. In other words, the VOC-based VSC and the grid dynamics are undesirably coupled [15]. Therefore, the design of the VSC control system cannot be achieved without considering the main ac grid parameters. Moreover, the WG impedance might have a wide range of variations due to the loads variations, grid reconfigurations, and faults [7], [9], [16], [17]. However, to realize the plug-andplay characteristics in modern power systems [7], the control design needs to allow seamless integration of the VSC with no prior knowledge of the grid parameters.
The strength of a power grid against the connected VSC is usually evaluated by the short circuit ratio, which is the ratio of the ac grid symmetrical short circuit level at the PCC to the VSC rated dc power [18]. The ac grid is considered weak when 2< SCR < 3 (WG); and very weak (VWG), when 1 < SCR < 2 [18]− [20]. If SCR > 3, the grid is regarded as a stiff grid (SG). The VOC of VSC has a detrimental effect on the stability of the grid-VSC interconnection and can shift the location of the system eigenvalues which might result in poorly damped dynamics and power oscillations [21]. The smaller the SCR level is, the more prone is the system to instability [22].
The interaction dynamics between the three-phase VSCs in the rectification mode and SGs are studied in [23]. Therein, the rectifier is initially modeled by an ideal constant power load (CPL) and it is shown that the CPL introduces a negative incremental resistance that becomes prominent at a certain level of power which excites the resonance frequency of the VSC LC filter and as a result, the system becomes unstable. Further investigation of this problem is carried out in [5]. According to [5], the resulting transfer function of the VSC represents a nonminimum-phase zero in the rectification mode which reduces the closed-loop stability margin of the gridconnected VSC whereas the system remains stable in the inversion mode.
Several studies about the VSC-WG systems have shown unstable interaction dynamics. According to [21], even without considering the outer control loops, i.e., the DVC, the AVC, and the PLL, instability can happen due to the interaction of the CC with the VWG impedance. In [1], [8], [17], [15], [24]− [31], it is shown that the interaction between the PLL unit of VSCs and the WG impedances can be another source of instability. This undesired phenomenon is called the grid synchronization instability (GSI) [1], [31]. This issue is also another limiting factor for the active power transfer between the WGs and VSCs [1]. Moreover, the instability due to the GSI is dependent on the operation mode of the VSC, such that the VSC-WG system is stable for a wider range of SCR in the inversion mode than in the rectification mode. In other words, a higher power transfer is allowed between the VSC and the WG when the VSC is operating in the inversion mode. Therefore, improving the system stability in the rectification mode is more critical than the inversion mode under VWG conditions; a challenge that has not been widely investigated in the literature.
Since a high-bandwidth PLL decreases the damping of the grid-connected VSC systems [1], [21], [31], several researchers have suggested the idea of reducing the PLL bandwidth as a remedy for fixing the GSI problem and increasing the real power transfer in VSC-WG systems. However, this method often results in a PLL with a very slow dynamic response which is not desirable (see e.g., [5], [32], [33]). Modifying the structure of the outer control loops, the AVC and PLL, by adding linear functions of output voltage and currents has been proposed to improve the VSC-WG stability [15], [26], [32], [34]. Essentially, these methods change the output impedance of the VSC such that the sourceload admittance matching holds between the VSC and WG. Thus, the VSC-WG systems stability is preserved according to the Nyquist stability criterion [35]. However, most of these methods address the inversion mode of operation whereas the more challenging rectification mode is not considered. Further, the level of improvement in the VSC-WG system stability is limited to SCR = 2. The compensation of the VWG impedance with a negative virtual impedance that is injected by a front-end VSC has been achieved in an HVDC system assuming that the dc-side voltage is maintained sufficiently high and hence the overmodulation is avoided [33]. Moreover, the dc-side voltage is assumed to be a constant value, and therefore, the DVC is not applied to the VSC. The gain scheduling method is used to design the proposed outer AVC of a front-end VSC of an HVDC system [20]. Similar to [33], the VSC-WG system stability is maintained at SCR = 1 in both directions, yet, at the expense of a complicated AVC system that relies on a lookup table to evaluate four pairs of control parameters sets. However, the key disadvantage of the preceding methods is that the steady-state responses of the VSC is affected especially under the VWG conditions.
Emulating the characteristics of synchronous machines (SM) has inspired several researchers to develop power synchronization control (PSC) [19], [24], [37]. As a major feature of the PSC, the PLL loop is not required, and the inner CC is replaced by a voltage control loop. Therefore, the integration of VSCs into the VWG can be achieved. While the majority of works about PSC have been done for VSCs in the inversion mode, the rectification mode of operation is also suggested to improve the stability of the WGs when supplying several VSC-interfaced loads [22]. However, since the current is not directly controlled, the control system must dynamically switch to a current limiting operation under severe transients such as faults which is practically challenging [33]. Therefore, as long as stability issues in the VSC-WG systems can be mitigated, the VOC is still the preferred method [33].
A simple and effective method that can mitigate instabilities due to the interconnection of VOC-based VSCs, in the rectification mode, and ac grids, with extremely low SCRs, has not been presented in the literature so far. Motivated by this drawback, a simple and lossless dual active compensation (DAC) scheme is proposed in this work that can be effortlessly integrated into the existing VOC. Upon incorporating the proposed dual-compensation scheme, the dynamic responses of the VOC loops are not negatively affected, and the steadystate values remain unchanged. Therefore, there is no need to redesign the VSC control system. The contributions out of this work are enlisted as follows.  Stability analysis and assessment of the operation of the VSCs in the inversion and rectification modes under the VWG condition.  Development of an actively compensated VSC-WG system, using the proposed DAC compensator, to achieve stable performance in the rectification mode under the VWG condition.  Development of the small-signal model of the VSC-WG system where the dynamics of VSC outer control loops and the proposed DAC are considered.  Verification of the effectiveness of the compensated VSC-WG systems following large-signal disturbances such as step changes in the current and voltage references and grid angle disturbances. The rest of the paper is structured as follows. In Section II, the nonlinear model of the VSC-WG system is developed in the dq-RF followed by a discussion about the VSC controller design. Section III discusses the correlation between the power transfer capability of VSC-WG system and the SCR in the rectification mode. In Section IV, a small-signal stability analysis of the VSC-WG system in the rectification mode is studied using the linearized model of the system. Then, the modal and sensitivity analyses are carried out under the VWG conditions. In Section V, the proposed DAC scheme is introduced which is followed by a discussion about designing the DAC parameters using the root-locus method. Section VI provides the large-signal simulation results. The real-time verification of the proposed method is presented in Section VII. Finally, the paper is concluded in Section VIII. Fig. 1(a) shows a three-phase VSC in the rectification mode that is supplying a generic dc load at the dc-side with the nominal power Pn. The dc load is modeled by a current source in parallel with a dc filter capacitor. At the ac-side, the VSC, which is cascaded by an LC filter with a passive damping rd [38], is connected to the PCC. The role of the LC filter in this arrangement is to reject the switching harmonics from affecting the VSC output voltage vo. The PCC is connected to a step-down transformer Tr which, on the high-voltage side, is connected to a WG that is modeled as an ideal voltage source, with constant voltage vg and constant frequency ωg, i.e., infinite ac bus, in series with a high-value equivalent impedance. The WG impedance and Tr leakage impedance are lumped together and shown in Fig. 1(a) as an RL impedance with Lg and rg as the inductive and resistive parts, respectively. The complete system parameters are depicted in Appendix A. Fig. 1(b) shows the VOC control system which is established on the synchronous dq-RF. As shown, the PLL tracks the phase voltage angle at the PCC and generates the required frequency ωvsc and the angle θvsc for the transformation of variables between stationary abc-and dq-RFs. The dynamic equations corresponding to the VSC-WG circuit and control loops, i.e., CC, PLL, DVC, and AVC, are presented in the following subsections. It should be noted that all equations are in the frequency domain and written in the dq-RF, wherein s represents the Laplace operator. To make the equations compact, they are presented in the matrix form and dq terms are labeled with subscript "d,q" where necessary. Also, all the reference values and operating points are denoted by superscript " ref " and "°", respectively.

A. POWER CIRCUIT DYNAMIC EQUATIONS
The circuit equations relating to the ac-side of the VSC-WG system in Fig. 1(a) are given in Appendix B for compactness.

B. CONTROL DYNAMIC EQUATIONS
The dynamic equations corresponding to the VSC-WG control system are developed in dq-RF and are presented in detail in Appendix B. Fig. 2 shows the block diagrams of the CC loops as the inner control loops that are identical in dq channels. The AVC is included in the VSC control system as the outer control loop to regulate the PCC voltage at the nominal value [5], [9], [20], [30]− [33]. Fig. 3 shows the control block diagram of the PCC voltage. Also, a compensating signal ucpq is introduced to the forward loop in Fig. 3 which is discussed in Section V. The closed-loop diagram of the PLL used in this work is shown in Fig. 4. Fig. 5 shows the closed-loop block diagram of the DVC. As shown, a compensating signal denoted by ucpd is added to the forward loop which will be discussed in Section V. The details about deriving the transfer functions used in Fig. 3−5 are also presented in Appendix B.

C. CONTROL DESIGN OF THE VSC-WG SYSTEM
The bandwidth (BW) of the CC loop is usually designed to remain in the range of 10−20% of the converter switching frequency [5]. The BWs of AVC and DVC loops are also considerably slower than the CC loop. The control objectives are to design the control loops in Figs. 2−5 with high BW and small overshoots (enough damping), while the closed-loop stability of the VSC-WG system is preserved at the nominal operating point. Consequently, the controller gains are obtained as presented in Appendix A. In summary, the BWs of {529, 29, 6} Hz are assigned to the CC, DVC, and AVC loops, respectively. Also, the BW of 26 Hz is assigned to the PLL loop to give reasonably fast-tracking dynamics to the PLL when subjected to fast changes in the operating point and at the same time filter the grid low-frequency harmonics [5], [40], [41].

III. Power-Angle Limitation at Low SCR
The VSC with the LC filter can be considered as an active electronic load (AEL) as seen by the WG. Fig. 6 shows a VSC . Active electronic load connected to the WG through an equivalent series impedance.
with an LC filter in a compact form that interfaces the dc load to the ac grid. A series RL impedance g Z   is connecting the PCC bus and grid infinite bus with voltage phasors 0 g V  and o V   , respectively. Since the PCC voltage is regulated at the nominal value Vg, the steady-state expression for the transferred real power Pac according to Fig. 6 can be written as follows which shows Pac is a function of the phase angle difference δ.
According to the definition of SCR [18], the following can be written Dividing both sides of (1) by Pn and using (2) give the per-unit value of the transferred power as follows Assuming that the nominal power is transferred to the AL in Fig. 6, i.e., Pac = 1 pu, the critical SCR (SCR c ) which is defined as the smallest SCR that the system can operate under the nominal condition according to the power-angle limit, is obtained at δ = φ. Using the result in (3) gives the following which shows that SCR c depends on the XR ratio. Assuming a nonzero line resistance, XR ratio is a finite value which results in φ less than 2  . Therefore, SCR c for the VSC-WG system in the rectification mode is always more than unity according to (4). However, reversing the power to find the limit for SCR in the inversion mode, i.e., Pac = -1 pu and δ < 0, results in SCR c < 1. Consequently, unlike the study of the stability of the VSC-WG system in the inversion mode [39], the VWG condition in the rectification mode is at some SCR c which is greater than unity assuming a WG condition.

IV. Small-Signal Stability Assessment of the VSC-WG System
The state-space model of the VSC-WG system without compensation signals, i.e., ucpd,q = 0 in Figs. 3 and 5, is developed by linearizing the VSC-WG dynamic equations given in Appendix B at the nominal power level and using the parameters listed in Appendix A. The state-space model is represented in the matrix form as follows where "~" signifies a small deviation in variables, Auc is the state matrix as given in Appendix C, and  uc X is the state vector as given by A.

MODAL ANALYSIS
The nominal values of different states are obtained by solving the algebraic equations of the VSC-WG system at the nominal power operating point and under SCR = 1.18 condition. The algebraic equations can be obtained by setting s in the VSC-WG dynamic equations to zero. Then, Auc in (5) is evaluated using the parameter values provided in Appendix A. Table I summarizes the results where the relative participation of a state in an eigenvalue (mode) is evaluated using the participation factor (PF) measure [44]. As shown in Table I, the system is highly unstable due to the presence of two unstable complex eigenvalues in the lowfrequency and high-frequency ranges, λ2-3 and λ4-5, respectively. The presence of these unstable eigenvalues shows that while the VSC control loops are designed to retain stable dynamics under the nominal condition, the VOC-based VSC and WG interconnection bears highly unstable dynamics. According to the PF analysis in Table I, PLL, AVC, and DVC show strong participation in λ2-3 while λ4-5 is mostly affected by dc-side and ac network states. Moreover, ac network states have moderate participation in λ2-3. Therefore, the dynamic interaction between the VSC control dynamics and the WG impedance is the primary source of instability in the VSC-WG system. There is also real stable eigenvalue λ1 which corresponds to the PLL states and the WG states do not show any participation in it.  Fig. 7(a) for rectification mode, initially both dominant complex eigenvalues λ2-3 and λ4-5 are in the left halfplain (LHP). As Pac increases, λ4-5 have significant move towards the jω axis while λ2-3 exhibit mild movement in the same direction. Therefore, the stability of the VSC-WG system diminishes as the active power increases. Moreover, the VSC-WG system is not stable at Pac = 0.86 pu since λ4-5 enter right HP (RHP). Eventually, λ2-3 enters the RHP at Pac = 0.97 pu as well. Therefore, the VSC-WG system is unstable under the nominal condition due to the movement of two separate pairs of complex eigenvalues into the RHP. Fig. 7(b) shows the relocation of the dominant eigenvalues as a result of the same changes in the power level in the inversion mode of operation. As shown, λ4-5 relocation is limited to the LHP, while λ2-3 cross the jω axis and the system becomes unstable at Pac = 0.87 pu. This shows that first, the stability of the VSC-WG system at the nominal ac power is mostly influenced by the dominant low-frequency (range) eigenvalues and highfrequency (range) eigenvalues in the rectification mode and the inversion mode, respectively; second, the stability of the system in the inversion mode is slightly better than the  rectification mode.

2) PASSIVE DAMPING
The effect of adding a series damping resistance rd to the VSC LC filter on the dominant eigenvalues of the VSC-WG system is shown in Fig. 8. According to the figure, λ4-5, that are initially in the RHP, slightly relocate toward the jω axis and then move in the opposite direction as a function of increasing rd from zero. As shown, the system remains unstable at the nominal active power. Therefore, passive damping is not able to mitigate the VSC-WG instability problem. However, a value is assigned to rd to damp the LC filter resonance peak during light-load conditions and without extra power loss under the VWG condition as given in Appendix A.

3) PLL
The effect of changing the PLL bandwidth on the system stability is studied by changing the PLL gains (Kpω, Kiω) by a gain of 0.1 to 10. The effect of these changes on the relocation of the dominant eigenvalues is found under the nominal condition and is summarized in Fig. 9. As demonstrated, λ4-5 progress in the RHP in the unstable direction while, λ2-3, which are initially in the LHP, move towards RHP. Fig. 9 shows that λ2-3 are less affected by the changes in the control gains as compared to λ2-3. Moreover, by decreasing the PLL gains by 10 degrees of magnitude, which limits the PLL BW to 3 Hz, the VSC-WG system remains unstable at the nominal active power.

4) DC VOLTAGE CONTROL
DVC gains are changed in this part to investigate their influence on the dominant eigenvalues of the VSC-WG system at the nominal power. Fig. 10 shows the progress of the eigenvalues towards the imaginary axis as the controller gains (Kpdc, Kidc) are changed by a gain of 0.5 to 1. As shown, the complex pair λ4-5, that are initially in the LHP, approach the imaginary axis as a result of changes in the control gains until they cross the axis, where the BW of the DVC is 17 Hz. Further increase in the gains results in the relocation of the eigenvalues into the RHP. Meanwhile, λ2-3 move in the same direction as λ4-5 yet constantly in the RHP. This shows that the instability problem of the VSC-WG system exists within a wide range of variations in the BW of the DVC.

5) AC VOLTAGE CONTROL
The effect of varying the AVC gains on the dominant eigenvalues of the VSC-WG system at the nominal active power is depicted in Fig. 11. According to the figure, similar to changing DVC gains, λ4-5 are initially in the LHP. Then, by multiplying the control gains (Kpv, Kiv) by a gain of 0.08 to 1, they progress extensively towards the unstable region and enter the RHP, where the BW of the AVC is 2.5 Hz. Meanwhile, λ2-3, that initially have real form, relocate slightly until they merge and turn into a complex pair, still in the RHP, suggesting that the system remains unstable during the whole movement. Parallel to this relocation, the BW of the AVC increases from 0.5 to 5.5 Hz.   The sensitivity analysis in Section III shows that the stability of the VSC-WG system is violated at the nominal active power due to the dynamic interaction between the VSC control system and the WG impedance. The instability can be avoided only under the condition that the DVC dynamics are extremely compromised which is not desired. To mitigate this issue, a DAC scheme is proposed by which, two linear functions of the VSC output voltage are added to the AVC and DVC loops to change the distribution of the system eigenvalues in the complex plane and stabilize the system at the nominal power without compromising the system dynamics. Moreover, the system damping is increased under lower levels of power. As shown in Figs. 3 and 5 in red, the feed-forward compensators ucpd,q are added to the DVC and AVC closed-loop systems, respectively. Based on these augmentations, the equations for current references can be rewritten as The compensators ucpd,q in (7) and (8) where Kcpd, ξ, and ωcpd are the gain, damping ratio, and center frequency of the band-pass filter (BPF) corresponding to ucpd; and Kcpq and ωcpq are the (dc) gain and cut-off frequency of the low-pass filter (LPF) corresponding to ucpq. Based on the PFs of dc v  and c od v  in the dominant eigenvalues of the VSC-WG system as given by Table I, the BPF in (9) is selected to affect the unstable modes corresponding to eigenvalues λ4-5 in the high-frequency range without any undesired effect on other frequency ranges. Moreover, the LPF in (10) is selected to affect the unstable modes corresponding to the low-frequency range dominant eigenvalues λ2-3. Since vod is constant and voq is zero in the steady state, the compensators have zero effects on the steady-state operation of the VSC according to (9) and (10).

A. LINEAR MODEL OF THE COMPENSATED VSC-WG SYSTEM
The VSC-WG with the DAC is linearized in this part similar to the uncompensated model in Section IV using the same dynamic equations with the exception of considering nonzero compensation signals as given in (7) and (8). The linearized model of the compensated VSC-WG system is presented as follows where the state matrix Acp is shown in Appendix C and the states vector  cp X is given as where xcpd1-2 and xcpq, are the new state variables that are introduced by the BPF and LPF in (9) and (10).

B. DESIGN AND ANALYSIS OF DAC COMPENSATION
The DAC compensators presented in (9) and (10) are three and two degrees of freedom controllers, respectively. The root locus method is used to find the optimum values of the DAC parameters using the state-space model of the compensated VSC-WG system as given in (11). The effect of changing different DAC parameters on the dominant eigenvalues of the VSC-WG system is obtained at the nominal power under SCR  Fig.12(a) shows the migration of λ4-5 as a function of the increase in the BPF gain Kcpd at ωcpd = {300, 600, 900} rad/s while the ucpq compensator is disabled by setting Kcpq to zero. As shown, λ4-5, that are initially located in the RHP, move towards the jω axis as Kcpd increases. Moreover, the compensation effectiveness can be boosted by taking larger values of ωcpd. As shown, at ωcpd = {600, 900} rad/s, λ4-5 enter the stable region (LHP). According to Fig. 12(a), the optimum frequency at which ucpq applies maximum damping to the overall system dynamics is ωcpd = 600 rad/s. According to the figure, the effect of increasing Kcpd on the system damping is twofold. On one hand, λ4-5 move in the direction of increasing the system stability, on the other hand, λ6-7 move in the opposite direction decreasing the system stability. Therefore, a trade-off is considered to find the optimum value for Kcpd where the resulting value is given in Appendix A. Moreover, increasing the damping ratio ξ has a mild positive effect on the system damping (not shown in Fig. 12). Unlike λ4-5, the lowfrequency range eigenvalues λ2-3 are not affected by ucpq compensator and remain in the unstable region (RHP). Fig.12(b) shows the migration of λ2-3 as a function of the increases in the ucpq compensator gain Kcpq at ωcpq = {5, 10, 15} rad/s while the ucpd compensator is enabled with the optimum parameters (ωcpd = 600 Hz and Kcpd = 3.5). As shown, λ2-3, that are initially in the RHP, relocate and move towards the imaginary axis and enter the stable region. According to Fig. 12(b), the maximum improvement in the system stability is reached at ωcpq = 10 rad/s and the optimum value of Kcpd is found at 225 where the dominant modes have the maximum damping. It should be noted that due to the frequency-scale separation between the BPF and LPF, the ucpd and ucpq dynamics are decoupled. Therefore, the DAC compensators ucpd,q can be designed independently. Moreover, the DAC can dynamically mitigate the unstable oscillations in both low-frequency and high-frequency ranges without any unwanted cross-coupling. Fig. 13 shows the trajectory of the dominant eigenvalues of the VSC-WG system with the proposed DAC compensation subject to the increase of Pac from 0.85 to 1 pu. As shown, λ4-5 progress towards the imaginary axis, similar to the uncompensated system in Fig. 7, nevertheless, constantly in the LHP. Moreover, λ2-3, follow the same pattern as λ4-5 in the stable region but with a slower rate. Fig. 13, shows that the proposed DAC compensation improves the VSC-WG system stability for a wider range of active power (up to 1 pu) in the rectification mode as compared to the uncompensated system under the VWG condition. Fig. 14 shows the progress of the dominant eigenvalues subject to changes in SCR from 1.5 to 1.1, which corresponds to the SCR c level in (4) and the XR ratio given in Appendix A. As shown in Fig. 14(a), λ4-5 move towards the imaginary axis and cross it at SCR = 1.39 as the SCR is decreased by increasing the grid impedance Zg. According to Fig. 14(b), the dominant modes λ4-5 follow a similar trend but cross the imaginary axis at SCR = 1.16. Therefore, the DAC scheme extends the stability margin of the VSC-WG to a closer vicinity of the theoretical limit as compared to the uncompensated system.

VI. Simulation Results
A series of time-domain simulations are carried out on the nonlinear model of VSC-WG system to verify the results that are obtained based on the small-signal model that is developed in the previous sections. The VSC-WG shown in Fig. 1 is built in MATLAB/Simulink environment based on the system specifications that are provided in Appendix A. The average model of the VSC is used for the purpose of dynamic simulation [5].

A. RESPONSE TO ACTIVE POWER STEP-UP
The active power response of the VSC-WG system subject to the sequential power steps at different power levels is summarized in Fig. 15. A small step change is applied to the input of the VSC dc-side current source Idc at t = 0.1 s at different power levels. As shown in Figs. 15(a)−(b), the responses of the VSC active power with and without DAC are very close up to Pac = 0.85 pu. At higher power levels, the responses tend to diverge. As shown in Fig. 15(c), the unstable oscillatory behavior is visible in the uncompensated system response Pac is close to 0.85 pu while the response of the compensated system exhibits well-damped stable dynamics at the same power level. These oscillations relate to the relocation of λ4-5 to the RHP with the change in the power as observed in Fig. 7(a). Note that the period of the oscillations is 4 ms which closely matches the frequency of the corresponding eigenvalues λ4-5, i.e., 1494 Hz, as they cross the  imaginary axis in Fig. 7(a). More importantly, the VSC-WG system with enabled DAC demonstrates stable responses under the full range of the active power injection as shown in Figs. 15(a)−(d).

B. RESPONSE TO GRID ANGLE CHANGE
Another perk of using the proposed DAC scheme is the enhancement in the robustness of the VSC-WG system against the grid angle variations. Fig. 16 shows the VSC-WG responses where a 10-degree step disturbance happens in the grid voltage angle θg at the infinite ac bus at t = 0.5 s and is cleared in t = 1 s while the VSC-WG active power is Pac = 0.85 pu. The power response of the compensated system is shown in Fig. 16(a) in blue. As shown, Pac undergoes an undershoot and overshoot of about 0.03 and 0.01 pu at t = 0.5 and 1 s, respectively, yet the VSC controller manages to regulate the injected power at the nominal value. As shown in Fig. 16(b), there are overshoots and undershoots of 10 degrees in the VSC angle difference response δ following the changes in the grid angle. The VSC PLL tracks the actual PCC angle and quickly updates the VSC angle. Since the VSC-WG active power is not changing, the value of δ returns to the same value right after changes. Moreover, the VSC-WG system stability is well preserved. The same condition is applied to the uncompensated VSC-WG system. As shown in Fig 16 with the dotted red line, the uncompensated system fails to track the deviations in the angle. Therefore, the VSC-WG does not reach a stable operating point.

C. RESPONSE TO GRID IMPEDANCE VARIATION
The grid equivalent impedance depends on the power flow especially in grid-connected microgrids where several DGs with plug-and-play capability are accommodated. Moreover, the disconnection of lines in the case of fault occurrence imposes a rapid change in the grid impedance. Therefore, the WG impedance is considered time-varying [9], [34], [42], [43]. Fig. 17 shows the responses of the VSC-WG system to the increase in the grid impedance Zg. Since the rate of the change in the grid impedance is not a priori assumption, the simulation is repeated for two periods of 0.33 s and 1 s which represent fast and slow changes in the WG impedance, respectively. The system is initially in the steady-state stable condition at SCR = 1.5. Then, at t = 0.5 s, Zg increases linearly from 0.8 pu to 1 pu and SCR decreases from 1.5 to 1 consequently while the VSC active power is at the nominal value. In the meantime, according to Fig. 17(a), Qac increases to compensate for the reactive power absorbed by the WG reactance and maintain the so-called voltage stability [43]. As shown in Fig. 17(b), δ increases as the grid reactance increases which is justified according to (1) knowing that the VSC-WG active power is not changing. There are overshoots and undershoots in the system responses during the fast-rate changes in the grid impedance. However, the stable operation of the system is maintained during both rates of change. According to Fig. 17, the stability of the VSC-WG system with DAC enabled is guaranteed under a wide range of fast and slow-rate changes in the grid impedance.

D. INTERACTION BETWEEN DAC AND VOC
The dynamic interactions of the proposed compensation method with the primary controllers of the VSC-WG control system are investigated at Pac = 0.85 pu, where the system is naturally stable without the active compensation. Fig. 18(a) shows the frequency tracking responses of the PLL subject to a 1 Hz step in the frequency of the grid at t = 0.5 s. Visibly, the DAC has an insignificant effect on the ωvsc response and hence on the PLL dynamics. Fig. 18(b) shows the responses of ifd following a 5% step in the current reference at t = 0.5 s. As shown, the proposed DAC scheme manages to substantially decrease the overshoots and suppress the oscillations. Fig  18(c) shows the variations in the magnitude of the PCC voltage |vo| following a 5% step change at t = 0.5 s. As shown, the proposed DAC scheme suppresses the oscillations in the uncompensated response without making the response sluggish. The variation of the dc voltage response vdc is shown in Fig. 18(d). As shown, when the reference increases by 1% at t = 0.5 s, the compensated system exhibits a much more damped response with smaller over/undershoots as compared to the uncompensated system. Also, the system response speed is not compromised. Therefore, the outer control loop dynamics are not negatively affected by the introduction of the DAC feedforwards while benefiting from the compensators where the undesired oscillations are attenuated.

VII. HIL REAL-TIME VERIFICATION
To verify the simulation results about the effectiveness of the proposed DAC scheme in improving the VSC-WG stability in the rectification mode, the VSC-WG system in Fig. 1 is developed in the hardware-in-the-loop (HIL) system assuming the switched-model of the VSC as shown in Fig. 19. The HIL system essentially includes MT 6020 as an FPGA-based realtime circuit simulator and NI-PXIe-7868R CPU on which the VSC-WG controller is developed as shown in Fig. 19. Two I/O interface boxes are used to allow the physical connection between the circuit simulator and the controller. The emulated VSC-WG and the DAC parameter specifications follow the same values given in Appendix A. The time-step of the realtime simulation is 1 μs while the controller is running at 50 μs sampling time.
A series of tests are performed during which the VSC-WG active power is increased with a staircase profile Pac = [0.4,  Fig. 20 shows the responses of the VSC-WG system without DAC compensation. As shown in Fig. 20(a), vo is regulated at 1 pu during the period t = [0, 6) s due to the AVC action. As shown in Fig. 20, io increases after each step in the dc power and reaches a new steady-state point each time due to the CC action to maintain the power balance between the dc and acsides of the VSC. The difference of the dc-side voltage from the reference value (dc-side voltage error) ∆vdc is depicted in Fig. 20. According to Fig. 20, VSC-WG system operation is stable during the period t = [0, 6) s. However, with further increases in the Pac at t = 6 s, the ∆vdc response shows undamped oscillations as shown in the zoom window superimposed on Fig. 20. As shown, the VSC-WG system is unstable at Pac = 0.88 pu which agrees with the small-signal result in Fig. 7(a) where λ4-5 are in the unstable region at the same power level. Moreover, the unstable oscillations are more pronounced in the ∆vdc response as compared to the other responses in Fig. 20 since vdc has the largest participation in  the eigenmode related to λ4-5 according to Table I. Similar series of tests are repeated for the VSC-WG system with DAC enabled. The active power profile is given as Pac = [0.6, 0.8, 0.9, 0.95, 0.97, 0.99, 1] pu with the increases in Idc at t = [1.5, 3, 4, 5, 6, 7, 8] s. Fig. 21(a) shows the experimental results. As shown, the system is stable and the vo, io, and ∆vdc responses are well-damped and regulated in the steady state during the period t = [0, 9] s. The undershoots in the ∆vdc response in Fig. 21(a) is less than 0.2 during the start-up and at the beginning of each step. Despite them, the VSC-WG system is stable at the nominal active power under the VWG condition. Fig. 21(b) shows a closer view of the VSC-WG responses in the steady-state under the nominal condition where the switching ripple content is pronounced for ac and dc-side voltages. Due to the filtering effect of the WG large inductance, the VSC output current is almost ripple-free as shown in Fig. 21(b). It should be noted that the total harmonic distortion of vo in Fig. 21(b) is smaller than 5% which complies with the IEEE standard 519 [45]. As shown in Fig.  21(b), the switching ripples are translated into the dc-side response ∆vdc as well. Yet, their content is negligible as compared to the average value of vdc which is regulated at the nominal value by the DVC. response of Pac around t = 7 s, as magnified by the zoom window in Fig. 22(a), and the response of the average model in Fig. 15(d) closely matches. This verifies the development of the small-signal model in Section V. Fig. 22(b) shows the angle difference response δ. Initially, δ is close to zero since the VSC active power is zero. By increasing Pac and noting the output voltage is regulated at 1 pu, δ increases once the power increases according to (1). Fig. 22(c) shows the variations in the DAC signals ucpd,q. As shown in Fig. 22(c), the compensation signals are activated during the transient conditions while they have zero impact on the system in the steady state. Moreover, due to the frequency separation of the LPF and BPF function, ucpd,q responses are visibly separable in terms of dynamic response.

VIII. CONCLUSION
Throughout this work, the integration of VSCs into the VWG systems has been investigated. The instabilities associated with the dynamic interaction between the VOC-based VSC in the rectification mode and the grid impedance have been mitigated effectively using the proposed DAC scheme under the VWG condition. The DAC scheme includes the injection of modified versions of the PCC voltage into the dq current references of the CC loops. It is shown that the proposed DAC scheme contributes successfully to the relocation of the eigenvalues on the complex plane from the unstable region to more damped locations in the stable region. In addition to the stabilization of the VSC-WG system under the VWG conditions, the stability/robustness of the system subject to the grid angle deviations has been improved with the proposed DAC. The effectiveness of the proposed DAC has been validated analytically using the small-signal analysis and numerically using the large-signal nonlinear model of the VSC-WG system which is developed in MATLAB/SIMULINK and then tested in real time using a HIL experimental set-up. The proposed DAC has the following features: (1) it is simple and can be easily designed using the linear control tools, (2) it does not impact the steadystate condition of the VSC-WG system, (3) it has a minimal influence on the existing VOC system of the VSC and so it can be designed independently, (4) it requires no extra sensors for practical implementation. Time-domain simulations and experiments of the VSC-WG system are carried out to verify (1), the stability of the VSC-WG system with the proposed DAC scheme under VWG condition, (2) the improved damping property of the compensated VSC-WG system, (3) the enhanced capability of the VSC-WG system to withstand sudden grid angle deviations and wide range of variations in the grid impedance.

APPENDIX A
Parameters of the VSC-WG system are provided in Table II.

B. CURRENT CONTROL
A pair of similar proportional-and-integral (PI) compensators Gs(s) = Kpc + Kics -1 , regulates ifd,q to follow the reference values ifd,q ref . The voltage feedforwards and decoupling current terms are introduced to the forward paths in Fig. 2 to decouple the dq CC dynamics and cancel the effect of disturbance inputs vod,q when plugged into (A1) [5]. The expressions for the control inputs ud,q according to Fig. 2 As shown in Fig. 2 If the PWM dynamics are neglected and the VSC averaged model [5]  As shown in Fig. 3, a negative gain is added to the forward path to cancel the negative sign of Tiv ac (s) in (A11). A more accurate treatment for obtaining the ac transfer function without ignoring the frequency deviations is presented in [39].

D. DQ-FRAME SYNCHRONISATION
As shown in Fig. 4, a conventional PLL system is used to track the angle of the PCC phase voltage. This is done by employing a PI controller Gpll(s) = Kpω + Kiωs -1 that regulates the q component of the voltage voq to zero. Therefore, the following can be derived for the PLL dynamics where ωvsc and θvsc are, the VSC frequency and phase angle generated by the PLL, respectively; ωg and θg are the frequency and the phase angle of the grid voltage source, respectively; and δ = θg − θvsc is the phase angle difference.

E. DC VOLTAGE CONTROL
The dc-side voltage error edc = vdc ref −vdc passes through a PI compensator Gdc(s) = Kpdc + Kidcs -1 and the result is used as a reference for the d channel of the CC. Therefore, the following relation between edc and ifd ref exists The VSC dc-side power Pdc is equal to the sum of the instantaneous active power at the VSC terminals and in the dc filter capacitor Cdc neglecting the switching loss in the VSC. The dc transfer function from ifd to vdc, denoted by Tiv dc (s), is obtained as follows. First, the following expression is derived based on instantaneous power equilibrium [5]