P-type Cu2O Thin Film Transistors for Active Matrix Displays: Physical Modeling and Numerical Simulation

In this paper, we present the physical modeling and numerical simulations of p-type Cu2O TFT for the design and development of active matrix displays. In Cu2O, the carrier transport is through copper and oxygen vacancies (VCu and VO) which are prominent defects due to their low formation energies. These defects were modeled with acceptor-like and donor-like Gaussian states. From the simulations, it was observed that the VCu significantly controls the OFF current and threshold voltage (Vth), while VO degrades the ON current. For the analysis of device stability, both positive and negative bias stress (PBS and NBS) on Cu2O TFT was investigated with dielectric/channel interface traps in simulations. Under NBS, a significant negative shift in the Vth was observed due to hole trapping from channel to dielectrics. On the contrary, during PBS, a small shift in Vth was observed with significant degradation in sub-threshold swing (SS) due to the deficiency of free electron and the presence of additional defects generated in Cu2O channel as stress time increase. In addition to this effect of increase in Cu2O channel thickness were studied where a significant amount of shift in Vth from -7.1 V to -6.1 V was observed as the thickness increased from 45 nm to 65 nm. Finally, the dynamic performance of Cu2O was evaluated and found to be better for higher channel thickness in terms of holding of the output voltage. From these observations, the p-type Cu2O TFT shall be considered for the stable and efficient pixel circuit of active matrix displays such as AMLCD.


I. INTRODUCTION
High resolution flat panel displays such as 8K×4K with high pixel density (7680×4320 pixels) require high refresh rates up to 120 Hz [1]. To achieve this, transient response based thin film transistor (TFT) technology with fast refresh is needed, which can help the pixel capacitor to charge in a short time. There are several reports available on amorphous hydrogenated silicon (a-Si:H) based TFT, where considerable work was done on the transient response. However, they are not efficient at providing high refresh rates due to their low effective-field mobility (µ F E ), and high subthreshold swing (SS).
In recent times, oxide semiconductors (OS) have been highly preferred over a-Si:H TFT technology due to their low temperature and good uniformity over large area, which also support flexible displays. Amorphous Indium Gallium Zinc oxide (a-IGZO) TFTs has gained enormous recognition for its high µ F E (> 10 cm 2 V −1 s −1 ), large band gap (∼ 3.2 eV), and low SS (~0.1 V/dec) [2]. These attractive properties help to reach the required refresh rates for driving high resolution displays. However, it has few limitations, such as high fabrication cost due to the low abundance of indium (∼2 ppm by mass of earth's crust). Also, p-type conduction in a-IGZO is not possible due to its valence band (VB) structure which consists of oxygen 2p orbitals. These orbitals localize the hole carriers, resulting in high effective mass. TFT technology, efficient and fast switching p-type TFTs are required with excellent electrical performance, compatible to n-type TFTs. Few metal OSs show native p-type characteristics, such as cuprous oxide (Cu 2 O) and tin monoxide (SnO). Based on the findings by Kawazoe et al., cuprous oxide (Cu 2 O) was found to be a potential candidate for p-type TFTs [5]. It shows a high Hall mobility of > 100 cm 2 V −1 s −1 [6]. This is due to the hybridization of Cu 3d orbitals and O 2p orbitals, resulting in the dispersion of valence band (VB) states. This weakens the localization of holes, which consequently improves the hole mobility. Since, Cu 2 O is abundant in nature, its fabrication cost is also low. Several articles were reported on the deposition of Cu 2 O thin films, which show that it exhibits p-type conduction due to negatively charged Cu vacancies (V Cu ) and shows a direct band gap of~2 eV [7] [8]. Zou et al., reported the fabrication of Cu 2 O TFT, where the channel was deposited through pulse laser deposition [9]. It shows a good effective mobility of 2.7 cm 2 V −1 s −1 with high ON/OFF current ratio of 1.5×10 6 and low SS of 137 mV/dec. Similarly, Chang et al., achieved a similar TFT performance through defect elimination techniques, such as Sulphur treatment [10]. In view of flexible TFTs, a room temperature (RT) fabrication of Cu 2 O TFT was demonstrated by Yao et al., where a polyethylene terephthalate (PET) substrate was used [11].
Though, many articles reported the fabrication and characterization of Cu 2 O TFTs [12], [13], carrier transport through various defects of copper-oxide systems is rarely reported. Jeong et al., studied the carrier transport mechanism of Cu 2 O through the calculation of the density of VB tail states via bias and temperature dependent drain currents [14]. However, they have not explained the effects of Cu-vacancies (V Cu ) and O-vacancies (V O ) on the performance of TFTs and circuits. Early reports on modeling the carrier transport of amorphous semiconductors account only tail states [15]. Later, Davis et al., added donor/acceptor sub-gap states in the model [16]. The model further expanded to include both donor and acceptor sub-gap and tail states and demonstrated in numerical simulation of TFTs [2], [17]. The modern density of states (DOS) model has flexibility to define the electronic states of defects with respect to valence band maximum (VBM) or conduction band minimum (CBM). Also, the tail and sub-gap states can be described with realistic exponential and Gaussian distributions for accurate simulations.
In this paper, we present the numerical simulation of Cu 2 O TFTs using density-of states (DOS) model. First, the defects and disorders of the Cu-oxide system are reviewed and DOS model of Cu 2 O is presented in section II. Numerical simulation of Cu 2 O TFTs for various thickness and fitting with measured results are presented in section III. Along with DC characteristics, the bias stress test are investigated for various stress times and presented in section III. Finally, in section IV, we have presented the evaluation of the dynamic performance of Cu 2 O TFT pixel circuit for high resolution displays.

II. DOS MODEL FOR CU2O
Cu 2 O has a simple cubic structure with lattice parameter a = 4.2696 Oxygen atoms are organized in a body centered cubic (BCC) sub lattice, where as copper atoms are formed in a face centered cubic (FCC) sub lattice [18] as shown in fig.  1 (a). In general, based on the stoichiometry, copper oxide has two stable phases, i.e. Cu 2 O and cupric oxides (CuO). Apart from this, it has one more phase called paramelaconite Usually, achieving p-type conduction in OS is very difficult due to the localization of the hole carrier by the O 2p orbital. However, in Cu 2 O, the localization effect is less due to the hybridization between the Cu 3d and O 2p orbitals. Moreover, as shown in fig. 1 (a) defects in Cu 2 O such as copper vacancies (V Cu ) generate excess holes, which lead to p-type conduction [19], [20]. It has relatively shallow transition level e(0/ − 1), positioned just above the VB edge (E V +0.28eV ) [7]. Based on several literature, the concentration of V Cu varies between 10 16 -10 18 cm −3 [21], [22]. These metal vacancies directly affect the density of states of the oxide system, which are mathematically modeled to perform realistic simulations. The density of states (DOS) model consists of exponentially-decaying band-tail states and deep-gap (Gaussian) states, which are often associated with disorders and defects in oxide semiconductors, respectively. Disorders in OS are related to variation in the bond lengths, bond angles and coordination numbers where as defects are due to cation/anion vacancies or interstitial. These states are of two types i.e., localized acceptor-like and donor-like states. Accordingly, these localized acceptor and donor-like bandtail are present near CB and VB, where as acceptor and donor-like Gaussian states are at lower half and upper half of the forbidden band gap. Now, the total DOS is given by the sum of both exponential decaying band tail states (a donor-like, G T D (E) and acceptor-like, G T A (E)) and Gaussian distribution (donor-like, G GD (E) and acceptorlike, G GA (E)) of sub-gap states, i.e.
Here E is defined as trap energy. g T A (E) (cm −3 eV −1 ) and g T D (E) (cm −3 eV −1 ) at E = E C and E = E V are band edge densities at CB and VB respectively. There characteristic slopes are given by U T A and U T D . Similarly, Gaussian distribution, with peak densities of g GA (E) and g GD (E) for acceptor-like and donor-like traps at trap energies E = E GA and E = E GD respectively. Their slopes are represented by characteristic decay energies U GA and U GD .

III. SIMULATION OF P-TYPE CU2O TFT A. DC CHARACTERISTICS
The numerical simulation, using TCAD Silvaco [23], was carried out for the staggered bottom gate TFT shown in the Fig. 2 (c) inset. Based on the boundary condition, the simulation tool solves the Poisson, continuity, and charge transport equations which are coupled together. Apart from this, the numerical simulation also considers other models such as Fermi-Dirac model, field-dependent mobility model VOLUME 4, 2016 and defect model etc. These models are applied to the channel layer of the TFT. In addition to this, necessary boundary conditions are also applied to regulate the carrier movement between source and drain contacts along with thermionic and tunneling models.
To validate the physical modeling of Cu 2 O TFTs, we have considered the experimental work of Nam et al [8]. From the bottom, a p-type (heavily doped) silicon substrate was used as the gate electrode. Thereafter, a 100 nm thick silicon dioxide (SiO 2 ) dielectric was thermally grown on the top of the substrate. Using RF magnetron sputtering, Cu 2 O thin film of thickness 45 nm was deposited with subsequent annealing for 7 min at 500 0 C . For source and drain contacts, nickel (Ni) was deposited using the evaporation method and the latter patterned with a channel length and width of 100 and 1000 µm respectively.
For the simulation and fitting of Cu 2 O TFT, electronic properties such as hole band mobility (µ P =47.5 cm 2 /V.s) [8], and electron and hole effective mass (m C = 0.98m 0 and m V = 0.66m 0 ) [24] are considered. Table 1 shows the parameters used for the simulation of Cu 2 O TFT. Few DOS parameters greatly affect the transfer characteristics of TFTs during simulation, such as g GA and U T D . These parameters are taken into account based on the earlier conclusions drawn from our early works [25], [26]. It is believed that cation vacancies with low formation energies are responsible for p-type conduction. This was justified by Raebiger et al., in first principle study of Cu 2 O. It concludes that p-type conduction originates from copper vacancies (V Cu ), which are acceptor-like defects and found just above the VBM. Thus, based on the above facts, V Cu was associated to g GA . Fig. 2 (a) illustrates the impact of the change in g GA on the I-V characteristics. There is an increase in the OFF current as g GA increases. This signifies that, more hole carrier transport is taking place between source and drain through the channel which makes the TFT in depletion mode. Apart from the OFF current, V th also shifted towards the positive x-axis. Despite of this, the variation in ON current is minimal. VBM of Cu 2 O consists of O 2p orbitals. These orbitals are sensitive to direction dependent disorders [27], [28]. Due to this, the characteristic slope of tails state near VB is always larger than that of CB. To understand this effect we have changed the U T D value as shown in Fig. 2 (b). We can observe that, higher U T D value can degrade the drain current performance. To clarify this anomaly, at the interface (SiO 2 /Cu 2 O), band bending due to U T D was examined with the help of a probe. The Fermi energy, E F relative to the VB edge (E F − E V ) was plotted with respect to V GS for different U T D . As shown in Fig. 2 (c), for large values of U T D , E F is moving far away from VBM. This explains the reason for the degradation of drain current. In Cu 2 O, there are other defects which contribute to the conduction mechanism. These are oxygen vacancies (V O ) and copper interstitial (Cu i ). However, V O predominately affects the drain current due to its low formation energy in comparison with Cu i . It is a donor-like defect, since it donates electrons. This is explained by another DOS parameter, g GD . Fig. 2 (d) shows that a higher value of g GD can greatly affect the ON current of the TFT. The simulation values used in g GA and g GD are quite comparable with the literature [7]. A detailed overview of Cu 2 O defects with respect to their formation energy and their associations to DOS parameters, defect density is shown in Fig. 1 (a) and (b) respectively.
The simulation was further applied to Cu 2 O TFT with a 65 nm channel thickness. Fig. 3 (a) and (b) shows the I-V fitting the measured data [8] and extracted DOS. Lee et al., investigated the a-IGZO TFT for various channel thicknesses such as 30 nm, 50 nm, and 85 nm through DOS [29]. It was observed that, a 30 nm thick channel has less number of carrier concentration as compared to an 85 nm thick channel. This indicates the presence of less number of traps (acceptorlike tail states) in the 85 nm channel than 30 nm thick channel. As a result, there is a decrease in the V th requirement to turn ON the TFT. A similar behavior was observed in Cu 2 O TFT as the channel thickness increased from 45 nm to 65 nm. As a result, V th has decreased from -7.1 V to -6.1 V. To capture this mechanism, donor-like tail states, g T D were reduced from 1 × 10 21 to 9 × 10 20 cm −3 eV −1 . Figure 3 (c) shows the overlay of tail states from measured Cu 2 O TFT (40 nm thick channel) [14] and simulated Cu 2 O TFT (45 nm and 65 nm thick channel). This significant fit proves that the DOS model for Cu2O is realistic and gives physical insight into the defects and disorders present in Cu 2 O. Key DOS parameters and overall TFT performance are presented in Table 1 and 2 respectively. Recently, few studies on nano crystalline Cu 2 O show the presence of grain boundary (GB) which largely affect the film resistivity [30]. One shall incorporate the effect of GB in DOS model and field effect mobility model to achieve realistic simulation of TFTs

B. BIAS-STRESS-INDUCED INSTABILITIES
Biasing of the gate terminal over a prolonged time period will result change in the electrical performance of TFTs, which is often referred to bias stress instability. Most significantly, the variations in threshold voltage (V th ) and sub-threshold swing (SS) of transfer characteristics are the common effects. Based on the survey from several literature, it was found that the variation in electrical characteristics of TFTs in the back-panel due to bias stress leads to nonuniform pixel brightness in display technologies, such as AMLCDs, and AMOLEDs [31]- [33]. For instance, a shift of 0.1 V in V th of a TFT in the back-panel of AMOLED display shall reduce about 20% brightness [34]. In this regard, few studies on the characterization of positive and negative bias stress (PBS and NBS) instabilities have been reported in recent times on various oxide semiconductors, such as n-type InGaZnO [32], n-type SnO 2 [35], p-type SnO [36] and p-type Cu 2 O [37].
In this section, similar to the simulation of DC characteristics, we have presented the investigation on the origin of bias stress instability in Cu 2 O TFT. Recently, Park et al., have examined the bias stress instability in Cu 2 O TFT experimentally [37]. In both negative bias stress and positive bias stress tests, variation in the transfer characteristics was observed. This is due to two major phenomena; (1) The trapping of hole carriers at the channel/dielectric interface [38], [39], (2) The formation of extra defects states in the subgap states at the channel/active region [40], [41]. In this regard, the interface trap model is used to describe the time domain emission and capture process of electron/hole from an acceptor/donor trap at the insulator/semiconductor interface, independently reported by F. P Heiman et al [42] and D. Ielmini et al [43]. In this model, the carrier capture rate defines the recombination rate of the transient current continuity equation, with structural relaxation of hole traps in the insulator. To incorporate this model, a uniform distribution of interface charges at a density of Q it , about a depth (d) in the insulator from the interface is included. The capture rates are computed using carrier cross-sections of carriers for electrons (σ n0 ) and holes (σ p0 ) with respect to the quasi-Fermi level is defined as: where are the evanescent wave-vectors corresponds to electron and holes. The activation energy levels E tA and E tD are for acceptor-like and donor-like trap respectively, these values are presented in Guillen et al., [44]. Here, is modified Planks constant and m e,h are the effective mass of electrons and holes respectively. It is common approach in TCAD simulators to choose the maximum trap depth d = 5 nm [23]. To compare the results of bias stress simulations, measured NBS and PBS transfer characteristics of Park et al., are taken [37]. Numerical transient simulations of NBS and PBS were performed for Cu 2 O TFTs for various stress times from 0 to 2 × 10 4 s, for the sweep of gate voltage from 10 to -30 V at regular intervals, to meet the experimental results. Fig. 4 (a) and (b) show the simulated NBS and PBS transfer characteristics of Cu 2 O TFT, respectively, for gate bias for the applied stress time of 0 to 2 × 10 4 s, along with the measured results [37]. For NBS at V GS−Stress = -25 V, the Q it is increased to fit the measured results for 0 and 2×10 4 s, corresponding to before and after stress conditions. The DOS parameters of the channel were not changed. Table-3   for the best fit for both before and after stress conditions. From Fig. 4 (a), it was observed that, as the duration of stress time increases, the transfer characteristics of TFT shift to the negative V GS . This shift is computed by change in magnitude of threshold voltage (|∆V th |), presented in Fig. 4 (c). A close fit was observed between measured and simulated data. The negative V th increases with increasing Q it , which explains the transfer of holes from the Cu 2 O channel to the interface. On the other hand, there is no significant change in SS, which shows that the channel is less influenced by NBS. Similar observations were reported for a-IGZO TFTs [45]. Fig. 4 (b) shows the compatibility of simulated and measured PBS results for V GS−Stress = 25 V. It was observed that, as the stress time increases, a notable increase in the SS was observed while the maximum shift in V th is less than 3 V. Based on the observation from Park et al., [37], there could be a shortage of free electrons in the Cu 2 O channel due to PBS. This shows that the DOS of the channel, near the channel/dielectric interface, is disturbed due to electrical stress. In order to model this phenomenon, few DOS parameters need to be tweaked to fit the experimental results. For the shortage of free electrons in channel, that is oxygen vacancies (V O ), g GD was parametrically reduced to have a best fit. It was found that a reduction of two orders in g GD results a significant fit. Also, to introduce hole traps near the channel/dielectric interface, acceptor-like Gaussian states (g GA ) were increased from 6.5 × 10 20 to 9 × 10 20 /cm 3 eV. These changes in DOS resulted in a good fit between simulated and measured Cu 2 O TFTs for both with stress (time = 20000 s) and without stress, refer Fig. 4 (b). For various stress times, the |∆V th | was extracted from simulation and measured transfer characteristics of Ref. [37], found an excellent fit. Compare to NBS, the PBS shows a small shift of V th . This indicates the back-channel was not strongly depleted due to low absorption of O 2 during electrical stress and the low carrier concentration at CB of Cu 2 O. On the other hand, SnO TFT shows a large shift in V th during electrical stress when the back-channel is exposed to air medium [36]. Therefore, Cu 2 O TFTs show better stress stability compared to p-type SnO TFTs.

IV. PERFORMANCE OF PIXEL CIRCUIT WITH P-TYPE CU2O TFT
Ultra-high definition (UHD) display technologies, with resolutions of 4K and 8K pixel densities, require refresh rates of up to 120 Hz to avoid image flickering. This requires pixels to charge within a recommended charge time margin (t cm ). These issues are often addressed by transient characterization of TFTs. Based on the article reported by Kaneko et al., 1 × 10 11 6.9 × 10 11 -g GA (cm −3 eV −1 ) ----6.5 × 10 20 9 × 10 20 g GD (cm −3 eV −1 ) ----4 × 10 17 4 × 10 15 image flickering results from the variation in the feed through voltage ( V p ). This V p is due to the overlapping of gatesource capacitance (C GS ) [46]. Lee et al., have studied the details of V p and t cm in dynamic response of a-Si:H TFTs [47]. In recent times, Yu et al., reported dynamic studies of IGZO based TFTs for high resolution display requirements [48]. Based on the studies, IGZO TFT was found to be more stable and responsive over a-Si:H TFTs. The reasons for this improvement in IGZO TFT are the high mobility of IGZO (9.1 cm 2 V −1 s −1 ) and low SS of < 130 mV/dec.
Although several reports on dynamic characterization studies are available in ntype TFTs, very few reports are available for p-type TFTs [26], [49]. Considering the electrical performance and requirements of pixel circuits, in this report, we have presented the characterization of the dynamic response of p-type Cu 2 O TFTs for 45 and 65 nm channel thickness. To study the charging and holding process of the pixel circuit, a mixed-mode simulation of the following pixel circuit was performed. A simple pixel configuration of one Cu 2 O TFT (T 1 ) and one storage capacitor (C ST ) is considered for this work, depicted in Fig. 5 (a). Driving control and data signals of pixel circuit is given as follows: In each frame, a fixed DRAIN pulse with a voltage high of V DH is applied at the drain bus to start the charging process. The pulse reaches low DRAIN voltage V DL to reset the frame the pixel. Fig. 5 (b) shows the DRAIN and GATE signals. The charging time margin t cm is calculated by [50], where the frame rate F R and the number of row-lines N RL are specified by the UHD technology. For full HD and 4K displays, t cm is 16 and 8 µs respectively [51]. The set/reset period t set is calculated from t cm of the GATE pulse. Often, t set = 3 × t cm is assumed while the GATE pulse arrives at 1 × t cm just after the rise of the set/reset pulse. Positive and negative edge times (t r and t f ) of GATE pulse shall vary between 1 to 100 ns. The choice of t r and t f significantly influences the voltage holding process of storage capacitor. In displays, the delays in GATE and DRAIN lines due to RC parasitic are often affect the requirements of t cm and t set . Yet, these effects are not considering to evaluate the performance of Cu 2 O TFT based pixel circuit.
Simulation of the transient response of a pixel circuit with oxide semiconductor TFTs for various time margins is demonstrated using the mixed-mode platform in the Atlas of TCAD Silvaco. In these simulations, physical models of TFTs such as Fermi-Dirac and defect models, are considered for steady-state analysis, which is initiated with the twostage Newton method [23]. On the other hand, the positive and negative of GATE and DRAIN pulses ramped on an exponential scale to bypass the convergence issues at the time of numerical simulation. Considering the fact, the t r and t f are taken as 10 ns with minimum time-step of 1 ns. In all transient analysis, the GATE pulse amplitude for set and reset is fixed as V GH = −20 V and V GL = 0 V respectively. During the set and reset of the charging process, the DRAIN pulse is excited with amplitudes of V DH = -10 V and V DL = 0 V. In the pixel circuit, the C ST = 1 pF is used to achieve maximum charging delay to evaluate the transient performance of p-type Cu 2 O TFTs.
For the Cu 2 O TFT, a channel length of 20 µm, and an S/D overlap length of 5 µm were chosen. To show the effect of active layer thickness on pixel circuit performance, TFT with 45 nm and 65 nm were simulated, respectively. Dynamic response for full HD displays (t cm of 16 µs ) are simulated. Fig. 5 (c) shows the overlayed output voltage at source terminal for 45 and 65 nm TFTs across the storage capacitor. For comparison, W/L ratio, L OV GS was kept the same for both the 45 and 65 nm Cu 2 O TFT respectively. We can observe that 65 nm TFT overcharged the capacitor voltage as compared with 45 nm. This could be due to more hole carriers present in 65 nm thick channel which is confirmed by increase in the g GA . After that, W value of both the TFTs were adjusted to get similar charging and holding performance as shown in fig. 5 (d). From earlier studies [46], the feed through voltage ( V P ) is expressed analytically as, Here, C GS is the overlapping capacitance between gate and source of TFT. From the above equation (6), V P is directly and inversely proportional to gate-source overlap length (L OV GS ) and C ST respectively.
It shows that, V P value is high for 45 nm TFT as compared to 65 nm TFT. This is due to the difference in the V th between 45 and 65 nm TFTs. V th for 65 nm TFT was calculated from the simulation and found to be -6.1 V. However, charging capacitor through 45 nm TFT performed marginally quick over 65 nm TFT.
In structural design point of view for TFT, gate to source/drain overlap (L OV GS ) in an important factor. Figure  6 shows the variation in L OV GS on 65 nm TFT. We can see that as it decreases to 1 µm, V P value got drop since it is proportional to L OV GS . Nevertheless, the TFTs driving capability is reduced, which can be seen in terms of charging. This is due to the fact that, smaller or narrow L OV GS causes high series resistance at the source/drain contacts due to current crowding effect [52], [53]. Where as larger L OV GS not good for display operation, since it causes large parasitic capacitance [46]. Finally, an exponential fit of RC time constant (τ ) for output voltage (V OU T ) within GATE pulse was performed to evaluate the charging characteristics of pixel circuit, expressed as Solving this equation to calculate the required time to charge the C ST will yield [48] , Alternatively, the time constant should be computed by substituting V OU T = 0.63V DH . Similarly, the time constant can also be calculated from transient simulation, by computing the time at 63% of V DH from V DL = 0. The theoretical and simulation results are compared in Table 4. It was found that for both the 45 and 65 nm Cu 2 O TFT, the charging time is almost very similar. However, some variation in V P was found. For 65 nm Cu 2 O TFT, V P is low in comparison with 45 nm TFT, which means it will experience less flickering.

V. CONCLUSION
In this article, physical modeling and numerical simulations of the p-type Cu 2 O TFT for the design and development of active matrix displays are presented. To understand the origin of bias stress instabilities, both positive and negative bias stress (PBS and NBS) on Cu 2 O TFT were investigated. From the investigation obtained, the following observations were drawn: 1) Copper and oxygen vacancies (V Cu and V O ) are prominent defects due to their low formation energies. They effect the acceptor-like (g GA ) and donor-like (g GD ) of DOS model. While V Cu significantly affects the OFF current and V th , the V O largely degrades the  ON current. 2) Under NBS, the interface charge carrier density, Q it was responsible for the shift in the V th since the hole carriers moved from channel to channel/dielectric interface. On the other hand, a small variation in V th with a significant deterioration in SS was observed under the PBS condition. This is due to the deficiency of free electrons and the presence of additional defects generated in Cu 2 O channel as stress time increases. 3) A significant amount of shift in V th from -7.1 V to -6.1 V was observed as the thickness of Cu 2 O channel increased from 45 nm to 65 nm. This is due to the decrease in the donor-like tail states, g T D since it captures the hole carriers. 4) Dynamic performance of Cu 2 O was evaluated and found to be better for higher channel thickness in terms of holding the output voltage. Also, the effect of gatesource overlap length (L OV GS ) on the output source voltage was studied. It was observed that, smaller or narrower L OV GS causes high series resistance at the source/drain contacts due to current crowding affect. However, the larger L OV GS increases the parasitic capacitance, which affects the display performance. Modeling of TFT through density of states (DOS) is a reliable approach which provides physical insights into the device, such as carrier transport and the behavior of the defects present in the channel. This contributes the necessary recommendations for optimizing the device in terms of its dimensions and channel material, which enhances the overall device efficiency. Finally, from circuit perspective, through DOS, a direct cause-effect relationship between defects and circuit performance can be realized under both DC and transient based electrical characterization. Therefore, it gives the developers a platform to realize complex large scale electronics.