A Scalable Discrete-Time Integrated CMOS Readout Array For Nanopore Based DNA Sequencing

This paper introduces a high-speed mixed-signal readout array in 130-nm CMOS for the amplification and digitization of picoampere-range signals. Its design is inspired by the needs of emerging DNA sequencing technologies based on biological nanopore sensors. To overcome switching and substrate noise this system adopts an in-pixel analog-to-digital converter (ADC) architecture and a novel readout technique while consuming 10x less power than similar designs described in the literature. The in-pixel ADC architecture is inherently scalable and immune to electrical interference which can be extended to 100s of channels. With a 5 pF input capacitance, the amplifiers achieve a maximum bandwidth of 100 kHz and demonstrate a noise floor as low as 4 fA/√Hz and a gain in the range of GΩ at 10 kHz. Circuit noise behaviour and theoretical maximum performance estimates using behavioural models are also discussed.


I. INTRODUCTION
T HIS paper presents a new CMOS "readout" chip capable of amplifying and digitizing very weak electrical current signals. The size of these signals is commensurate with those processed by a new generation of DNA sequencing machines. This application emphasizes not only sensitivity to small signal levels, but also bandwidth and the need to simultaneously operate over many parallel channels. To properly deal with these competing constraints as they stand now, and as they are expected to evolve, requires specially formulated readout chips, a problem addressed by the design described in this paper.
In more depth, our chip's purpose is to simultaneously carry out amplification, filtering, and digitization for individual signals as low as 10 picoampere (pA). As a necessity, this design aimed to achieve suitable per-channel signal processing quality. This goal targets the ability to process at sufficient sensitivities (⇠1 pArms) and speeds (at least 4 kHz) per channel. Our system met and exceeded these application-realistic specifications.
Of equal importance, however, was to forward a design that could practically achieve these per-channel performance targets across an array of simultaneously active pixels. For truly scalable designs, such a system should maintain its signal qualities while demonstrating a rich variety of functions, programmability, and excellent power efficiency. Over the reminder of the paper we provide the details of such a design including its specifications ( § III), the system architecture ( § IV), circuit design ( § V), experimental measurement results ( § VI), and comparison to other state-of-the-art contributions ( § VII).
First however we outline the exciting application that has motivated and constrained this design: nanopore-based DNA sequencing.

II. NANOPORE-BASED DNA SEQUENCING
An illustration of the essential technical features of a nanopore-based DNA sequencer are shown in Fig. 1. The concept is straightforward: as a DNA strand goes through a small hole (the nanopore) a weak current indicative of the DNA's molecular structure (i.e., the sequence of bases A, C, G, T) is excited [1]. This is essentially the resistive pulse sensing (RPS) concept as exploited by classic instruments such as the Coulter particle counter [2]. An ensuing analysis ("basecalling") of this current enables one to compute the sequence of the DNA strand that instigated it.
The thought of extending this concept to DNA sequencing is at least three decades old [3], but it was not until 2014 that mass-made nanopore-based DNA sequencing machines became generally available to laboratory practitioners [4]. This time span underscores the substantial difficulty of adapting the idea to practical DNA sequencing contexts. Although by some measures the fidelity of the nanopore-based approach is presently ⇠10⇥ worse than incumbent DNA sequencing machines [5] it demonstrates profound advantages in many other aspects, even in this early phase of it technological development.
Among their benefits, nanopore-based sequencers can measure DNA samples directly (rather than relying on chemically modified proxies); they also conduct their measurements in a streaming, real-time, fashion (rather than batch mode); they have been shown to measure contiguous DNA up to about 10 3 ⇥ longer than most other sequencing methods; they sense about 10 5 ⇥ faster than incumbent technology; and, given their ability to pack many sensors in a small volume, they achieve a throughput per m 3 that is over 10⇥ better than established techniques. As a result, even palmsized nanopore-based DNA sequencers have been marketed and have inspired excitement for the wide-spread deployment of DNA sequencing in low-cost and mobile contexts across a broad array of applications [6].
Numerous innovations were required to make nanoporebased sequencing practical. Naturally, the engineering of the nanopore sensor itself was critical. Presently, only bio-engineered "biological nanopores" (i.e., protein structures) have demonstrated commercial viability for DNA sequencing. Alternative fabrication methods (e.g., "solidstate nanopores"), although very promising [7] have not yet managed to meet the needs of DNA sequencing applications at scale. Currently, for commercial production, in excess of 10 4 biological pores can be arrayed at densities over 10 nanopores/mm 2 .
Of nearly equal importance to the nanopores themselves, have been the readout circuits that prepare these sensors' weak current outputs for ensuing digital analysis (i.e., basecalling). Readout chips must not only be able to digitize these small currents with sufficient accuracy and speed, but it is essential that they do so in an arrayed fashion. Many of the outstanding benefits of nanopore-based sequencers would be useless without the opportunity to register multiple measurements simultaneously.
This context served as the core inspiration for the CMOS readout chip we describe below. We sought to present a design that satisfied the core electrical signal processing requirements of nanopore-based DNA sequencing while also addressing the scales at which practical utilization of such a chip now calls for. Beyond satisfying the state-of-the-art as it is, we also sought to forward a design that could serve the technology as it evolves. For example, although the rates at which biological nanopore sequencers could measure DNA increased rapidly between 2014 and 2016 (from 30 Hz to 450 Hz) no further advances in per-channel speed have since been announced.
To our knowledge, a readout system as described here has not been presented in the open literature. However, a number of contributions to the area have been presented and serve as inspiration for our design. Previous works tend to focus on the realization of the analog facets of nanopore readout systems: the analog front-end (AFE). In this vein, work on suitable amplifiers has been especially active [8]- [21]. However it is almost certainly the case that as nanoporebased technology evolves, systems that consist of an array of channels and systems the provide a means to digitize all those channels will become critical. On this front, there have been relatively few reports.
Designs that contain readout arrays of four and twenty channels intended for use with solid-state nanopores are presented in [22] and [23], respectively. However, these contributions do not invoke any on-chip analog-to-digital converter (ADC) by which these signals may be digitized locally. To our knowledge, they also do not possess a facility to multiplex their channel signals through a limited set of chip output ports. Some interesting current readout arrays for electrochemical sensors have been presented in [24]- [30] but the bandwidth of amplifiers range from tens up to a thousand Hz. Biological nanopore experiments need tens of kHz bandwidth. A notable current readout array with 10 kHz bandwidth is presented in [31]. However, this contribution cannot be used with large input capacitance seen in nanopore sensors due to its amplifier topology. Also the system is not fully integrated as it uses off chip ADCs. We believe these are critical needs for practical systems expected to support large numbers of channels. Such features are important for nanopore-based systems intending to achieve high throughput with high sensitivity and low cost as they allow the measurements of many channels to be emitted as a serialized output stream.

III. SYSTEM SPECIFICATIONS
As noted above, the focus of this paper is on readout systems intended for signal conditioning of biological nanopore sensor arrays. At present, the biological nanopore sensing modality is arguably the most practical existing means of realizing high-throughput multi-channel nanopore-based DNA sequencing in the miniature. In this context, the signal specification for our system is discussed in § III-A. § III-B presents the amplifier requirements.

A. SIGNAL SPECIFICATION
A sense of the signal emerging from a biological nanopore in response to its interaction with a DNA strand is shown in Fig. 2. As with classic RPS, in the absence of DNA translocation through a nanopore, a quiescent "baseline" current, I base , flows through the sensor. In realistic DNA-sequencing applications based on biological nanopores I base ⇡200 pA. Once, a DNA strand enters the pore, thus obtruding its opening, there is a sudden drop in I base , by about 150 pA. Thereafter, as shown in § II, there are fluctuations in this low current, between about 50 and 100 pA. These fluctuations are a reflection of the DNA's finer structure. Once a DNA strand has completely traversed the sensor, the current returns to typical I base levels.
While the pore is obtruded by DNA, the induced low current fluctuations (see inset of Fig. 2) may be modelled as an aperiodic non-overlapping random pulse train [4]. Focusing only on the AC component of such a current signal, we can express its double-sided power spectrum with where 2 i it the mean-square of the DNA signal fluctuations and f t is the average translocation rate. In modern nanoporebased sequencers i ⇡ 10 pArms and f t ⇡ 450 Hz [4].
In such a signal, 95% of the AC power lies below 2f t . This suggests that to barely accommodate existing nanoporebased sequencers a readout system should exhibit a bandwidth of B=1 kHz while adequately amplifying the small input with minimal noise injection. We turn to a deeper consideration of these points next.

B. AMPLIFIER GAIN AND NOISE REQUIREMENTS
As indicated above, between its maximum unperturbed I base and its minimum obtruded current, the sensor's output signal swings across a range of about 150 pA. Mapping this swing to a V FS = 1-V ADC full-scale input range, a practical levels for portable technologies, requires the readout to realize a resistive gain of R G ⇡ 6 G⌦ (196 dB⌦).
For the readout system's SNR requirements we need to account not only for the signal, but also the data processors that may follow it. As noted above, complex detection schemes are needed to convert measured nanopore data to base sequence equivalents of the corresponding DNA. The readout system must not further complicate this process by injecting too much noise of its own. For this purpose, maintaining an SNR of 20 dB should be sufficient [32].
For the minimal requirements noted above -B=1-kHz, SNR=100, i =10 pArms, f t =450 Hz -an average inputreferred amplifier spot noise of q is needed. A more aggressive objective is to target faster nanopore systems capable of accommodating higher f t and thus faster sequencing rates. Indeed, today's biological nanopores are subject to intricate means of slowing down their reading ability in order to accommodate the bandwidth limits of existing readout circuitry. For example, a 20⇥ boost in the readout system's measurement bandwidth B would require the design to achieve an average noise of about 10 fA/ p Hz instead. Our work targets such potential future performance standards.

IV. SYSTEM ARCHITECTURE
As mentioned earlier, the information signal from a biological nanopore is only about 10 pArms. This calls for an ultra-sensitive, high gain, amplifier. But intending to enable high throughput measurements by arraying a single chip with many such amplifiers, all simultaneously active, invites substantial engineering challenges. Expecting the chip to also digitize these signals imposes further complications. Even with different supplies for digital & analog components and deep n-well to provide substrate isolation, digital components are a major source of noise. Consequently, a careful choice of system components and architecture is needed to preserve the sensitivity of the analog components. Fig. 3 shows an overview of our overall system architecture. At the highest level our design consist of three main blocks: our custom CMOS chip (digital pixel readout integrated circuit -DPROIC), a control and interface block (CI), and a networking block (NW). The CI supports all vital functions of DPROIC (reset, bias, clocking, programming, serial communications, etc.). The NW is responsible for VOLUME   forwarding the digitized measurement results from the CI to a remote processing system (e.g., the basecaller).The CI and NW are implemented on programmable hardware, CPLD and FPGA, respectively. In this paper, we discuss in detail only the DPROIC block, who's internals are further elaborated in Fig. 3. As shown, the design consist of 30 channels/pixels. A major design choice for DPROIC was to implement in-pixel digitization capability. This decision affords the most flexibility for scaling. Perpixel digitization enables more sophisticated data movement over very large arrays and it minimizes the distance over which analog data needs to be transported. Rough initial estimates indicated that even with this added complexity an extremely large array could be constructed within die sizes currently used for DNA sequencing (exceeding 100 mm 2 ).

V. READOUT CIRCUIT IMPLEMENTATION
This section presents an analysis of our readout system channels, its AFE component is discussed in § V-A & § V-B and its ADC in § V-C4.

A. DISCRETE-TIME AFE: AMPLIFICATION SEQUENCE
Using a capacitive-feedback TIA as the first stage provides low noise amplification (e.g. by obviating a noisy feedback resistance or active equivalent as present in continuous-time designs [16], [33]), but consequently requires a reset mechanism to avoid saturation of the amplifier. The gain of the integrator stage is dependent on its integration time period T INT and on the value of the feedback capacitor C F used. Longer integration periods and smaller feedback capacitor values give higher gain which can be expressed as the transimpedance where K represents the fraction of the integration period over which the DT-TIA is actually engaged in integrating the input. The AFE's output and control signals are shown in Fig. 4b where four main phases are identified: label=0 1) Reset: The switch control signals 1 and 2 go high. As a result, the charge in the DT-TIA and CDS stages from the preceding sampling epoch is flushed by 1 and 2 , respectively. 2) Noise Sample: 1 goes low and 2 remains high. In this brief phase, the DT-TIA commences signal integration while the CDS continues in reset. Effectively, a sample of the apparatus noise is captured on C 1 .

B. DISCRETE-TIME AFE: NOISE ANALYSIS
To convey underlying system features, a first-order noise analysis of the DT-AFE is presented in § V-B1.

1) Noise simulation with first-order model
The noise transfer function of the amplifier can be calculated in three steps: 1.) noise of the DT-TIA's integrator opamp amplified due to parasitic input capacitance, 2.) noise filtering due to the filter, 3.) noise shaping due to CDS and sampler. The signal transfer function can be calculated in two steps: integration stage, differentiation (CDS) stage.
Since the TIA has a synchronous reset (i.e. the sampling period, T S , is equal to integration period, T INT ), the equivalent noise model of the integrator is captured by the schematic in Fig. 5. The equivalent input-referred current noise of CMOS opamp is 0.1⇥10 15 A/ p Hz and hence can be ignored. The input-referred voltage noise of the opamp, v n , is amplified and filtered by the opamp. The noise transfer function (NTF) of the integrator is given by where in which C F is the integrator feedback capacitor, C IN is the nanopore parasitic capacitor, A 0 is the DC gain of the opamp and f c is the 3-dB cut-off frequency of the opamp. This noise is filtered using our LPF (f c f LPF ), so the NTF can be updated to The noise power spectral density (PSD) at the output of a LPF is thus given by where the opamp's input referred noise PSD may be modelled using [34] S n (f ) = S V0 This model captures the opamp's underlying thermal noise component, S V0 , and flicker corner frequency f flc . For our design estimates, we employ typically reported values for these terms: S V0 around 2.5⇥10 17 V 2 /Hz (i.e. v n ⇡5 nV/ p Hz) [20], [33] and f flc around 10 kHz. The equivalent noise model of the CDS is captured by the schematic in Fig. 6. The PSD at the output of CDS is given by where A CDS = C 1 /C 2 is the gain of CDS. Eq. (9) has two parts. The first term corresponds to the high pass filtering experienced by the flicker noise component out of the LPF. As thermal noise is uncorrelated noise, it is not cancelled by the CDS. The second term in (9) represents the amplified thermal noise. Finally, the noise PSD at the output of the T/H is given by The signal transfer function (STF) of the amplifier, from the integrator to T/H, is given by Fig. 7a shows the input referred noise density of the DT-AFE for various sampling frequencies, f S , with C IN set to 5 pF. The flat profile at low frequencies is indicative of the degree to which the system suppresses flicker noise. At 1-kHz sampling frequencies the system can achieve a sub 0.1 fA/ p Hz spot noise that rises in proportion with sampling frequency, due to diminishing transimpedance gain. At f S = 100-kHz (signal bandwidth of 50 kHz) this parameter reaches 6 fA/ p Hz. Integrating the input-referred noise density across operating bandwidth we approximate the system SNR as a function of signal bandwidth in Fig. 7b. This estimate demonstrates the potential of DT-AFEs for future nanopore sequencers. For DT-AFEs based on 5-nV p Hz amplifiers, a 20-dB SNR is possible for 25 kHz signals, about 25-times greater than the minimal contemporary needs noted above.

C. READOUT CHANNEL: IMPLEMENTATION
This subsection briefly outlines the circuit components used for the implementation of the readout channel.

1) Integrator
The amplifier uses an active integrator. The folded cascode opamp used in the integrator. It consumes of 105 µA current from a 1.2 V power supply. The opamp has been optimized for low noise. An input PMOS differential pair and large devices are used to reduce flicker noise. The opamp has a simulated thermal noise of 7.7 nV/ p Hz while the corner frequency is approximately 5 kHz. The open-loop DC gain of the opamp is 65 dB while the unity gain bandwidth is 100 MHz. The value of feedback capacitor C i can be varied from 25 fF to 150 fF.

2) Filter
The amplifier uses a Gm-C filter. To implement an RC filter in range of tens of kHz requires a large resistor and hence a large area. The resistor can be also implemented using a transconductor or active resistor. Though mosfet-C filter have better linearity, Gm-C filter have faster settling time. The time constant of a Gm-C filter is given by where C LPF is the capacitor used in the filter and g m is the transconductance of the transistor. The filter's time constant can be varied by either changing the capacitor or the g m of the transistor. In this implementation, the time constant is varied by changing the g m using the bias current while 1 pF capacitance was used. . The W/L of PMOS device was chosen to be 1µm/2µm. The PMOS source follower transistor was biased in sub-threshold region and has a g m that can be varied from 100 nS to 5 uS. The g m of the voltage follower remains constant from 0.05 to 1 V input voltage. The Gm-C filter settle faster compared to comparable RC filter due to large V GS during reset.

3) Correlated Double Sampling
An active CDS was employed in the amplifier. By using active CDS, the signal can be further amplified for data conversion. The CDS uses the same opamp used in the integrator. The value of C 1 used is 350 fF while C 2 can be varied from 50 fF to 150 fF. The effect of kT/C noise of C 2 is negligible. The performance of the amplifier with respect to bandwidth is shown in Table. 1. The simulation was performed with a 5 pF input capacitance and 20 fF feedback capacitor. It is evident from the results that noise floor is dependent on sampling period and integration period.

4) ADC
SAR ADCs are usually used for medium resolution and data rates in the range of few mega samples per second (MSps) while operating at low power [35]. The SAR ADC included in this design consists of a capacitive digital-toanalog converter (DAC), a comparator and digital circuits to perform a binary search algorithm. The digital output of the ADC can be in serial or parallel form. In this design, a 10-bit synchronous SAR ADC was implemented. This implementation uses a split capacitor DAC for smaller area and a class AB latched comparator to reduce kickback noise. Table 2 shows the options available for gain and bandwidth adjustment in each channel. Fig. 8 shows the layout of the DNA nanopore array. The 3⇥2 mm chip is fabricated in 0.13-µm CMOS technology. The area of each channel is 320⇥220 µm 2 .

D. READOUT MODES
Nanopore readout system need ultra-sensitive amplifiers but this makes integration of readout circuitry challenging. An AC noise from digital switching of ADCs couples into the high impedance input node of sensitive amplifiers from substrate and power supply through a capactive link. The noise can minimized using deep n-well & p+ guard ring and using separate power supply for digital and analog circuits. The noise sampling phase occurs after the amplifier is reset while the sampling phase occurs at the end amplification period. To minimize the impact of this AC noise due to digital circuit, the readout needs to be performed outside the these two phases otherwise it corrupts the measured signal.
To overcome this problem this section shows two ADC operation modes, serial and parallel. The timing diagram of serial and parallel mode is shown in Fig. 9a and 9b respec- tively. In the serial operation mode, the ADC conversion and data transfer is done right after the output is sampled. The amplifier is not operated while the ADC is performing conversion. This leaves some dead-time when the amplifier is non-operational. In parallel mode, the ADC conversion and data transfer are performed between the two CDS samples. It is clear from Fig. 9 that parallel mode improves the integration time and hence the overall performance of the amplifier. The block diagram for test setup has been shown in Fig. 10. The sensor is modeled on PCB using a 1-G⌦ resistor and 5-pF capacitor. Due to ultra-sensitive amplifiers careful testbench considerations were needed. Digital resistors are low noise compared to on-desk voltage sources. They also provide the opportunity to generate analog waveforms for multiple channels simultaneously. Hence digital resistors, which act as a voltage divider, were used along with 1-G⌦ resistors to generate test signals in the range of pico-amperes.

VI. MEASUREMENT RESULTS
Another important design choice was to use a complex programmable logic device (CPLD) instead of a field programmable gate array (FPGA). Intel CPLDs do not need any external oscillator. This is very useful as it provides isolation from large noisy signal of the oscillator. The entire analog frontend and CPLD are placed inside a shielded box. Another FPGA board which is isolated from the analog frontend is used to receive the data transmitted from the CPLD. The CPLD serializes the data from all ADCs and forwards it to the Xlinix Zynq 702 FPGA evaluation board. The CPLD is also responsible for loading the configuration registers on the test chip.
The Xlinix FPGA receives the serialized data along with its clock and stores deserialized data it a buffer. This data is transferred via TCP/IP socket to a Javascript graphical user interface (GUI) application. The data is plotted and saved by the GUI in real-time. To guarantee real-time operation the FPGA uses DMA to transfer data from buffer to TCP/IP socket. Fig. 11 shows the transient output of the integrator, filter and CDS for a DC input current of 10 pA. The integration time for this measurement was set to 61 µs. The reset period of the integrator and filter is 6 µs while for the CDS it is 15 µs.

1) Transient Results
The transient output for 400 Hz 100 pA pk-pk input square wave is shown in Fig. 12. The input capacitance of amplifier was 5 pF and sampling frequency was 16 KS/s. Fig. 13 shows the open-input noise spectrum at various sampling frequency. The noise measurement for various gain  settings of the integrator is shown in Table 3. The optimal gain setting is '010' as this maximizes the gain without clipping the signal, even though setting '100' provides the maximum gain. The bandwidth of the measurement was set to 13.95 kHz. The least observed noise at this bandwidth is 1 pArms.

3) Readout Mode
As highlighted in § V-D, the amplifier is sensitive to ADC digital noise. This section provides a digitized results comparison for each mode. It can be seen in Fig. 14 that amplifiers operate normally even with the ADC operating during the integration phase. But ADC operation causes a heavy DC offset in the output signal. During the serial ADC operation, the offset current was 10 pA while for parallel operation the offset current was 300 pA. This is probably due to unwanted current injection from the substrate during ADC operation but with proper input current offset cancellation circuitry it can be corrected easily.
By operating the ADC in parallel, the dead time is removed and it improves the performance of the system. But this comes with added distortion. Since the SNR of the system is so poor, the detectors should be able to handle such deterministic distortions.

4) Channel Interference
The transient output of nine channels measured simultaneously is shown in Fig. 15. It was noted that two channel in the same row exhibit a spur which is about 1000 times smaller than the signal in the active channel. This due to the capacitive coupling from wire routing of the input signal. If the local-pads are used there will much lower electrical coupling.
A summary of the systems main physical and performance characteristics is given in Table 4.

VII. CONCLUSION
This paper presented a signal conditioning array for nanporebased DNA sequencing. The array consists of 30 channels, each channel contains a DT amplifier and in-pixel SAR ADC. The DT amplifiers have a gain of G⌦ and are capable of sensing a pico-ampere current. This chip is a complete system with integrated electrode and readout circuits which sets the stage for high throughput DNA sequencing experiments. The chip has been validated against emulated nanopore signals and was found functional. The chip is intended for use with biological nanopore and has on-chip electrodes to implement highly integrated sensors. The performance comparison with other nanopore arrays have been presented in Table 5. The system is the first complete array ROIC with multiple channels and integrated ADCs found in literature for nanopore based DNA sequencing. Using novel readout techniques, triple-well isolation, filtering and low crosstalk PCB components the system was able to overcome problems caused by integrating digital circuits. Furthermore, the power consumption of the amplifier is 10x lower compared to stateof-art DT amplifier with comparable noise and bandwidth presented in [13], [20]. The channels also has the smallest area consumption compared to other state of the art nanopore amplifiers which is imperative for large arrays. The chip also contains various gain & filter settings as well as calibration circuits to deal with process variations. The system has 1000x smaller cross-talk in neighbouring channels compared to actual signal amplitudes. This low electrical cross-talk and in-pixel ADC architecture, facilities the ability to scale to hundreds of channel.