Asynchronous Digital Low-Dropout Regulator with Dual Adjustment Mode in Ultra-Low Voltage Input

This paper presents the asynchronous digital low-dropout regulator (AD-LDO) with dual adjustment mode in ultra-low voltage input. The architecture of the proposed AD-LDO consists of the asynchronous control loop and the power PMOS array. The proposed AD-LDO is controlled by switched bidirectional asynchronous control loop which can eliminate the clock power consumption of synchronous LDO. The dual adjustment mode can not only provide wider loading current, but also can reduce output voltage ripple. Moreover, the proposed AD-LDO only uses one bidirectional asynchronous control loop for two adjustment modes, so it can save area and reduce power consumption. Under the 350mV input voltage and 300mV output voltage, the proposed AD-LDO can provide 2.4mA output current with 99.8% current efficiency and only consume 5μA quiescent current. Therefore, the proposed LDO is suitable for applications of wearable electronic devices with an ultra-low supply voltage.


I. INTRODUCTION
In recent years, integrated circuit (IC) design of wearable electronic products has developed in the direction of ultra-low voltage, ultra-low power consumption and high integration. The most important issues of wearable electronic products are small area and low power consumption. In power management system, there are two kinds of power circuits to provide the required power supply voltage: the switching converters, and the low-dropout regulators (LDOs). The advantage of LDO is that it does not require additional inductors like switching converters. Therefore, it is suitable for integration in a chip. Another important issue is power consumption. The power consumption of a circuit can be given as follows: where CLD is the equivalent load capacitance, VDD is the supply voltage, f is the operating frequency, and Ioff is the standby current. According to the formula (1), the most effective method to reduce power consumption is to decrease the supply voltage VDD for extending use time of wearable electronic produces. As illustrated in Fig. 1, the system-on-a-chip (SoC) of a wearable electronic product includes various analog, digital, mixed-signal, and RF circuits. In references [1]- [11], many circuits with a supply voltage of 0.3V have been proposed. Therefore, the design of power management IC will focus on ultra-low voltage design to achieve ultra-low power consumption.  The LDO is more suitable for ultra-low power circuits than the switch converter because it has the advantages of small chip area, low circuit complexity, and low output voltage ripple. As shown in Figure 2, the traditional analog LDO consists of the error amplifier (EA), the power MOS, two feedback resistors (Rfb1 and Rfb2), a load capacitor (CL), and an equivalent series resistance (RESR) in parallel with a load resistor (RL). The operation performs the following steps in order. First, the EA compares the voltage error between feedback voltage (VFB) and reference voltage (VREF) to generate an analog voltage signal (VG) to control the power MOS. Second, a corresponding output current is generated to regulate the output voltage by adjusting the VG voltage of the power MOS. Since there is no influence of the switch, the output voltage of the LDO is more stable than the switching converter. However, due to limitation of the threshold voltage (VTH) and voltage headroom, the traditional analog LDO is difficult to design in ultra-low voltage systems. Conversely, the digital LDO is easily to design in ultra-low voltage system. Figure 3 shows the branch diagram of digital LDOs architecture. The circuit architecture is divided into three parts: synchronous, asynchronous and hybrid. Most architectures of digital LDOs are synchronous system [11][20]- [25][27]- [32]. The advantage of the synchronous digital LDO is that the design is simple, and the clock is responsible for the operation of the circuit. However, the synchronous digital LDO is controlled by the clock, and it will encounter several problems. The first is the clock skew problem, which will cause the internal control state value of the digital LDO to be wrong, and the output voltage of the digital LDO cannot be locked. The second is the operating frequency setting problem. As shown in Fig. 4 [16], the clock (Fclk) frequency is related to the tracking time and the current efficiency. Due to the high frequency, the tracking time is short. However, it will cause a large power consumption of quiescent current in the locked state. On the contrary, the low frequency cause the long tracking time, but the quiescent current power consumption is lower. Both NMOS and PMOS power MOSs are used to reduce the effect of transient response on output voltage in [16]. In [17] [18], asynchronous multi-loop is used to improve the problem of slow thermal code tracking, speed up the tracking speed and voltage regulation accuracy. However, it takes a lot of quiescent current. In [26], the asynchronous method is use to fast lock, and then switch to an analog LDO for voltage stabilization. However, the analog LDO cannot be used at ultra-low voltage. Reference [33] uses asynchronous-flash for fast tracking, and then use bidirectional synchronous shift register for voltage regulation. In [16]- [18], [26] and [33], asynchronous digital LDO uses handshaking protocol to communicate with neighboring circuits instead of clock signals. It has the advantages of high tracking speed and no clock skew problem. Since there is no clock, the quiescent current power consumption in the locked state is extremely low. Therefore, this paper proposed an asynchronous digital low-dropout regulator with dual adjustment mode in ultra-low voltage input in a standard 90 nm CMOS process technology.
(1) Only one switched bidirectional asynchronous control loop.
The proposed AD-LDO only uses the same SBACL for two adjustment modes, so it can save area and reduce power dissipation. (2) Ultra-low voltage applications. This indicates that the architecture can be applied to 0.35V and low-power applications. The remainder of this paper is organized as follows: Section II describes the circuit structure and operating principle of the proposed AD-LDO. Section III presents the simulation results. Finally, the conclusion is drawn in Section IV.

II. CIRCUIT STRUCTURE AND OPERATING PRINCIPLE OF THE PROPOSED AD-LDO
The voltage difference between the reference voltage VREF and the output voltage VOUT is converted into the set of digital codes through dual adjustment mode in the asynchronous digital control loop. The set of digital codes controls the subsequent power PMOS array to charge the output voltage VOUT. Therefore, the output voltage is regulated. In addition, the transfer function in [25] mentions a digital LDO as a first-order feedback system. Therefore, the proposed AD-LDO has enough phase margin to keep the circuit in a stable state. The relative operating principles and circuit architecture of the asynchronous digital control loop and the power PMOS array are as follows.  Figure 6 illustrates the operation principle of the coarse adjustment mode, the fine adjustment mode and the dual adjustment mode. The traditional digital LDO only uses the coarse adjustment mode or the fine adjustment mode to track the reference voltage. If the coarse adjustment mode is selected, it has the advantage of fast locking, but the output voltage has a large voltage ripple after locking. On the contrary, if the fine adjustment mode is selected, the tracking time will be longer, but the output voltage will be more stable after the lock. Based on the above, the proposed AD-LDO adopts dual adjustment mode to achieve fast locking and low output voltage ripple characteristics.

B. THE ASYNCHRONOUS DIGITAL CONTROL LOOP
The asynchronous digital control loop consists of a switched bidirectional asynchronous control loop (SBACL), a finite state machine (FSM), a data MUX, a peak detector, and a data register. The peak detector circuit structure is shown in Fig. 7. The circuit consists of two inverters with different logic threshold voltages and digital logic gates. When the mode signal is high, the peak detector is operating in the coarse adjustment mode. This circuit will not activate the detection function. On the contrary, when the mode signal is low, it is the fine adjustment mode. If the feedback voltage (VFB) exceeds the set voltage range of two inverters, the XNOR will output a high level. At the same time, the mode signal is low and a pulse signal (Reset) is generated after the subsequent logic gate operation. The Reset signal is provided to the system to restart the coarse adjustment mode.
In the initial state, the asynchronous digital control loop operates in the coarse adjustment mode. After the SBACL compares the reference voltage VREF and the feedback voltage VOUT, it generates a set of coarse adjustment digital codes CTSN to control the subsequent large size PMOS array to achieve fast locking operations. When the fast locking operation is completed, coarse adjustment digital codes CTSN will be recorded in the coarse data register. Then enter the fine adjustment mode, the SBACL sends a control signal Brq<11:0> to the FSM to generate two control output signals Sel and Mode. The fine adjustment digital code of SBACL is sent to data register through the output FDS of the data MUX under the selection signal Sel. Another signal Mode is sent to the peak detector to detect whether the VOUT voltage change exceeds the fine adjustment range. In the fine adjustment mode, the reference voltage VREF and the feedback voltage VOUT are compared through the SBACL to generate a set of the fine adjustment digital codes FTSN. This set of digital codes control the subsequent small size PMOS array to achieve fine-tuning operation. When the fine-tuning operation is completed, fine adjustment digital codes FTSN will be recorded in the fine data register. The lock time TLOCK of the proposed AD-LDO is given as follows: where RLOAD is an equivalent resistance of loading, N is the total number of modified asynchronous control units (MACU). IC and IF are the currents of large size PMOS and small size PMOS, respectively. TC is the time of the coarse adjustment operation to the (j-N) th stage, TF is the time of the fine adjustment operation to the (i-N) th stage, and Tn is the operating time of each MACU in SBACL. The total lock time TLOCK can be expressed in formula (3). If IC is m multiplied by IF, the relational expression of TLOCK is as shown in formula (4). Therefore, the ratio of the coarse current to the fine current can be set to reduce the lock time keep the voltage ripple low.

C. SWITCHED BIDIRECTIONAL ASYNCHRONOUS CONTROL LOOP (SBACL)
As shown in Fig. 5, the SBACL consists of the heading reflector (HR), MACUs and the terminal reflector (TR). The HR and the TR [16] are used as the boundary of the SBACL. The MACU circuit structure is illustrated in Fig. 8. When the Mode signal is high, the SBACL is in the coarse adjustment mode. The comparator of the MACU is shown in Fig. 9. It is a clocked-comparator structure. The comparator of the MACU is triggered by the previous-stage forward signal to compare the voltage difference between VREF and VOUT, and the resulting output signal is sent to the output CTSN of the DFF_C. Then send the CTSN signal to CMQN by selecting 2-1 MUX to control the subsequent large size PMOS for fast locking. Moreover, the 2-1 MUX output signal CMQN and output signals CMQN+1 and CMQN+2 of the next two stages are sent to the State-MUX as selection signals. As shown in Table I, the MACU passes the forward signal to the next stage MACU or backward signal to the previous stage MACU by selecting the signal combination. As described above, each stage of MACU will do the same operation until the SBACL completes the coarse adjustment operation. After the coarse adjustment operation is completed, the DFF_Cs of MACUs saves the coarse adjustment digital codes and then enters fine adjustment mode. When the Mode signal is low, the SBACL is in fine adjustment mode. The same MACU is used for the fine adjustment operation without extra area cost. The comparator of the MACU compares the voltage difference between VREF and VOUT, and the resulting output signal is sent to the output FTSN of the DFF_F. Then send the FTSN signal to CMQN by selecting 2-1 MUX to control the subsequent small size PMOS for low output voltage ripple operation. Finally, after the fine adjustment operation is completed, the DFF_Fs of MACUs saves the fine adjustment digital codes. Therefore, the dual adjustment mode proposed in this paper only uses one set of SBACL without increasing extra area cost.

D. OPERATION PRINCIPLE OF THE AD-LDO
The timing diagram of the proposed SBACL is shown in Fig. 10. The FSM is mainly used to decide whether to use coarse adjustment mode or fine adjustment mode. Figure 11 illustrates the circuit structure of the FSM. Initially, the whole system is reset to coarse adjustment mode. The comparator of VREF VOUT EN the first MACU compares the voltage difference between VREF and VOUT. If the VOUT is lower than the VREF, the MACU1 generates signal 0 and stores it in the coarse data register DFF_C, and turns on the subsequent large-size PMOS to charge the VOUT. In the meanwhile, forward signal (Freq0) is sent to coarse data registers MACU2. The remaining tracking operations from Freq1 to FreqN can repeat Freq0. When the backward signal Breq5 appears, the output Mode signal of the FSM changes from high to low. Then the SBCAL enters the fine adjustment mode. The SBACL restarts tracking from the first MACU, generates a digital control signal and stores it in the fine data register DFF_C, and turns on/off the subsequent small-size PMOS to charge/discharge VOUT. When the entire tracking operation finally stabilizes to a set of Freq1 and Breq2, and then the entire AD-LDO tracking is completed.
When the system enters the fine adjustment mode, the output voltage is monitored by a peak detector. As illustrated in Fig. 12, once the output voltage variation exceeds the 10% the peak detector will generate a reset signal to reset the entire system. The formula of output voltage variation is given as follow:

E. POWER PMOS ARRAY
As illustrated in Fig. 13, the power PMOS array includes large-size PMOS and small-size PMOS, which are used for large current and small current respectively. Moreover, large-size PMOSs are used for coarse adjustment, and small-size PMOSs are used for fine adjustment, both of which are 12 bits. As shown in Fig. 5, because the digital code for coarse and fine adjustment is generated with the same SBACL, power consumption and area can be saved. The power PMOS array is controlled by the thermal code which is stored in the data register. The size of power PMOS is directly related to the output load current and output regulated voltage. So the output current can be defined as where IH is the heavy load current, N is the number of PMOS bits, RLOAD is the load resistance, IC and IF are the currents of the large size and small size PMOS, respectively. As in formula (6), N in the proposed AD-LDO is equal to 12, so the heavy load current IH is 12 times that of the coarse adjustment current IC. And the fine adjustment current IF is one-twelfth of the coarse adjustment current. The large size of the PMOS can immediately provide a large current IC to achieve fast tracking. The small size of the PMOS can supply small current IF to reduce the output voltage ripple. As shown in formula 7, it is the limit to maintain the system operation in the fine adjustment mode.

III. SIMULATION RESULTS
The proposed AD-LDO was designed in TSMC standard 90 nm CMOS process technology. The chip layout of the proposed AD-LDO is shown in Fig. 14 and the active area is 0.114mm 2 . The input voltage is 0.35 V, the output voltage is adjusted to 0.3 V, and the load current range is 0.2mA~2.4mA. Figure 15 is the simulation waveforms from heavy load (2.4mA) to light load (0.24mA) and from light load (0.24mA) to heavy (2.4mA) load. Regardless of the conversion, the entire system will be reset first. Start tracking from the coarse adjustment mode until the output voltage change is less than 10%, and then enter the fine adjustment mode. As shown in Fig.15, the longest tracking time is 7.5μs from light load to heavy load. Finally, the output voltage VOUT is regulated. Figure 16 shows the simulation results of output voltage changes under heavy load and light load in different corners of the environment. As shown in the simulation waveform, the maximum voltage variation is ±1% at light load. The comparisons of the prior digital LDOs are shown in Table II. This paper proposes the new asynchronous digital LDO with dual adjustment mode under 0.35V input voltage. It can provide a stable output voltage of 0.3 V and a heavy load current of 2.4 mA. The quiescent current is only 5µA and the current efficiency is 99.8%. Quiescent current includes leakage current and other wasted current of the whole circuit. Other indexes such as line regulation, load regulation and current efficiency are listed in Table II respectively. In digital LDO, we often use line regulation to express PSRR. The line regulation of the proposed AD-LDO is 4.5mV/V. The load regulation of the proposed AD-LDO is 0.3 mV/mA low than most papers. Moreover, the proposed AD-LDO has a very low ratio of voltage change divided by current change. The proposed dual adjustment mode technology has the characteristics of low output voltage ripple and fast tracking. Although the dual adjustment mode tracking architecture is used, only one SBACL circuit is used. Consequently, the area cost is saved. Therefore, the proposed AD-LDO is suitable for SoC applications of wearable electronic devices with an ultra-low supply voltage.

IV. CONCLUSION
This paper proposes a new design for an asynchronous digital controlled LDO with dual adjustment mode technique in ultra-low voltage. The coarse adjustment mode is fast tracking, and the fine adjustment mode is to reduce output voltage jitter. Base on simulation results of 90nm CMOS process technology, it can provide a stable output voltage of 0.3 V and a load current of 0.24 mA to 2.4 mA. For a supply voltage of 0.35 V, the quiescent current is only 5 µA, and the current efficiency is 99.8%. Therefore, the proposed AD-LDO is suitable for wearable electronic devices with an ultra-low supply voltage.