Analog CMOS readout channel for time and amplitude measurements with radiation sensitivity analysis for gain-boosting amplifiers

The front-end readout channel consists of a charge sensitive amplifier (CSA) and two different unipolar-shaping circuits to generate pulses suitable for time and energy measurement. The signal processing chain of the single channel is built of two different parallel processing paths: a fast path with a peaking time of 30 ns to obtain the time of arrival for each particle impinging the detector; and a slow path with a peaking time of 400 ns dedicated for low noise amplitude measurements, which is formed by a pole-zero cancellation circuit and a 4th order complex shaper based on a bridged-T architecture. The tunability of the system is accomplished by the discharge time constant of the CSA in order to accommodate various event rates. The readout system has been implemented in a 180 nm CMOS technology with the size of 525 μm x 290 μm. The building blocks use compact gain-boosting techniques based on quasi-floating gate (QFG) transistors achieving accurate energy measurement with good resolution. The high impedance nodes of QFG transistors require a detailed study of sensitivity to single-effect transients (SET). After carrying out this study, this paper proposes a method to select the value of the QFG capacitors, minimizing the area occupancy while maintaining robustness to radiation. The nonlinearity of the CSA-slow-shaper has been found to be less than 1% over a 10-70 fC input charge. The power dissipation of the readout channel is 4.1 mW with a supply voltage of 1.8 V.


I. INTRODUCTION
Front-end electronics (FEE) are a fundamental part in the signal processing systems of modern particle detectors. Regardless of the type of experiment and associated electronics, some basic principles are common: the electronic readout system has to acquire the signals from the sensor, digitizing and storing them for later analysis. The design of readout front-end channels finds great interest nowadays in applications where the sensor response to external physical stimulus is given in form of electrical charge, typically a short current pulse. Signal processing from radiation detectors for nuclear or particle physics, or medical imaging applications, are particular fields where FEE are widely used, with a trend towards complete system on chip design solutions [1]- [4].
In addition, in some of these scenarios the performance of analog circuits under radiation conditions is nowadays a main concern. This hostile environment, in which the FEE systems often operate, requires designs that take into consideration the harmful effect of radiation on some electronic components, especially those based on semiconductors, as this increases the probability of failure.
FEE refers to the closest electronics to the detector, and involves signal conditioning tasks related to charge to voltage conversion, amplification, pulse-shape conformation and analog-to-digital conversion. The operational amplifier (opamp) is the most important building block for the analog part of a front-end system, whose performance limits most of the properties of the overall front-end channel. With the increasing demand for a higher number of channels, and given their high density of electronic components, the performance of sensors and sensor interface integrated circuits is increasingly important. Systems with low noise and low power consumption have become essential. In particular, the power efficiency of the analog building blocks must be improved.
An extensive discussion over the design of readout systems for semiconductor radiation detectors exists in literature [5]- [12], yet these systems require continuous improvement in order to keep up with the developments in modern detector systems. Furthermore, many of the available integrated readout circuits are implemented in modern CMOS technologies, where several trade-offs must be conciliated: power dissipation-bandwidth, low voltage-high gain, low voltage-dynamic range, noise-power dissipation and high gain-small size transistors. In particular, the scaling properties of the VLSI processes have degraded some analog parameters of the transistors, and thus, they have also changed the design techniques used for CMOS analog circuits. In this way, the low output resistance of the transistors directly decreases the gain. Thus, for a proper closed-loop operation of the main circuits of a FEE, i.e., charge sensitive amplifiers (CSA) and shapers, the open-loop gain of their active elements (op-amps) must be high enough.
To this end, several approaches have been introduced [13]- [16]. One of the most extended techniques is the regulated cascode, based on the use of an extra amplifier to achieve a local negative feedback loop that further enhances the output resistance of the circuit [17]. The implementation of this extra amplifier determines the performance of the complete op-amp in terms of power consumption, bandwidth, chip area, and supply voltage.
This work addresses the low open-loop gain problem related to the degradation of the analog properties of transistors in modern CMOS technologies. A single stage telescopic amplifier is designed using a local feedback amplifier, resulting in an increased amplifier output resistance. The auxiliary amplifier is realized in a compact design based on the quasi-floating gate (QFG) technique, which has the effect of only a low increase in power consumption, making it suitable for low voltage applications [18], [19]. The properties of the telescopic amplifier have been exploited to design a front-end readout system for charged particle detection using silicon as detector material. Furthermore, as the proposed FEE is intended for radiation detection, these techniques should be validated assuming that the readout channel works in harsh environments, such as, particle accelerators or nuclear applications, where high levels of ionizing radiation interact with analog components, producing large voltage transients, which must be taken into account to ensure a proper functionality of the system.
In the particular case of the proposed circuit, the use of QFG transistors could compromise the behavior of the circuit due to the existence of very high impedance nodes. These nodes could cause the transient voltage variations due to an impact (single-event transient, SET) to lengthen over time, preventing the use of the circuit for harsh environments. In this paper, the effect of high-energy particles impacts on QFG transistors has been analyzed in detail and a methodology has been proposed that allows selecting a value of QFG capacitors to minimize the effect of radiation. This study and methodology are based on the use of an automatic tool to evaluate the sensitivity to single-event effects (SEE) [20].
The paper is organized as follows: Section II describes the basic architecture of the front-end readout channel and presents in detail the circuit schematics. Section III deals with the simulation results and analyzes the robustness to radiation of the front-end system, and in particular, of the QFG technique. Section IV deals with the measurement results of the system. Section V presents the noise performance. Finally, some conclusions are drawn in Section VI. Fig. 1 shows a block diagram of the readout front-end system designed for semiconductor particle detectors. The ASIC consists of a single readout channel formed by a charge sensitive amplifier (CSA) with a capacitive feedback CF and a resistive feedback (MF) connected in parallel, a pole-zero cancellation (PZC) network, a differentiator CR-stage, two second-order bridged-T filters connected in cascade (slow shaper) and a CR-RC filter (fast shaper). The internal biasnetworks are not shown in the block diagram.

II. FRONT-END READOUT CHANNEL
The input charge comes from the detector, which is a solidstate device made of silicon. The detector is an inversely biased pn junction built with two electrodes to which a high electrical potential is applied. The detector directly transforms the impinging radiation into an electrical signal. The radiation generates electron-hole pairs, which are put in motion by the influence of the electrical field, producing an electrical current. In nuclear and particle physics, the signals obtained are usually pulse signals.

A. CHARGE SENSITIVE AMPLIFIER AND DESIGN CONSIDERATIONS
Since the charge QIN delivered by the semiconductor detector is very small it is quite impractical for immediate signal processing. A proper amplification is required, and for this reason, preamplifiers are the first stage in the readout system. They are usually placed closest to the detector for noise minimization, since noise at this stage is critical. The preamplifier provides an output pulse whose amplitude is proportional to the charge released by the incident radiation.
A charge sensitive amplifier is adopted for the collection of the charges from the detector since this type of amplifier provides a charge-to-voltage conversion independent of the capacitance at the input node (both the detector capacitance and parasitic capacitances). Assuming at the input a delta-like current pulse a voltage step is obtained at the CSA output, which is proportional to the total charge carried by the detector pulse, given by: where CF is the feedback capacitor of the CSA and Ci is the total capacitance at the input node. If the op-amp has a large open loop gain (A >> 1), then the above equation can be simplified to vout (t) = − QIN/CF, and the conversion gain is determined by a well-controlled component, the feedback capacitor. Thus, this work is focused on achieving this high gain since for old CMOS technologies it is relatively easy to reach, but for modern CMOS processes additional gain enhancement techniques are needed.
The core of the preamplifier is a modified telescopic amplifier shown in Fig. 2. This topology uses cascode transistors that allow achieving quite large gain for a single stage due to the large impedance at the output node. This also requires that the current sources connected to the output nodes are realized using cascode current mirrors. The voltage gain can be written as GmRout, where Gm  gm1 and For typical values, the voltage gain can be approximate as: A large bandwidth is also required to process the fast pulses from the detector. Usually, for the telescopic topology the high gain is obtained without any degradation in speed if a careful design is made. Nevertheless, for the charge sensitive amplifier it is possible to use cascode transistors since the output swings are only of several tens of millivolts.
A pMOS has been chosen as input transistor (M1) for its superior noise performance, since for modern CMOS technologies the flicker noise becomes more significant. The cascode transistor M2 limits the voltage across the input transistor and minimizes short-channel effects.
As mentioned above, the open loop gain of the telescopic amplifier determines the performance of the feedback system, i.e., the accuracy of the charge-to-voltage conversion. In order to increase the gain, from eq. (3) we must increase the transconductance of the input transistor gm1 or the output resistance of transistors ro. In practice, noise requirements also require to increase gm1 through the width and the bias current. With respect to ro, its value is given by 1/(λID), and appear in the path signal, it is desirable to keep their capacitances to a minimum, whilst M3 and M4 affect the signal to a much lesser extent, have greater mobility and can therefore have larger dimensions, doubling the length and width. Note that, since in a conventional telescopic amplifier the same current flows through both transistors M4 and M1, it is difficult to decrease ID, which makes it complicated to simultaneously obtain high transconductance gm1 of input transistor M1 and a high output resistance ro4 (ro3) of transistor M4 (M3).
In this work, in addition to the design considerations described above, and taking into account that the intrinsic gain of transistors decreases continuously as sizes scale down, additional gain enhancement techniques are addressed [21]- [22]. The telescopic amplifier in Fig. 2 includes two of them: (1) the regulated cascode approach based on a local negative feedback loop that increases the gain by a factor AGB [14]; and (2) an additional biasing branch formed by M6 and M7 that delivers most of the current of the input transistor M1, overcoming the aforementioned gm1-ID trade-off, and improving noise performance (as the input transistor carries out all the current) [23], [24]. A conventional source follower stage formed by M8 and M9, which acts as an output buffer, has been included to drive the load.
The regulated cascode technique does not compromise stability nor reduces headroom if it is used at low swing internal nodes. Different topologies to realize the local feedback (or auxiliary) amplifier, which enhances the effective gain of the cascode transistor, have been reported [25]- [29]. The proposed implementation in this work is based on a simple common-source amplifier (M5 and IB1) but combined with the QFG technique [19] to mainly overcome the limitation of low supply voltages. If the gate of transistor M5 is directly connected to the drain of M1, the maximum voltage at the drain of M1 is given by VDD − (VTH5 + VDS,sat5), where VDS,sat5 is the overdrive voltage for M5 to remain in saturation.
However, the use of the QFG approach achieves that the gate of M5 is connected to a DC biasing voltage through a large resistive element Rlarge, and it is AC coupled to signals by means of the small valued capacitor C. The gate of M5 is decoupled in DC of the drain of M1 (and thus, this node can operate at higher voltages), and transistor M5 acts as a diode in DC, making VGS = VDS. Rlarge is implemented using a series connection of diode-connected transistors [30]. The path for signals from the drain of M1 is a high pass filter while for signals at the drain of M5 is a low pass filter, both with corner frequency fc=1/(2πRlargeC), typically of a few Hz. At frequencies higher than fc the drain of M5 is no longer connected to the gate, whereas the coupling capacitor C establishes a connection between the drain of M1 and the gate of M5. Thanks to the large value of Rlarge, the value of the capacitor C is only limited by the parasitic capacitance at node Y in order not to attenuate the voltage transferred from the drain of M1 to the gate of M5. A similar QFG scheme is applied to cascode transistor M3. Finally, the QFG gain-boosting (GB) auxiliary amplifier does not introduce additional noise. Thus, the noise generated by the resistance Rlarge is negligible since it is not a resistance due to the channel of the transistor, but the leakage resistance of a diode-connected transistor operating in the cutoff region.
Regarding the feedback network, the pMOS transistors MF1a and MF1b in Fig. 1 behave as an active resistance (RF) connected in parallel to the feedback capacitor CF to avoid saturation of the CSA by continuously discharging the feedback capacitance. These transistors contribute to the parallel noise at the CSA input and their values were chosen to be high (nominal value of 1.2 MΩ, with transistor dimensions W/L of 0.5 m/10 m and VFB = 100 mV) as a trade-off between noise and counting rate. A high resistance value provides a slow pulse tail and minimizes the noise introduced, but a tail too slow can lead to pile-up effects resulting in the overlap between successive pulses in high rate experiments. The use of active feedback transistors instead of passive resistors saves area and reduces parasitic capacitances, and allows controlling the feedback resistance. The CSA pulse output decays exponentially with a relatively long discharge time constant τF = CFRF. CF has been set to 500 fF.

B. POLE-ZERO COMPENSATION CIRCUIT
The low frequency part of the CSA output pulse is removed by an RC differentiator stage (high pass section) formed by CPZC and R5 in Fig. 1. The CSA feedback network together with the differentiator stage create an undershoot at the shaper output, which produces a baseline shift, and thus, a loss of the amplitude resolution of the system. The undershoot can be removed applying a pole-zero cancellation circuit by adding a resistor MPZC (RPZC) in parallel to the capacitor CPZC [31]. This resistor has also been implemented by pMOS transistors and creates a zero that cancels the pole introduced by the feedback network of the CSA. The transfer function is given as: where RF and RPZC represent the equivalent small signal channel resistance of the MF and MPZC transistors, respectively. The correct cancellation requires that the condition CFRF = CPZCRPZC is satisfied.

C. PULSE SHAPERS
The CSA output is split into two different bandpass filters to process in parallel the incoming pulses for time and energy measurements. The fast path is a CR-RC shaper optimized to determine the input charge arrival time with a peaking time of 30 ns. The slow path is a shaper consisting of two (RC) 2 filters in cascade shaper used for peak-amplitude measurement with a peaking time of 400 ns. The aim of the slow shaper is to optimize the overall signal to noise ratio by filtering the CSA output, limit the pulse width to reduce the possibility of pulse pile-up, and provide additional gain to the analog processing chain.
The amplifier used as the core for the fast shaper has the same topology as that of the CSA, but the size and the power dissipation of the input transistor is lower because it has less influence on the noise performance of the entire system. However, for the slow shaper a different amplifier topology has been used. Thus, a two-stage op-amp has been designed as shown in Fig. 3. The input stage is based on the telescopic topology with QFG gain-boosting scheme equal to that of the CSA but scaled-down, and the output stage is a rail-to-rail common source scheme that maximizes the output swing. With a supply voltage of only 1.8 V, it is advisable to avoid using cascode transistors in the output branch of the slow shaper in order to enlarge the energy range that the front-end electronics can handle. The choice of the filter type, order and its time constants strongly depends on the specified energy resolution of the readout system and its high-rate operation requirements. Two types of filters are often used: semi-Gaussian pulse shaper CR-(RC) n based on real poles, and quasi-Gaussian shaper. For the same filter order n, the quasi-Gaussian shaper is more suitable for low noise performance and high rate applications since it allows obtaining a shorter and symmetrical pulse. This satisfies the baseline return time requirement, which is a fraction of the average interarrival time, precluding the overlap between successive pulses.
A compact approach to obtain a quasi-Gaussian filter, which can be applicable in integrated circuits, uses a simple CR differentiator with a real pole followed by a limited number of active filter sections, which have complex poles obtained on the basis of frequency domain analysis.
The designed slow shaper is implemented with two secondorder bridged-T filters connected in cascade, and optimized for low noise accurate peak-amplitude measurement. The transfer function of each second-order section shown in Fig.  1 is given as: The procedure used to design the quasi-Gaussian filter (or complex shaper) follows the direct synthesis method [32]. The simple CR differentiator formed by R5 and CPZC in Fig. 1 realizes a real pole, which determines the time constant. The two complex conjugated poles obtained by the 4th order bridged-T topology are in the positions: The relation between the time constant of the differentiator and the real pole is given by R5CPZC = σ0τx/A0, where A0 = 1.4766878, σ0=1.0844 and τx is the time constant of a CR-RC filter. For τx = 250 ns, R5 has been set to 91.5 k yielding CPZC = 2 pF. The complex pole pairs are pi = -Ai ±Wi, where Ai and Wi are the real and the imaginary parts, respectively. From (6), they are given by: The coefficients Ai and Wi are provided in [32] for each second-order stage of the filter. In order to simplify the design, all resistances are set to the same value R=R1=R2=R3=R4 = 40 k. For the first stage: A1 = 1.4166647, W1 = 0.5978596, and for the second stage: A2 = 1.2036832 and W2 = 1.2994843. From (7), C3 = 4.78 pF and C5 = 5.63 pF. Applying the same procedure for the imaginary part in (8) (5) that the gain can be varied by adjusting the resistance R6, and this has no effect upon the location of the pole of the filter. This resistance has been set to R6 = R7 = 20 k.
Regarding the fast shaper, the values have been set to: C0= 650 fF, R0 = 8 k, and C1 = 4 pF, providing a peaking time of 30 ns.

III. SINGLE EVENT EFFECTS RADIATION STUDY
The readout channel has been tested to analyze its robustness under irradiation conditions using a tool designed by some of the authors. The Analog FTU hardware debugging system, AFTU [20], is a software tool that allows circuit designers to evaluate the SEE sensitivity of analog/mixed signal circuits at transistor level. To this end, AFTU takes a Spectre-based netlist and automatically adds charge injection elements all over the circuit to emulate the effects of high-energy charged particle impacts without changing its functional behavior. The user can define a test campaign to simulate the influence of SEEs by means of three input configuration files. From them, AFTU creates an Ocean script-based file that manages a sensitivity analysis according to some predefined heuristics and parameters. The result of running the script is a file (.csv) that contains all the results, classified following the applied criteria settled by the user.
Since there are no memory elements in this design, the study of SEE will be focused on the effect of Single Event Transients (SET). For the proposed circuit, an "amplitude/pulse width" analog metric has been settled to detect potentially dangerous transient pulses, determining its maximum voltage deviation (from non-irradiated signal values) and maximum recovery times. The current sources used as charge injection elements follow the double exponential model [33], [34]. Standard formulas (9) where e is the electron charge,  is the Si density, Ep=3.6 eV is the e-h pair energy creation, and d=2 m is the recollection depth.
As previously stated, the impact of ionizing particles can generate charge injections into different nodes of the circuits, leading to the appearance of SET effects. The use of QFG has allowed the design of gain-boosting techniques in a very compact way. Nevertheless, the use of the QFG technique implies the existence of very high impedance nodes in which a transient effect can be particularly relevant, as it can last a large amount of time. Due to this situation, the study of these effects using AFTU to evaluate circuit robustness could be of great interest to ensure a proper functionality of the elements involved. Such a study to evaluate the effects of SETs over the QFG technique has not yet been performed, to our knowledge.
To this end, a representation of a pMOS transistor with its parasitic pn junctions, that can be affected by an impact of a particle, and all the possible current sources modelling charge injections [34] are shown in Fig. 4. For the case of an nMOS transistor, the model is similar but only sources that inject a current from drain/source to bulk are modelled. There are several blocks in which the QFG technique is applied: two in the CSA amplifier and four in each slow shaper amplifier (SHA1, SHA2). Impact simulations have been carried out for each QFG block of the circuit. For the sake of clarity, the results obtained for the study of the CSA blocks will be explained in detail, while a qualitative discussion of the effects in the SHA blocks will be included taking into account the previous study in the CSA.  The procedure followed is based on evaluating the nominal performance of the system and comparing it with the results after an impact in a QFG block. In this way, we can observe the outputs of the circuit and classify the different SET effects depending on their influence into four possible classes: I. Impacts with no influence at the output (Fig. 7a). II. A transient effect with recovery times shorter than the time between impacts (5 µs) (Fig. 7b). III. Impacts that generate large variations in the output voltage, affecting several consecutive impacts (Fig.  7c). IV. Impacts that cause the system to completely stop functioning as a detector (Fig. 7d).
The most relevant results from the simulations are summarized in Table I for the CSA amplifier, where the voltage deviation at the output of the system is quantified for class III effects and circuit malfunctions as a detector (class IV) are marked as an X for every transistor in which the impact has been emulated. A value of charge of 0.3 pC has been used as a worst-case injection, based on estimations for a similar technology studied in [35] and the previous work carried out in similar studies using AFTU [20], [36], applying the formulas in (9) and (10). This corresponds to a linear energy transfer (LET) of approximately 15 MeV-cm 2 /mg, which is less than the maximum expected for radiation environments such as the High-Luminosity Large Hadron Collider tracker at ATLAS or CMS [36]. The results of the rest of the blocks in the SHA op-amps are also summarized in Tables II and III.  From these results, it can be seen that the GBP block is more affected by impacts than the GBN scheme for every opamp. A possible solution to this effect can be to increase the value of the capacitor in the GB scheme, to decrease the voltage variation in the node which is affecting the circuit performance.
From simulations of impacts in the first CSA shaper, it can be seen how the circuit performance can be corrected by using a higher value of the capacitor. As an illustrative case, Fig. 8 represents the effect of an impact that generates a malfunction with C= 200 fF (nominal design value) and C=1.2 pF.

C=1.2pF (increased value)
Reference output signal In this way, the analysis using AFTU not only allows determining circuit vulnerabilities, but it can also be used to solve those vulnerabilities. By means of performing simulations for different sizes of the capacitor we can optimize the robustness of the GB blocks in the proposed scheme, determining an appropriate value. Of course, the larger the capacitor value, the more robust the circuit will be with respect to SET, at the cost of significantly increasing its area. The simulations carried out make it possible to select the minimum value of the QFG capacitors while maintaining robustness to radiation. In Tables IV and V, the effect of increasing the capacitor size is summarized for the GB blocks in the CSA amplifier.  (FIG. 5).

Cap value [fF]
Error class         200  III  -29  29  29  500  III  -25  25  29  800  III  -18  18  27  1200  III  -13  13  21 If we perform a similar analysis for the other two SHA opamps, each one with four GB blocks, we can also adjust the capacitor to an optimum value. This effect is summarized in Tables VI, VII, VIII and IX. As it can be noticed, we can correct some class IV errors and convert them into class III errors, using AFTU to optimize the capacitor size for the most sensitive GB blocks.  (FIG. 6).

Cap value [fF]
Error class V [mV] at the output for impacts in transistor      bis  bis  200  III  161  178  157  175  300  III  52  76  42  67  500  III  24  40  13  34  800  III  13  29  2  19  As a result of the performed study, the values of the capacitors have been selected for every QFG block to ensure that the front-end readout channel works properly as a detector. In this way, we are ensuring that impacts will not generate any class IV error at the output of the circuit. The capacitor values have been selected considering a trade-off between robustness and area occupation, allowing a maximum error of 100 mV in the worst cases (GBP blocks), and 40 mV in the GBN schemes. The final values implemented are summarized in Table X for each GB block of the scheme. In addition to these contributions, simulations to determine the minimum value of charge required to generate a voltage variation of at least 10 mV at the output have been performed, obtaining the results summarized in Table 11. As an example, if we consider the GBP block in the CSA amplifier for a capacitor value of 500 fF, any charge below 0.02 pC will not generate a variation at the output bigger than 10 mV. In this way, we can have an estimation of the "critical charge" for every GB block in the circuit for different sizes of capacitors.

IV. SIMULATION AND MEASUREMENTS
The front-end channel operates from a single supply voltage of 1.8 V. The microphotograph of the described circuit is shown in Fig. 9. The size of the channel is 525 µm x 290 µm, whereas the die size is 1.5 mm x 1.5 mm. The chip was manufactured via MOSIS service in IBM 180 nm CMOS technology. Due to the opaque passivation layer, only capacitors are shown. The chip also includes a test injection circuit, consisting of a small test capacitor, Ctest in Fig. 1, that receives a controlled amplitude square voltage signal from a signal generator. A charge Qin = Vtest x Ctest is injected at the input of CSA by applying a voltage step through the test capacitor.
The dimensions W/L = 750 µm/0.18 µm for the pMOS input transistor M1 of the CSA in Fig. 2 have been chosen according to the noise minimization guidelines for a detector capacitance of Cdet = 10 pF. This transistor is biased with a drain current of 1.125 mA, of which the additional biasing branch formed by M6 and M7 delivers 750 µA, and its transconductance gm1 is 18.3 mA/V. The simulated parameters of the CSA core amplifier are open loop voltage gain KV = 3.2 kV/V, GBW = 1.78 GHz (for a load capacitor of 1 pF) to meet the short timing requirements, and current consumption 1.275 mA (2.3 mW) including the QFG gain-boosting schemes and the source follower stage. Note that in Figure 10 at very low frequencies the magnitude presents a first-order high-pass behavior due to the quasi-floating gate technique used for the local feedback amplifier of the regulated cascode, which has no influence on the behavior of the circuit.  The charge sensitive amplifier presents a charge gain of approximately 2 mV/fC due to the feedback capacitor CF = 500 fF. It can be noted in Fig. 10 that the pulse height is about 57 mV, generated by an input test charge Qin = 30 fC, which is injected into the CSA input, giving the CSA an accurate charge-to-voltage conversion. In addition, the decay time is five times the time constant RF·CF for a nominal estimated value of the feedback resistance of 1.2 MΩ. Fig. 12 shows the time response of the analog channel to a signal charge of 45 fC, showing a peak height about 290 mV. The peaking time, which is the time when the shaper output reaches the peak amplitude, is about 400 ns. A small undershoot can be observed due to mismatch between resistances in the pole-zero cancellation circuit. The gain pulse of the slow path is around 6.5 mV/fC. Owing to the railto-rail output swing of the two-stage amplifier in Fig. 3, the dynamic range of the slow shaper is enhanced.   The output voltage of the slow path must be linear for the charge range of the detector Fig. 14 shows the energy response and the dynamic range obtained. The nonlinearity of the CSAslow-shaper has been found to be less than 1% over a 10-70 fC input charge range.

V. NOISE ANALYSIS
In order to analyze the noise characteristics of the design, the equivalent noise charge (ENC) is considered as it allows for direct comparison with the number of electrons released in the detector at the input of the CSA.
Most of the noise in a well-designed front-end system has its origins in the detector, the CSA input transistor, or the feedback resistance of the CSA. For a generic front-end electronics channel, and considering a simplified noise model, the ENC is given by: VOLUME XX, 2017 9 In this expression, α encompasses the noise components corresponding to detector leakage current, detector bias resistance RBIAS, and CSA feedback resistance, RF; ap is the white current noise coefficient, CG represents the gate capacitance of the CSA input transistor, β represents the CSA input transistor thermal noise component, aw is the white voltage noise coefficient, AF is the CSA input transistor 1/f noise coefficient and af represents the 1/f voltage noise coefficient. The coefficients ap, aw, and af, related to the shaper transmittance function H(s) and the CR-(RC) 4 complex filter are, respectively, 0.51, 0.91, and 0.53 [37]. Note that for M1 in strong inversion the β coefficient is proportional to (8kT)/3gm1.
The characteristics of the CSA input transistor M1 are crucial for achieving a good noise performance, thus special care must be taken when choosing its type, size, as well as biasing conditions. Thermal noise in the channel and flicker noise are the dominant noise contributors of M1. Given that a high input pulse rate requires a short peaking time, the thermal noise of the input transistor dominates the total ENC noise of the slow processing path. Furthermore, the 1/f noise coefficient AF of the pMOS input transistor of the CSA is lower than that of a nMOS transistor. The contribution of the thermal noise is proportional to the value of the total input capacitance CT, and inversely proportional to the square root of the transistor transconductance, gm1. Therefore, the thermal noise can be reduced by increasing the input transistor transconductance, while considering low power and low occupied silicon area requirements. In this work the front-end electronics has been optimized for detector capacitance of 10 pF. An equivalent noise charge of 466 electrons was measured for the slow path comprising a complex shaper.

VI. CONCLUSIONS
A single front-end channel built of two different parallel processing paths for silicon detectors readout is presented. The readout channel includes a charge sensitive amplifier, bandpass filters, and a pole-zero cancellation circuit. The system, realized in 180 nm CMOS technology, is capable of both time and amplitude measurement of charge-pulses delivered by semiconductor detectors. A 4th order complex shaper improves the signal to noise ratio and minimizes the ratio of pulse width to peaking time. The amplifier cores have been designed with gain-boosting techniques based on quasifloating gate transistors providing low noise, accurate amplitude measurements, and good resolution in the input pulse arrival time determination. Using an automatic SET simulation tool, the effect of possible impacts on the QFGs has been studied, proposing a method that allows selecting the design parameters of the QFGs to achieve a circuit resistant to radiation. The system has a large dynamic range and a power consumption of only 4.1 mW, even though the single channel is built of two different parallel processing paths.