Experimental Determination of Interface Trap Density and Fixed Positive Oxide charge in Commercial 4H-SiC Power MOSFETs

We measure interface trap density near the conduction band edge and fixed oxide charge in commercial, packaged, 4H-SiC 1.2 kV planar Power MOSFETs. These traps determine the device threshold voltage, performance, and reliability. The subthreshold slope is used to extract interface trap density at the SiO2-SiC interface near the conduction band edge from three vendors, which varies from 5.8×1012 to 9.3×1012 cm-2∙eV-1. Good agreement is obtained with threshold voltage measurements from 25°C to 150°C as devices with the highest interface trap densities exhibit the largest threshold voltage reduction over temperature. Fixed positive oxide charge, Not, balanced with interface traps and substrate doping, varies from 3.3×1012 cm-2 to 3.7×1012 cm-2. At high temperatures, electrons captured in interface traps emit to the conduction band and lower the threshold voltage together with fixed oxide charges, which are as high as interface trap densities. Thus, device design should be considered for a suitable threshold voltage to ensure the device does not operate in a Normally-ON condition and to protect against gate voltage surges. Therefore, more focus on characterization and reduction of the interface trap density and fixed oxide charge is needed to enable further improvement in effective electron mobility of SiC MOSFETs.


I. INTRODUCTION
SiC Power MOSFETs are efficient switching devices with low switching losses and high-power density over an extended temperature range [1]- [3]. SiC, similar to Si, uses thermally grown silicon dioxide (SiO2) as a native oxide. However, the gate oxide of SiC MOSFETs exhibits a higher density of trapped charges at or near the SiC-SiO2 interface. The high density of electrons in the interface traps (Dit) near the conduction band edge, along with fixed positive charges, Not, near the SiC-SiO2 interface create a design challenge for threshold voltage and cause reduced electron density in the conduction band. Furthermore, scattering of electrons in the channel results in a low effective electron mobility, a reduced current drive, and an increase in channel and ON resistance [4]- [7]. Post-oxidation annealing (POA) techniques with nitric oxide (NO), nitrous oxide (N2O), phosphosilicate glass (PSG), and phosphorus oxychloride (POCl3) have been employed to improve gate oxide quality and increase inversion electron mobility by passivating the SiC-SiO2 interface [8]- [16]. Recently, Kobayashi et al. [17] and Takichi et al. [18] have reported new approaches to reduce Dit and improve effective mobility by preventing oxidation of SiC during gate oxide formation.
The combination of extremely low intrinsic carrier density combined with p-well doping places the Fermi level near the conduction band edge in strong inversion, where the high values of Dit affects the threshold voltage and device reliability. The issues arising from the high Dit become complex when devices with dissimilar Dit operate at elevated temperature. Electrons trapped by interface traps emit back into the conduction band. This results in an uneven threshold voltage reduction and current drive. In a power module, where multiple devices are connected in parallel to share the current, the uneven threshold voltage reduction in paralleled devices results in uneven current sharing. The nonuniform current sharing can affect the long-term reliability of power modules. Even with reduction of Dit, the electron mobility is degraded by the scattering from the high density of fixed positive charges near the SiC-SiO2 interface. Although the origin of oxide charge has not been determined, a SiC-SiO2 transition layer with carbon clusters formed during the thermal oxidation process may be responsible for the donorlike defects [19]- [22].
In our work, we determine Dit and Not in commercially available 1.2 kV SiC Power MOSFETs. Transfer currentvoltage (I-V) characteristics in the subthreshold region are used to extract the Dit near the SiC conduction band edge, which are confirmed with high temperature measurements of the device threshold voltage. We extract Not for an assumed p-well doping density.

II. EXTRACTION METHOD FOR DIT
In order to examine the trap density at the interface of SiO2-SiC, we use the subthreshold characteristics. This permits the extraction of energy-dependent trap density by incorporating the surface potential derived from the subthreshold characteristics. We begin with the drain current in the subthreshold region [23], [24] where I0 is the current at VGS = 0 and VDS ≫ kT/q. IDM is the maximum drain current at zero surface potential (ϕS = 0) which incorporates VDS. The ideality factor n is given as where CD is the depletion capacitance, Cox is the oxide capacitance and Cit is the interface trap capacitance per unit area with the interface trap density In practice, Dit is extracted at several gate voltages, as a function of surface potential, within the subthreshold region. Fig. 1 shows the energy band diagram under weak inversion where the Fermi level (EF) is slightly above the intrinsic Fermi level at the surface (EiS). The traps in the range EF -EiS are filled with electrons and this range extends as the applied gate voltage increases to bring EF closer to the conduction band at the surface, ECS. The onset of inversion at ϕS = 2ϕF places the EF near the edge of ECS, where there is an increasing density of interface traps. The amount of the interface charge varies as the surface potential changes with the gate voltage. The surface potential is related to trap level, ET0, by the following expression: where ϕF is the Fermi potential. Both ϕS and ϕF are positive quantities in (4). The drain current value at a certain gate voltage at a fixed value of VDS can be expressed as the last term in (1). The threshold voltage is set at ϕS = 2ϕF in (1), such that Combining (1) and (5) leads to ϕS with the current level IDS (ϕS) measured at a certain gate voltage as where the surface potential is in the range ϕF < ϕS < 2ϕF. IDS (2ϕF) is the drain current at threshold voltage which is determined by the linear extrapolation method from the measurement data. Finally, from (4) and (6), ECS -ET0 is expressed as a function of surface potential:

A. INTERFACE TRAP DENSITY DISTRIBUTUION EXTRACTION
We examine commercial SiC planar power MOSFETs. The devices under test (DUTs) are from three vendors, referred to as C, D, and E, which are rated at 1.2 kV and 7 -12 A. Five devices from each vendor are selected with threshold voltage variation less than 0.05 V. All the electrical characterizations are performed with a Keysight B1505A analyzer. Fig. 2 shows IDS-VGS characteristics with a drain voltage of 0.1 V at room temperature. Threshold voltage at ϕS = 2ϕF is determined by a linear extrapolation (LE) method [25]. From the subthreshold curves, the ideality factors n can be determined with (2) as a function of VGS. Several gate voltages are selected in the subthreshold region. Dit, as a function of trap energy, is obtained with (3) and (7). To determine Cox, oxide thicknesses are estimated by voltage ramp-to-breakdown measurements at room temperature as shown in Fig. 3. With an oxide breakdown field of 11 MV/cm [26,27], DUT oxide thickness, from vendors C, D, and E, are 456, 452, and 389 Å, respectively. A p-type base doping concentration, NA = 2×10 17 cm -3 has been assumed for all samples.     The post oxidation anneal (POA) of the gate oxide plays a role in determining the Dit. Studies on the SiO2-SiC interface demonstrate N2O and NO anneal work best for the Si-face of 4H-SiC, which has been used in industry [28], [29]. N2O and NO treated MOS capacitors, compared with simply oxidized MOS capacitors, exhibited approximately 83 percent and 90 percent lower Dit at 0.1 eV below the conduction band, respectively [29]. Our Dit values are higher than reported VOLUME XX, 2017 9 values in [29] since the DUTs are commercial MOSFETs with heavily implanted Al p-base regions.

B. TEMPERATURE-DEPENDENT THRESHOLD VOLTAGE
Threshold voltages are measured as a function of temperature in order to study the performance of DUTs with different Dit values at high temperature. The devices were placed in an oven and measured at 25°C intervals from room temperature to 150°C. IDS-VGS transfer characteristics as a function of temperature are shown in Fig. 6 (a). As the temperature increases, the curves shift in the negative direction in all samples. Noticeable difference in subthreshold characteristics between vendors is observed. Subthreshold swing (SS) which is the inverse slope of the log (IDS) versus VGS in the subthreshold region, is a simple indicator for Dit, as shown in (2) and (3). Generally, the SS is higher in devices with larger Dit, which shows a gradual subthreshold slope. Fig. 6 (a) shows devices from vendor C present gradual subthreshold slopes with larger shift in IDS-VGS curve over the given temperature range. Whereas subthreshold slopes of devices from vendor E are steep and shift over the temperature is smaller. This indicates devices from vendor C have higher Dit. Vendor D is not shown for clarity but is located between the two vendors with medium subthreshold slope. Fig. 6 (b) shows the threshold voltage reduction with temperature. Devices from vendor C show the largest variation in threshold voltage with the temperature change as expected from the variation in I-V curves in Fig. 6 (a). High threshold voltage at 150°C for vendor C may be seen as an advantage from the point of view of safe operation of the circuit.
When threshold voltage at room temperature is taken as a reference, the threshold voltage reductions at 150°C in devices from vendors C, D, and E are 3.4 V, 2.6 V, and 1.7 V, respectively. The threshold voltage reduction at high temperature is primarily due to release of trapped electrons in interface states to the conduction band. The threshold voltage is defined as Consequently, the less negative charges in the interface traps and more carriers in the conduction band result in threshold voltage reduction. Threshold voltage reduction from room temperature to 150°C, ∆VTH, can be described as where variations in QF with temperature is assumed to be small. The first three terms in (8) involve temperature changes due to ϕF and bandgap narrowing and amount to threshold voltage reduction of only 0.19 V, 0.19 V, and 0.18 V for vendors C, D and E, respectively. Thus, the threshold voltage shift in experimental data is assumed to largely come from the where the threshold voltage is determined at ϕS = 2ϕF. The Fermi potential change (∆ϕF) from room temperature (ϕF,RT) to 150°C (ϕF,HT) is depicted in Fig. 7 (a) [30]. At elevated temperature, EF is closer to the Ei at the bulk due to increasing intrinsic carrier density. Therefore, less band bending is required to induce a sufficient carrier density in the conduction band at the surface. Trapped electrons above the EF emit back to the conduction band by the amount of Fermi potential change which results in fewer negative charges at the interface. ∆ϕF is the same for all samples as 0.085 V since we assume the same p-base doping for all DUTs. The effect of Fermi-Dirac distribution broadening at high temperature is neglected in the calculation. Nit can be obtained by two methods, either by integrating Dit within the potential change using the Dit distribution in the previous section (method A), or from temperature-dependent threshold voltage reduction (method B). Table I shows the extracted Nit values from two methods. Nit extracted from method B is indeed the integration of Dit from the conduction band edge where EF locates at room temperature (ECS -ET0 ≅ 0 eV) to ∆ϕF (ECS -ET0 ≅ 0.085 eV). Therefore, in order to integrate Dit from the conduction band edge through ∆ϕF, method A has been further extended to estimate Dit in the strong inversion. IDS (2ϕF) in (7) is raised close to the inversion point, ECS -ET0 ≅ 0 eV. Nit from method A in Table I is the integrated areas under each Dit curve in Fig. 7 (b). Nit values extracted from both the techniques are in good agreement.
The number of fixed charges per unit area, Not (= QF/q), is also calculated from (8) by subtracting the contribution of interface charges at room temperature. Here we assumed that the negative trapped charges within 0.3 eV of the conduction band contribute most of the negative charge in Nit. Therefore, integration is performed from ECS to ECS -0.3 eV for each vendor in Fig. 7. The value assumed for the p-well doping NA is 2×10 17 cm -3 as mentioned previously. Extracted Nit and Not values from DUTs are summarized in Table I. Although this method may provide relative comparison between devices and across the vendors, extracted values are not highly accurate compared to the real values since occupied trap density, Nit, is unlikely to be zero at T=150 °C. Therefore, our experimental condition gives a lower bound on Nit and Not.

IV. CONCLUSIONS
We describe a method to extract interface trap density, Dit, and oxide trap density, Not, on 1.2 kV commercial, packaged 4H-SiC Power MOSFETs since there is a delicate balance between the interface and oxide trap densities together with the design of the impurity profile to meet performance and reliability at room and elevated temperatures. These devices are under consideration for electric vehicles (EVs) and solar energy applications. A subthreshold slope method, combined with temperature measurements of threshold voltage, is used to determine the above-mentioned trap densities, as shown in Table I. Since process information is often not available from vendors, in our studies we estimated a gate oxide thickness with ramp-tobreakdown measurement and assumed a substrate doping of 2×10 17 cm -3 . The results in Table I indicate the significant differences among three vendors. Five devices, each from three different vendors C, D, and E, are used in the study. For example, a threshold voltage reduction over a temperature range from 25°C to 150°C of 3.4 V for vendor C is correlated with the highest integrated interface trap density. In terms of device operation, under fast switching with high switching losses, increasing junction temperatures cause a negative shift in threshold voltage. The threshold voltage should be carefully chosen to be higher than a critical value for safe operation of the circuit.
At high temperatures, electrons trapped in interface states emit to the conduction band and lower the threshold voltage together with fixed oxide charges, which are as high as interface trap densities. Thus, the impurity profile must be adjusted to maintain a threshold voltage to ensure the device does not operate in a Normally-ON condition and to protect against gate voltage surges. Therefore, more focus on characterization and reduction of the interface trap density and fixed oxide charge is needed to enable further improvement in effective electron mobility of SiC MOSFETs. Moreover, in high power applications where multiple MOSFETs are paralleled within a power module and multiple power modules are used, current sharing across devices should be uniform for long-term reliability. Otherwise, devices with low threshold voltage will carry a larger share of the total current. He joined the Electrical and Computer Engineering Department at The Ohio State University in 2010. His teaching areas concern analysis and design of integrated circuits for systems applications and the physics of semiconductor devices. In the years, he has been in industry and the university, he has over 300 papers and 28 U. S. Patents with colleagues and students. Today, these WBG semiconductors are being employed globally to improve efficiency and reduce power consumption in systems such as power supplies, solar inverters, and motor drives.
Previously, Dr. Agarwal was a Fellow at Northrop Grumman Science and Technology Center, Pittsburgh (1990Pittsburgh ( -1999. While at Northrop Grumman he led research activities on radio frequency Silicon and Silicon-Germanium transistors. He was also instrumental in solving a large number of fundamental issues relating to WBG technologies. Prior to joining Northrop Grumman, Dr. Agarwal held various teaching and research positions (1984)(1985)(1986)(1987)(1988)(1989)(1990) including Associate Professor in Allahabad, India and Member of the Technical Staff at AT&T Bell Laboratories, Murray Hill, NJ. While at Bell Labs he was involved in the development of Gallium-Arsenide digital circuits for fiber-optic communications.
Dr. Agarwal received his PhD degree in Electrical Engineering from Lehigh University, Pa in 1984; MS degree in Electrical Engineering from the University of Tennessee Space Institute (UTSI) in 1980; and Bachelor of Science in Electrical Engineering from MNR Engineering College, University of Allahabad, India in 1978. He jointly holds more than 60 patents, has co-authored more than 300 research papers, co-edited a book on Silicon Carbide Technology, co-authored five book chapters and was elected an IEEE Fellow in January 2012 for contributions to Wide Band Gap technologies.
As a leading research scientist in this area, Dr. Agarwal's life goal has been to successfully commercialize WBG power devices to resurrect the domestic power electronics industry while educating the next generation of researchers. This will ultimately enable the creation of high-quality manufacturing jobs in the US while perpetuating a high-tech US workforce.