Gate Driver for Wide-Bandgap Power Semiconductors With Small Negative Spike and Switching Ringing in Zero-Voltage Switching Circuit

Because SiC MOSFET-based zero-voltage switching (ZVS) power converter circuits provide high-speed switching, high power density and high efficiency can be achieved. However, an undesired negative spike is formed at the gate-source voltage owing to the crosstalk phenomenon in leg structures, such as half-bridge switch configurations, during high-speed switching. Additionally, ringing voltage occurs owing to resonance between the snubber capacitor and the common source inductance of the SiC MOSFET. Because SiC MOSFETs have a lower gate voltage rating than conventional Si devices, it is essential to reduce the negative spike and ringing voltages to ensure reliability. In this paper, the gate driver circuit is proposed for reducing the negative spike and ringing voltages of the gate-source in ZVS circuits. Because the proposed gate driver circuit provides an effective impedance path for each section through an active switch, a stable driving voltage range of the gate-source can be achieved. To verify the proposed gate driver circuit, an accurate simulation model of the 3-pin SiC MOSFET package is proposed, and the validity of the proposed model is verified through comparison of the simulated waveforms with experimental waveforms. The performance of the proposed gate driver circuit is verified through PSpice simulation.


I. INTRODUCTION
Power converters are key components in various industrial applications, such as renewable energy, electric transportation, and aerospace systems. Accordingly, high-speed switching techniques for switching devices are being implemented to achieve miniaturization, high efficiency, and weight reduction of power converters. Examples include widely applied soft-switching techniques, which use the resonance of a capacitor and an inductor. Soft switching technique enable switching devices to achieve high-speed switching and increased efficiency by reducing switching losses through zero-voltage or zero-current transitions during The associate editor coordinating the review of this manuscript and approving it for publication was Francesco G. Della Corte . on/off operations [1]- [7]. Additionally, high-speed switching can be realized by replacing the conventional silicon (Si)-based switching devices with wide-bandgap (WBG) devices. WBG devices have superior physical properties to Si-based devices and offer the advantages of fast switching speed and low conduction resistance [6]- [11]. Therefore, high power density and high efficiency can be achieved by concurrently using a WBG device and applying a softswitching technique.
However, during high-speed switching, undesirable crosstalk occurs in leg structures, such as half-bridge switch configurations [12]- [23]. Crosstalk is a phenomenon in which positive and negative spikes appear in the gate-source voltage owing to the current flowing into the Miller capacitor in the dv/dt section of the drain-source during turn-on and  [24]- [26]. turn-off. As shown in Table 1, because SiC MOSFETs have a lower threshold voltage than Si devices, unwanted turn-on may occur because of positive spikes. Therefore, this may result in an increase in switching loss and, in the worst case, switch burnout [14], [15]. Additionally, because SiC MOSFETs have low gate-source negative voltage rating, the rating may be exceeded owing to a negative spike by crosstalk, which results in switch burnout [22], [23].
In [15]- [17], negative offset voltage was applied during turn-off to reduce the effect of the positive spike voltage. If negative offset voltage is applied during turn-off, the threshold voltage margin for a positive spike can be obtained.
In [17]- [21], the positive spike voltage was reduced by adding an active Miller clamp to the gate-source. Because the active Miller clamp technique is operated in the dead time period after turn-off, it does not affect the switching performance. Additionally, it provides a low-impedance path, and the positive spike voltage formed at the gate-source can be reduced. However, conventional methods for reducing the positive spike caused by crosstalk cannot decrease the negative spike voltage but can worsen it instead. In [22] and [23], the positive and negative spike voltages caused by crosstalk were reduced by adding an auxiliary circuit to the gate-source. However, the ringing voltage due to inductances such as common source inductance (CSI) included in the gate loop was not fully considered.
Meanwhile, isolation converters, such as series-resonant, parallel-resonant, phase-shift full-bridge, dual-active-bridge, and LLC converters, can achieve zero-voltage switching (ZVS) over the designed frequency range [1]- [7]. However, turn-off loss still exists because hard switching occurs at turn-off [1], [6]. To solve this problem, the turn-off loss can be reduced by adding additional snubber capacitors at both sides of the switches [2], [27]- [29]. However, a ZVS with a snubber capacitor suffers from a resonance problem between the CSI and snubber capacitor [30]- [32]. For 3-pin package SiC MOSFET devices particularly, because CSI is unavoidably included in gate-source loops, ringing voltage occurs at the gate-source owing to the resonance [33], [34]. Because SiC MOSFETs have low gate-source threshold voltage and low negative voltage rating, as shown in Table 1, the negative spike and ringing voltages must be reduced to ensure the reliability of the gate driver circuit.
In this paper, we propose a new gate driver circuit for a SiC MOSFET-based ZVS circuit. It can reduce both the negative spike voltage caused by crosstalk and the ringing voltage caused by the resonance of the snubber capacitor and CSI. Before proposing the gate driver circuit, a detailed mode analysis of the dead time period is performed, and the gate loop is analyzed. For accurately analyzing the proposed gate driver circuit, a simulation model that reflects the dynamic characteristics of a 3-pin SiC MOSFET is proposed. Additionally, the proposed simulation model is validated through comparison with actual experimental results. The performance of the proposed gate driver circuit is verified through PSpice simulation.

II. GATE-SOURCE MODE ANALYSIS FOR ZVS CIRCUIT
In this section, a detailed mode analysis is conducted to analyze the causes of the negative spike and ringing voltages of the gate-source. Figure 1 shows the equivalent ZVS circuit, in which the parasitic components of the 3-pin package SiC MOSFET are included. Here, V DC represents the input voltage of the ZVS circuit; C S_H and C S_L denote the snubber capacitors connected in parallel with high and low switches; C ds , C dg , and C gs represent parasitic capacitors of the switch; and L s denotes the CSI by the inner bonding wire and source terminal of the package. D in denotes the body diode of the switch, R d is the equivalent resistance of the body diode, and R g(in) is the internal gate resistance. R g_H and R g_L represent the external gate resistances, V drv_H and V drv_L are the input voltages of the gate driver, and i load is the load current. Figure 2 shows the operation waveform during the dead time period from the turn-off of the high switch to the section in which the body diode of the low-switch conducts. Figure 3 shows the operation mode for each section from t 0 to t 4 . Here, i sw_H represents the current of the high switch and i D is the current of the body diode. i Cds , i Cdg , and i Cgs denote the VOLUME 9, 2021 currents flowing through each parasitic capacitor, and i Rg is the current flowing through the gate resistor. V Cs_H and i Cs_H , and V Cs_L and i Cs_L represent the voltages and currents of the high-and low-side snubber capacitors, respectively, and V Ls denotes the voltage formed across the CSI. V Cgs represents the voltage across the input capacitor C gs , and V GS_H and V GS_L denote the gate-source voltages of the high-and lowside switches, respectively. V P represents the Miller plateau voltage of the switch, and V th denotes the threshold voltage of the switch.

A. ANALYZING THE NEGATIVE SPIKE VOLTAGE OF GATE-SOURCE
Before t 0 , V GS_H is 18 V and V GS_L is 0 V; thus, the high switch is turned on, and the low switch is turned off. Therefore, in this section, power is transmitted to the load through the high switch. At t 0 , V GS_H decreases to V P by the turn-off signal of the high-side gate driver, and the operation region of the high switch moves from the linear region to saturation region. Therefore, although V GS_H decreases, the channel of the high switch is maintained because the operating region of the switch is located in the saturation region, and i sw_H is equal to i load .

2) STAGE 2 (t 1 -t 2 )
In the section from V p to V th of V GS_H , i sw_H starts to decrease at t 1 and the high swich completely turns off at t 2 . Therefore, the output capacitors of the high and low switches are charged  and discharged by i load as i sw_H decreases. Additionally, at t 1 , V Cs_H and V Cs_L start to rise and fall, and because the current and voltage of the switch intersect in the corresponding section, turn-off loss occurs in the high switch. Figure 4 shows the current path formed in the gate loop of the low switch from t 1 to t 4 . At t 1 , V Cds drops to -dv/dt by the discharge of C ds and C S_L of the low switch, and the discharge current i Cds gradually increases. Simultaneously, according to the relationship among V Cds , V Cdg , and V Cgs , as shown in (1), V Cdg and V Cgs decrease in proportion to V Cds . Therefore, the current paths of i Cdg and i Cgs are formed in the discharge direction, as shown in Figure 4, and i Cdg is equal to the sum of i Rg and i Cgs , as shown in (2).
Therefore, because of the current flowing through the gate loop, a negative spike starts to form in V GS_L and V Cgs , in proportion to the voltage drops of R g_L and R g(in) , as shown in the following equations: At t 2 , the high switch is turned off, and most of the load current flows through C S_H and C S_L . Because the charging and discharging of the snubber capacitors are not completed in this section, C S_H and C S_L are continuously charged and discharged from the load current in the same way as in Stage 2.

4) STAGE 4 (t 3 -t 4 )
At t 3 , V ds of the low switch is sufficiently discharged to be 10 V or less. The device used in this study is the same as the SiC MOSFET in Table 1 (SCTW90N65G2V), and Figure 5 shows the capacitance of the device according to drain-source voltage. As shown in the figure, when the drain-source voltage is less than 10 V, C ds and C dg increase rapidly, and the impedance decreases. Therefore, the slopes of i Cds and i Cdg increase rapidly in this section, and i Rg and i Cgs increase in proportion to i Cdg , as shown in (2). Accordingly, a negative spike with a sharp slope is formed in V GS_L and V Cgs . Figure 6 shows the operation mode from t 4 to t 8 . At t 4 , V Cds is formed as −V F , and thus D in conducts. Based on these characteristics, ZVS is achieved during turn-on.

1) STAGE 5 (t 4 -t 5 )
Because most of the load current flows through D in after t 4 , i D increases to i load . Owing to the increase in i D , a negative voltage is formed in L S by −di/dt. Accordingly, V Cs_L decreases by −V Ls and reaches a minimum voltage, and V Cs_H increases by V Ls and reaches a maximum voltage. Therefore, overshoot and undershoot occur in V Cs_H and V Cs_L at t 5 , and dv/dt equals 0; hence, i Cs_H and i Cs_L become 0 A.
2) STAGE 6 (t 5 -t 6 ) From t 5 to t 6 , V Cs_L rises to −V F , and V Cs_H falls to V DC + V F , returning to the same voltage as that at t 4 . Simultaneously, the current direction of the snubber capacitor is reversed by dv/dt of V Cs_H and V Cs_L . Therefore, as shown in (5), i D increases by the current of the snubber capacitor and reaches a maximum value at t 6 . Accordingly, di/dt of i D becomes 0 at t 6 , and thus V Ls rises to 0 V: 3) STAGE 7 (t 6 -t 7 ) At t 6 , i D is formed to a maximum value because of the current of the snubber capacitor, and at t 7 , i D returns to i load . Simultaneously, V Ls increases by +di/dt owing to the decrease in i D . Accordingly, V Cs_L increases and V Cs_H decreases by V Ls . Therefore, at t 7 , dv/dt of V Cs_H and V Cs_L become 0; thus, i Cs_H and i Cs_L become 0 A.

4) STAGE 8 (t 7 -t 8 )
At t 7 , V Cs_L is equal to −V F , and V Cs_H is equal to V DC +V F . The current direction of the snubber capacitor is reversed after t 7 by dv/dt of V Cs_H and V Cs_L . Therefore, as shown in (6), i D decreases by the snubber capacitor current and reaches a minimum value at t 8 . Accordingly, di/dt of i D becomes 0 at t 8 ; thus, V Ls drops to 0 V.
Through mode analysis from Stages 5 to 8, the power loop can be simplified, as shown in Figure 7(a). A resonance is induced between the snubber capacitors and L S after the body diode conducts. Consequently, the ringing voltage with a resonance frequency occurs in V Ls , i Cs_H , and i Cs_L , as follows: The gate loop can be equalized as shown in Figure 7(b), and ringing occurs at V GS_L as a result of V Ls , as follows:

III. GATE LOOP ANALYSIS FOR RELIABILITY
In this section, a detailed gate loop analysis is performed to analyze the physical relationship between the characteristics of a 3-pin SiC MOSFET and passive elements of the gate driver. Figure 8 shows the operation waveform according to the gate resistance under the same load conditions. Between t 1 and t 4 , negative spike voltages are formed in V GS_L and V Cgs by the current formed in the negative direction of the gate loop. Because the negative spike voltage is generated by the voltage drop of the gate resistance, as shown in (3) and (4), the smaller the gate resistance, the lower the negative spike voltage. Between t 4 and t 8 , the ringing voltage occurs in V GS_L because of the resonance between the snubber capacitors and L s . The ringing voltage formed in V GS_L is dominantly affected by the ringing voltage of V Ls , as shown in (8). However, V Cgs varies according to the magnitude of the gate resistance, as shown in Figure 8. A detailed analysis of these relationships is provided in the following.

A. DETAILED ANALYSIS OF GATE LOOP BETWEEN t 4 AND t 8 1) STAGE A (t 4 -t 6 )
As i D increases, i Cds and i Cdg flow along the path shown in Figure 9(a). Therefore, the resulting V Cds and V Cdg are negative, and V Cgs is determined accordingly. Here, V Cds changes depending on the load current. When the load condition is equal, V Cgs is more affected by the change in V Cdg . Notably, V Cdg is formed by the i Rg flowing through the gate resistor, and the magnitude of i Rg increases when the gate resistance is small, as shown in Figure 8. Therefore, when R g_L is small, as shown in Figure 8(a), V Cdg increases to a negative value smaller than V Cds , and, consequently, V Cgs increases to a positive value. However, if R g_L is large, as shown in Figure 8(b), V Cgs is formed as a negative value because V Cdg is higher than V Cds .

2) STAGE B (t 6 -t 8 )
In contrast with Stage A, i D decreases; thus, i Cds and i Cdg flow in the path shown in Figure 9 (b). Therefore, V Cds and V Cdg are charged in the positive direction. In this section, V Cdg increases more than V Cds regardless of the gate resistance, and the variation in V Cdg is high when R g_L is small, as shown in Figure 8. Thus, V Cgs drops to a negative value in both cases. Consequently, the smaller the gate resistance, the greater the variation in V Cgs .  Generally, the reliability of the gate-source voltage can be estimated through V GS_L , which is the shortest measurable point externally. However, although V GS_L exceeds the gate  threshold voltage, the channel current of the low switch (i sw_L ) does not flow, as shown in Figure 10(b). The reason behind this phenomenon is that V Cgs does not exceed the threshold voltage. Meanwhile, a large ringing voltage is generated in V Cgs owing to the small gate resistance, as shown in Figure 10(a). This results in an unexpected turn-on because the ring voltage of V Cgs exceeds the threshold voltage. Therefore, the reliability of gate-source voltages cannot be determined by externally measurable points (V GS_L ), and it is important to secure V Cgs in a safe range.

IV. PROPOSED GATE DRIVER CIRCUIT FOR IMPROVING RELIABILITY
As analyzed in Section 3, a conventional gate driver circuit with a single-gate resistor has unavoidable performance limitations owing to the trade-off relationship between the negative spike voltage and ringing voltage. Therefore, we propose a gate driver circuit in this section to reduce the negative spike and ringing voltages simultaneously and detail the operation of the proposed circuit. Figure 11 shows the proposed gate driver circuit. D off , R g(off ) , and S off represent a diode, resistor, and N-channel MOSFET, respectively, for the turn-off path. D NV and S NV denote a diode and P-channel MOSFET for reducing the negative spike voltage, respectively. V drv_off and V drv_NV represent the gate driving voltages for the S off and S NV switches, respectively. The proposed circuit maintains small and large gate resistance when negative spike voltage and ringing voltage occur, respectively. This can be realized by providing an effective impedance path for each section through the active switch (S off , S NV ). Through this operation, the negative spike and ringing of V Cgs can be simultaneously reduced. Figure 12 shows the operation waveform of the proposed gate driver circuit, which consists of three operation modes, as shown in Figure 13. Before t 0 , the low switch is turned on, and S off and S NV are turned off. Each operation mode is described as follows. The equivalent circuit of Mode 1 is shown in Figure 13(a). As V drv_L changes to 0 V at t 0 , V Cgs is discharged. Here, turn-off loss occurs in the low switch, as described in Stage 2 of Section 2. To reduce the switching loss, it is better to have a small gate resistance for fast turn-off. After t 0 , S off is turned on, and the discharge path of V Cgs is blocked by D NV . Therefore, V Cgs is discharged through R g_L or through a path leading to D off , R g(off ) , and S off . Simultaneously, because R off is smaller than R g_L , V Cgs is mostly discharged through R g(off ) and S off .

2) MODE 2 (t 1 -t 2 )
At t 1 and t 2 , a negative spike voltage is formed by the current flowing through the gate loop. Because a small impedance can lower the negative spike voltage, S NV and D NV should be selected as having a small impedance. As shown in Figure 13(b), S off is turned off, and S NV is turned on. Additionally, the current path is blocked by D off . Therefore, the gate-loop current flows through the R g_L path or S NV path. Simultaneously, because the impedance of the path from S NV to D NV is relatively small, most of the current flows through this path.

3) MODE 3 (t 2 -t 3 )
In this section, the ringing voltage is formed after the body diode conducts. The ringing voltage is generated by V Ls and can be reduced through a large gate resistance. As shown in Figure 13(c), S off and S NV are turned off, and the bidirectional current due to ringing is blocked by the body-diodes of S off and S NV and diodes D off and D NV . Therefore, the ringing current only flows through R g_L . To reduce the ringing voltage, a high resistance should be selected for R g_L . Because the switching time between Modes 2 and 3 is short, D NV must have a fast reverse recovery time.
Using the proposed gate driver circuit, fast turn-off to reduce switching loss is realized in Mode 1, and the negative spike voltage is reduced through a small impedance path in Mode 2. Additionally, the ringing voltage is reduced by the large gate resistance in Mode 3.

V. VERIFICATION OF THE PROPOSED GATE DRIVER CIRCUIT
To verify the effectiveness of the proposed gate driver circuit, a PSpice simulation was performed. First, to apply the characteristics of CSI and the internal capacitances of the device, a simulation model for 3-pin SiC MOSFET was proposed. The proposed gate driver circuit was validated by comparing its performance with that of a conventional circuit.

A. SIMULATION MODEL OF A 3-PIN SiC MOSFET
Typically, the switch model applies the spice model provided by the manufacturer. However, in the conventional spice model, the voltage of the parasitic components cannot be measured because its properties are already mathematically considered in the spice model. Therefore, we built and applied VOLUME 9, 2021  a switch model that can measure the voltage of the parasitic components externally, as shown in Figure 14. Figure 15 shows the experimental and simulation waveforms of the ZVS circuit. The negative spike voltage of the simulation waveform is −7 V, which is the same as that of the experimental waveform. Additionally, the maximum voltage is 19.1 V, which has only a 1% error compared with the experimental result. Based on this result, the validity of the switch model is verified, and it confirms that the analysis resultant with simulation will be equal to the experiment.  Figure 16 shows the simulation configuration of the 2 kW half-bridge ZVS circuit to which the proposed gate driver is applied. The detailed system parameters are presented in Table 2. Schottky diodes with fast reverse recovery time are applied at D off and D NV , and switch devices with small R ds(on) are applied to the N-channel MOSFET (S off ) and P-channel MOSFET (S NV ) .

B. SIMULATION RESULTS
The operation waveform from turn-off to turn-on of the proposed gate driver circuit is shown in Figure 17. In the proposed circuit, a designed effective impedance path is provided for each section by V drv_off and V drv_NV . Figure 18(a) shows the results of the conventional gate driver composed of a single resistor. If the gate resistance is low, the negative spike voltage is reduced, but a considerably high ringing voltage appears. However, if the gate resistance  is high, the ringing voltage is reduced, but the negative spike voltage increases. Figure 18(b) shows the result of the proposed gate driver circuit; a small negative spike and ringing voltages are evident. Therefore, it is possible to secure a stable driving voltage range using the proposed circuit. Figure 19 shows a magnified waveform of the negative spike and ringing voltages in Figure 18. In Figure 19(a), when the gate resistance is low, the negative spike voltage is −2.3 V, and the peak-to-peak of the ringing voltage is 22.5 V. When the gate resistance is high, the negative spike voltage is −6.5 V, and the peak-to-peak of the ringing voltage is 0.66 V. However, in the proposed circuit, the negative spike voltage is −1.2 V, and the peak-to-peak of the ringing voltage is 0.83 V, as shown in Figure 19(b). The performance comparison results are arranged in the Table 3. Consequently, the negative spike voltage is reduced by more than 81%, and the peak-to-peak of the ringing voltage decreases by more than 96% compared with the conventional circuit.

VI. CONCLUSION
In this paper, we proposed a gate driver circuit for reducing the negative spike and ringing voltages of the gate-source in a SiC MOSFET based ZVS circuit. By analyzing the detailed operating principles of the dead-time interval, the relationship between the parasitic components of a 3-pin SiC MOSFET and ZVS circuit parameters was determined.
To realize and analyze the precise operational characteristics of the 3-pin SiC MOSFET, we fabricated a switch model and demonstrated the validity of the model by comparing the simulation and experimental waveforms. The proposed gate driver circuit provided an effective impedance path for the gate loop through two additional active switches, and a stable driving range of the gate-source voltage could be secured. The performance of the proposed circuit was verified through PSpice simulation, and the negative spike voltage reduced by 81% and the ringing voltage by more than 96% compared with the conventional gate driver composed of a single gate resistor.