On the gm-Boosted Miller-Effect Minimized Inverter-Cascode Transimpedance Amplifier for Sensor Applications

This paper presents the small-signal operation of a gm-boosted inverter-cascode transimpedance amplifier which has not been reported previously and whose comprehensive analysis is not available in any reported article or text-book. A simplified sequential equivalent-circuit method is employed which eliminates the need for complicated circuit analysis techniques. The analysis shows that the gain and the gain-bandwidth of the gm-boosted inverter-cascode transimpedance-amplifier is enhanced by the gain of the gm-boosting amplifier. This is due to the increased output impedance of the TIA, and, the reduced input-referred miller-effect capacitance through miller-effect trade-off employing the gm-boosting loop. To verify the actual performance improvement achieved, circuit simulation results as well as measured experimental results are also provided.


I. INTRODUCTION
Transimpedance amplifiers (TIAs) are today one of the most crucial front-end analog conditioning circuits particularly for meeting the challenging current-sensing specifications in electronic systems, sensor and biomedical applications with nano-and pico-ampere sensed currents. This is in addition to the well-established traditional broadband fibre-optic storage and optical transceiver applications which employ inductive bandwidth enhancements. Many TIA designs in sensor and biomedical application require very high gain along-with low-bandwidth due to the slowly varying signals in such applications. Comparative reviews of many possible TIA topologies have been discussed by authors in [1,2]. Nano-pore DNA analysis [3,4] using solid-state nanopore (diameter ≤ 30nm) requires TIAs with very high gain and low bandwidth. In addition, the frontends of many other slowly-varying transducer applications such as radiation sensor [5] and pressure sensor [6] mostly require high gain TIAs. One well-known technique to enhance the gain of amplifiers is by employing g m -boosted cascoding devices. The gm-boosting technique has been employed in many analog building blocks such as transconductance-amplifiers [7], RF-frontend LNA [8], RF mixers [9] and so forth. The 2nd author recently reported numerous g m -boosted cascode structures [10] as well as a g m -boosted source follower structure [11]. However, the employment of g m -boosting in TIA designs have still not been fully explored as evident from the comparative studies in [1,2]. TIAs being a sub-topic in feed-back amplifier design it has also not been discussed in detail in the available popular analog CMOS text-books [12] , [13], [14], [15], [16] and other avenues. Improvement of the intrinsic-gain, output-impedance and band-width through g m -boosting can further enhance the performance of TIAs. The inverter-cascode TIA is an well-known TIA topology for high-gain biomedical applications. In this context, the implementation and comprehensive small-signal mid-band characteristics of a g m -boosted inverter-cascode TIA is investigated in this work. The complete circuit analysis of a g m -boosted inverter-cascode TIA has not been reported before. Like several recent articles by the 2nd author, complete mid-band derivations of the g m -boosted invertercascode TIA is developed using a simplified inspection technique [10] which was not reported before. Elementary circuit transformations [17] along with suitable use of Norton amplifier model [18] is employed for a "pictorial" transformation based mid-band gain expression derivation. In order to provide a verification of the design improvements achieved by the g m -boosting, comparison with the ordinary inverter-cascode TIA is also provided through circuit simulations and experimental results. Standard integrated circuit symbols [12], [13], [15], [16] have been utilized for all the MOSFET device parameters in the small-signal analysis following the general convention for microelectronic circuit analysis. As a note on using clearly-defined composite current/voltage notations in the derivations, it is to be mentioned that, all the voltages and currents in lower-case alphabets alongwith upper-case subscripts are quantities that have both a large-signal DC-bias along-with a small-signal (AC) variation superimposed on it. Also, all the upper-case voltage/current notations along-with upper-case subscripts are large-signal DC quantities. And, finally, all the lowercase voltage/current symbols along-with lower-case subscripts are AC values. The topology of the standard inverter-cascode TIA with resistor-feedback biasing is shown in the Fig. 1(a) where cascoding is employed to reduce the input referred miller capacitance for the TIA. Next, the Fig. 1(b) shows the circuit topology of the proposed g m -boosted invertercascode TIA with both resistor feed-back and Quasifloating-gate (QFG) [19,20] biasing options. Here AC coupling can be employed at the input in the form of Quasi-floating-gate inputs for separating the DC-bias circuits for the PMOS and the NMOS inverter sections. This is done in order to maintain higher overdrive dynamic range for these inverter devices to operate in saturation and achieve linear small-signal current-to-voltage transimpedance gain. The bias voltages for the PMOS and NMOS input devices are provided by diode-connected PMOS pseudo-resistors. Here PMOS and NMOS cascoding devices are connected in a negative-feedback loop employing differential amplifiers with gain "A". The g m -boosting differential-amplifier is assumed to have high input-impedance (similar to that of an ideal operational amplifier [17]) so that there is negligible current flowing into its terminals at mid-band frequencies.

II. TRANS-CONDUCTANCE-BOOSTED INVERTER-CASCODE TRANSIMPEDANCE AMPLIFIER AND ITS ANALYSIS
The gates of the cascoding devices M2 and M3 are biased by the DC level at the output of the g m -boosting differential amplifiers. Fig. 1(c) shows the cross-sections of diodeconnected CMOS devices as p-n junction leakage-diodes (pseudo-resistors) with PMOS leakage-diode (on the left) and NMOS leakage-diode (on the right), where, a p-n junction leakage-diode provides a high resistance path. Alternatively, resistor-feedback biasing can also be provided by shorting the AC coupling capacitors and opening the pseudo-resistors. Fig. 2 Fig. 2(b) which is essentially a shunt combination of the NMOS and the PMOS inverter sections of the g m -boosted invertercascode TIA. The values of the resistances 1/g m5 and 1/g m6 are very high due to the very small leakage-current flowing through the diode-connected pseudo-resistors, and, as a consequence the overall resistance across the current-source input is dominated by R F . Fig. 2(c) depicts the small-signal equivalent circuit of the g m -boosted NMOS half (section) of the TIA, while, Fig. 2(d) shows its output shorted equivalent circuit for finding the G m of the Norton Amplifier model [18] of this half. It is easily observed now that -g m3 (A+1)v y and g mb3 v b1s1 are two current-sources due the same voltage (0-v y ) across them (with voltages at b3 and s3 being zero and v y respectively). Hence, they are reduced to two conductors of values g m3 (A+1) and g mb3 respectively.
In the next diagram in Fig. 2 Changing sides and rationalizing, So that,   y o4 y o4 y y m3 mb3 o3 o3 out1 And in the final form, Similarly, applying the same small-signal analysis procedures to the PMOS cascode section (M1 and M2), the composite trans-conductance is given by, Also, the output impedance of the PMOS cascode section is given by, Next, Fig. 3 shows the final open-loop small-signal AC equivalent circuit of the g m -boosted inverter-cascode TIA. From the input side of this equivalent circuit, the input voltage v in imposing at the gates of M1 and M4 is equal to the product of the composite resistance and the current i in at the input so that, Since g m5 and g m6 is very small compared to 1/R F , From the output side of the equivalent circuit, the transconductance current sources G m1 v in and G m2 v in can be merged into one, so that the output voltage v out is given by, Applying (12) into (13), the open-loop transimpedance gain is given by, And, finally the closed loop Trans-impedance gain is given by, With variation in the g m -boosting gain "A" G m1 and G m2 essentially remains equal to respectively g m4 and g m1 . However, with increasing g m -boosting gain "A" the output impedances R out1 and R out2 increases so that the overall output impedance approaches R F gradually with R F being much smaller than the g m -boosted output impedances R out1 and R out2 . The overall transimpedance gain of the g m -boosted invertercascode TIA thus increases with the g m -boosting gain "A".

Miller-capacitance suppression with gm-boosting:
The input impedance looking towards the source of M3 ( in_S_M 3 R ) can be determined using Fig. 2 Since R F is much smaller than the g m -boosted R out2 , we can write from (17), Similarly, the input impedance looking towards the source of M2 ( in_S_M 2 R ) is given by, Hence, the total miller capacitance at the input is given by, The miller capacitance at the drain of M1 is given by, And, similarly the miller capacitance at the drain of M4 is given by, The total capacitance at the input of the TIA is then given by, Then the time-constant at the input, input  is given by, Inspecting (23) it is clearly evident that the time-constant at the input reduces with increasing g m -boosting gain "A" thus enhancing the bandwidth. Next, the total capacitance at the drain of M1, Then the time-constant at the drain of M1, Again, inspecting (27) it is clearly evident that the timeconstant at the drain of M1 also reduces with increasing g mboosting gain "A" thus improving frequency response. Following-on, the total capacitance at the drain of M4 is given by, Again, inspecting (30) it is clearly evident that the time constant at the drain of M4 reduces with increasing g mboosting gain "A" thus enhancing bandwidth. Inspecting (20), (21), (22), (23), (25), (28) it is clear that the g mboosted inverter-cascode trades miller-capacitance with the g m -boosting gain "A" between the input and the internal node. Since the pole due to the photo-diode (or sensor) capacitance constitutes the dominant-pole for the transimpedance amplifier this trading enables the reduction of the input time-constant and enhancement of the bandwidth for the transimpedance-amplifier. Thus, while cascoding reduces the miller capacitance appearing at the TIA input, the g m -boosting supresses the miller capacitance at the TIA input further by the g m -boosting gain "A". Also, inspecting (24), (27) and (30) it is clear that g m -boosting reduces all the time constants resulting in an overall bandwidth improvement.

Transfer-function of the gm-boosted inverter-cascode TIA:
Since the time-constants at all the nodes with miller-effect capacitances have been determined, the only remaining time-constant is at the output of the TIA, which is given by, Hence the four poles of the TIA are, The zero is possibly complex, and, although the devices in the upper and lower PMOS and NMOS halves are symmetrically located, they are unmatched. Consequently there is a finite value of this zero of the overall transfer function.

Noise equations for the gm-boosted inverter-cascode TIA:
Considering only thermal-noise of resistors and the drain-current noise of the MOSFET devices, the noiseinserted [21], [22] g m -boosted inverter-cascode TIA with noise-current-spectral-densities associated with all the devices is shown in the Fig. 5, where the drain-currentnoise can be expressed by a current-source connected across the drain and the source of the MOSFET devices operating in the saturation region [13]. Thus, the noisecurrent-power-spectral-densities of MOSFETs and the resistor R F in the Fig. 5    Where, K is the Boltzman constant and T is the temperature in Kelvin. Next, the noise-current-power-spectral-density of R F arriving at the node (a) splits into two equal components, so that the component at the drain of M2 is given by, . The noise-current-power-spectral-density at the drain can be referred to the source directly, but the draincurrent-noise-power cannot be referred to the source directly; it is referred as noise-voltage-power-spectraldensity to the gate-node [21]. Thus the noise-current-power arriving at the drain of M2 can be referred to the source of M2 at node (b). Next, the noise-voltage-power-spectraldensity referred to the gate of M2 at node (e) is given by, Thus, the input referred noise-current-power-spectraldensity at the drain of M11 (@ node (e) ) can be written as, (2 ) ( Since in the saturation region, C gs (≈2/3C ox ) >> C gd, we can simplify the above as, 2 2 2 2 n,in-e n,in-e db11 db13 gs2 Similarly, the noise-voltage-power-spectral-density referred to node (f) due to M12 and M13 is given by, 2 2 2 2 2 n,in-f n,m12 n,m13 m12 m13 And, noise-current-power-spectral-density referred to the source of M10 (@ node (g)) can be found by, Which can be simplified to, Hence, the total input referred noise-current-powerspectral-density at node (g) is the sum of the noise-currentpowers at nodes (e), (f) and the drain-current-noise-power of M9, given by, Accordingly, the total noise-voltage-power-spectral-density referred to the gate of M11 at node (b) is given by, Where, A V is the expression for the voltage-divider-gain due to the source-follower operation of M11, which is given by, Following-on, The input referred noise of the bottom half-circuit can be found in the same way as mentioned above, as follows: The noise-voltage-power-spectral-density referred to the gate of M3 at the node (h) is given by, 2 2 2 n,in-h n,m3 m3 Thus, the input referred noise-current-power-spectraldensity at the drain of M17 (@ node (h)) can be written as, Similarly, the noise-voltage-power-spectral-density referred to node (i) due to M14 and M15 is given by, 2 2 2 2 2 n,in-i n,m14 n,m15 m14 m15 And the noise-current-power-spectral-density referred to the source of M16 (@ node (k)) can be found by, Hence, the total input referred noise-current-power-spectral density at node (k) is the sum of the noise-current-powers at nodes (h), (i) and the drain-current-noise-power of M18, 2 2 2 2 n,in-k n,in-h n,in-i n,in-18 Accordingly, the total noise-voltage-power-spectral-density referred to the gate of M17 at node (c) is given by, 2 2 2 2 2 n,in-c n,in-k n,m17 2 m16 m17 V1 m17 Where, A V1 is the expression for the voltage-dividergain due to the source-follower operation of M17, given by, The total noise-current-power-spectral-density referred to the node (c) is given by, Thus, the total input referred noise-voltage-power and noise-current-power spectral-densities at input node (d) are given by, Next, neglecting 4 th order capacitance product terms,     2  2  2  2   2  2  2  2  2  n,in-d  n,m5  n,m6  n,m1  n,m4  m5  m6  m1  m4   2  2  2  2  2  2  2  n,in-9  n,m11  db1  gs2  bs2  gs11  2  m10  m11  V  m11  m1 2 n,in-18 f   2  2  2  2  2  2  n,m17  db4  gs3  bs3  gs17  2  m16  m17  1V  m17  m4   2  2 n,R F Which can be simplified as, Or in the final form,   (68) Since the transconductances of the diode-connected pseudo-resistors are very small due to the flow of the leakage-current as their bias-current, it is essential to choose appropriate sizes of these devices in order to reduce the input referred noise with increasing frequency.

III. SIMULATION AND EXPERIMENTAL RESULTS
The g m -boosted inverter-cascode TIA was simulated and fabricated using the 180 nm TSMC CMOS process technology, and, a 1.8V power-supply was employed for the simulations and the measurements. Relatively similar component and device sizes for the corresponding transistors were employed for the g m -boosted invertercascode TIA and the non-g m -boosted (basic) invertercascode TIA for their performance comparison. Both numerical solution using MATLAB to determine the effect of varying the g m -boosting gain "A" based on the derived equations, as well as, Cadence spectre circuit simulation of the overall gain-bandwidth was carried out. All the bias voltages and device sizes are shown in the Fig. 4. The transconductances, body transconductances and output resistances of the MOFET devices in the Fig. 4 were as follows: For M1, g m1 =372.269 µ-mho and r o1 = 100.35k. For M2, g m2 = 630.58 µ-mho, g mb2 = 176.9 µ-mho and r o2 = 26.40k. For M3, g m3 = 692.45 µ-mho, g mb3 = 150.53 µ-mho and r o3 = 10.37 k. For M4, g m4 = 647.25 µ-mho and r o4 = 80.73k. For pseudo resistors M5 and M6, g m5 = g m6 ≈ 0.01 µ-mho and r o5 = r o6 ≈ 26.7273M. For M9, g m9 = 201.88 µmho, and r o9 = 50.80 k. For M10, g m10 = 113.53 µ-mho, g mb10 = 36.42 µ-mho and r o10 = 1.49M. For M11, g m11 = 109.63 µ-mho, g mb11 = 35.12 µ-mho and r o11 = 1.70M. For M12, g m12 = 119.80 µ-mho and r o12 = 858.66k. For M13, g m13 = 112.92 µ-mho and r o13 = 448.90k. For M14, g m14 = 107.43 µ-mho and r o14 = 653.70k. For M15, g m15 = 102.32 µ-mho and r o15 = 501.41k. For M16, g m16 = 113.39 µ-mho, g mb16 = 30.83 µ-mho and r o16 = 1.87M. For M17, g m17 = 109.37 µ-mho, g mb17 = 29.73 µ-mho and r o17 = 2.18M. For M18, g m18 = 213.79 µ-mho and r o18 = 33.49k. The feedback resistor R F = 4,532 ohm. A photo-diode (sensor) capacitance of 2.7pF was used in the simulations. The various device capacitances are as follows: Fig. 6 shows increasing closed-loop gain of the g m -boosted inverter-cascode TIA with increasing g m -boosting gain "A" in accordance with (14) -(16) and the theoretical discussions. Next, Fig. 7 shows the considerable reduction of the miller capacitance at the input with the g m -boosting gain "A" while Fig. 8 shows the variation of the total capacitance at the TIA input. Fig. 9 shows that the dominant pole position at the input moves to higher frequency with the g m -boosting gain "A", and, in addition, Figs. 10 and 11 indicates that the non-dominant pole positions at the sources of M2 and M3 also moves to higher frequencies with the g m -boosting gain "A". Fig. 12 shows the variation of the input referred noise current spectral density with frequency indicating a noise current density of around 13 pA/sqrt(Hz) within the bandwidth of the TIA. The theoretical input referred noise current spectral density is also shown which is close to the simulated curve. Following-on, Fig. 13 shows a transient simulation of the g m -boosted inverter-cascode TIA indicating a nominal transimpedance gain of around 94dBΩ.    Next, Fig. 14 depicts an AC analysis simulation of the closed loop g m -boosted inverter-cascode TIA indicating a gain of around 133 dBΩ along with a bandwidth of around 3.1 MHz which is suitable for many slowly varying sensing and biomedical applications requiring high gain without the need for very high bandwidth. Simulation of an invertercascode TIA with similar device sizes and feed-back resistor but without g m -boosting yielded a gain of only around 85 dBΩ. Compared to a gain-bandwidth of only around 37,344 Ω-MHz without g m -boosting, a gainbandwidth of around 13,847,191 Ω-MHz was indicated by the AC-simulation employing the g m -boosting around the inverter-cascode TIA. Fig. 15 depicts respectively, (a) the open-loop gain (bode-plot), and, (b) the phase variation, obtained from the simulation of an open-loop configuration of the g m -boosted inverter-cascode TIA which also represents the loop-gain (T) of the TIA for unity feed-back (β=1). The plots thus indicate stable operation with a phasemargin of 66º for the unity feed-back loop-gain. Since the feed-back factor of 1/R F will reduce (scale-down) the loopgain while having the same poles and zeros, the TIA is expected to have a higher phase margin than 66º.  As shown in this figure, the peak-to-peak output-voltage swing is around 1V for a test peak-to-peak input-current swing of 20 µA.
Following-on, Fig. 16 shows the photomicrograph of the fabricated g m -boosted inverter-cascode TIA with a large area consumed by the feedback resistor. Next, Fig. 17(a) shows the experimental setup for testing the fabricated g mboosted inverter-cascode TIA, while, Fig. 17(b) shows the top and bottom photos of the fabricated PCB used for mounting and testing the TIA chip in a DIP package. A voltage signal wave-form from a Tektronix AFG3021C single-channel arbitrary function generator is the primary input to the PCB. A current source IC LT3092EST#PBF on the PCB employs this voltage wave-form to produce an equivalent current wave-form of the same shape as an input to the fabricated g m -boosted inverter-cascode TIA for measuring the transimpedance gain. The PCB used a 1.8V power-supply, and, 2 resistors, Rout=Rset=22k were connected to the current-source IC (underneath the PCB) to generate a current source output of 10 µA based on the data-sheet of the current source IC. A 2pF capacitor was used at the input as an equivalent photodiode (sensor) capacitance at the TIA input. The amplified voltage signal output from the TIA is fed to a non-inverting buffer-gate SN74LVC1G17DBVR and then displayed and measured out using a Tektronix TBS 1102b-EDU digital oscilloscope. A measured maximum gain of around 100 dBΩ was achieved by the fabricated g m -boosted inverter cascode TIA compared to the AC-simulated mid-band gain of around 133 dBΩ. Fig. 18 shows the measured transient voltage outputs of the fabricated g m -boosted inverter-cascode TIA for current source inputs, (a) square-wave input, (b) sinusoidal-wave input. A gain-bandwidth of around 325,000 was displayed by the fabricated TIA.

IV. CONCLUSION
A g m -boosted inverter-cascode TIA is proposed and its operation is discussed thoroughly using mathematical derivations. Simulations and experimental fabrication results are also provided. It is evident that the g m -boosting enhances the transimpedance gain and drives the transfer function poles further down in frequency on the bode plot. Considerable gain-bandwidth improvement is thus achieved by the TIA compared to the topology without g m -boosting. Also, a simplified inspection-based small-signal analysis method is demonstrated for the g m -boosted inverter-cascode TIA which has not been provided before in literature.