Single-Phase Hybrid Switched-Capacitor Interleaved AC-DC Boost Converter

In this paper a single-phase boost PFC multilevel interleaved high-voltage gain based on the hybrid switched-capacitor concept is presented. The proposed converter merges interphase transformers and switched-capacitor cells to obtain current sharing and high voltage gain. These features allow for both the reduction of voltage and current stresses on the semiconductors. Furthermore, the interleaving method allows for obtaining multilevel voltages at AC terminals, thereby reducing the weight and bulk of the input inductor. PFC operation is guaranteed through both input current control and output voltage control. Both steady-state and dynamic analyses were conducted. Experimental results for a 1.25 kW, 127 V to 800 V laboratory prototype are presented and discussed.


I. INTRODUCTION
In recent years there has been a growing demand for high voltage power supplies. These sources are required in applications such as renewable energy systems [1] and electric vehicle powertrains [2], among others [3], [4].
Hybrid topologies are the prominent technique that allows for high voltage gain. This technique combines a traditional boost topology with switched capacitor (SC) converters. The SCs allow increased voltage gain by means of diodecapacitor cells, that guarantees the voltage division on the semiconductors. It has been developed for numerous applications, such as LED systems [4], pulse generation [5], and high static gain systems [6], [7], among others [8]- [19].
On the contrary, in applications connected to the electrical network, power factor correction is required owing to the regulations. Typically, a PFC boost rectifier is applied to obtain a sinusoidal current at the input and a high power factor. Although it has a voltage-elevating characteristic, the gain of this converter is limited owing to losses and high efforts in semiconductors. One solution to this problem is the use of hybrid topologies. In [20] a family of unidirectional single-phase hybrid switched-capacitor (HSC) AC-DC boost rectifiers is presented, whose converters provide a static gain twice that of the conventional PFC boost rectifier, and can be increased with the addition of cascading multiplier stages. In [21] another family of single-phase and threephase unidirectional hybrid rectifiers with a high power factor is presented. Through a three-level generic cell, a static gain four times greater than that of the conventional boost converter was obtained. A reduction in the voltage stresses on the switches to one-fourth the output voltage, the PFC operation, and high efficiency. However, the topologies have an operating range limited to some applications owing to the significantly increased current stress at high power.
To overcome the high current stresses the interleaved technique can be employed. The interleaving technology is applied in power applications above 600 W, which also increases the equivalent switching frequency as demonstrated by [22]- [24]. It presents the current share between the connection arms, promotes waveform frequency multiplication of inductive and capacitive elements, and reduces voltage efforts [25], [26]. In addition, it promotes input-current ripple reduction, thereby allowing for filter size reduction, and contributes to a low electromagnetic interference level [27]- [30]. Recent studies have demonstrated that the interleaving technique associated with HSC converters, can be used in applications with high static gain and low ripple current, such as [31]- [33].
In [34] an interleaved double-input three-level boost converter, which is composed of two boost converters indirectly in series, is proposed. In [35] a nonisolated threelevel bidirectional dc-dc boost converter is proposed using the interleaving technique. In [36] an input-parallel-outputseries multilevel boost converter integrated with SC cells. These topologies present high-voltage gain and small voltage across all components, owing to the advantages of the interleaving method associated with SC concept. However, these topologies were applied only in DC-DC converters.
From the above, this paper presents a single-phase HSC interleaved AC-DC boost converter with a high power factor and high static gain. The converter has the inherent advantages of interleaved operation with a hybrid topology with an SC. Among the advantages are reduced input current ripple, low AC losses in the inductor, low voltage stresses across all semiconductor devices, and high output voltage.
In the following sections, the basic operation principle of the proposed high step-up converter and mathematical model are described. In addition, the control strategy and the main characteristics are presented. Finally, to validate the proposed converter, experimental results were obtained from a 1.25 kW prototype with 800 V output voltage.

II. PROPOSED CONVERTER
The proposed single-phase HSC interleaved AC-DC boost converter is shown in Fig. 1. It comprises four switches S n n ∈ {1, .., 4}, an input inductor L switching capacitors C j,k j ∈ {1, 2, 3} k ∈ {A, B}, and two interphase transformers with inductors. The interphase transformers are represented by self inductances L s , which are connected to an interleaved arm.
As previously mentioned, the interleaving technique associated with SC converters is advantageous for high static gain applications. Owing to the interleaving technique, the input inductor operates at twice the switching frequency, which reduces its bulk. The inductors of interphase transformers also have a bulk reduction, as they only have high-frequency magnetic flux. These advantages make the proposed topology more interesting when compared with the topologies presented by [21] because it operates in the PFC, as the reference topologies, and makes it possible to obtain other topologies with lower current stresses on semiconductors for high power applications compared to the reference.

A. OPERATIONAL STAGES
As the proposed converter operates symmetrically it is analyzed over a positive half cycle of the grid. However, quantitative and qualitative analyses are also valid for negative grid semi-cycles. It operates in four stages depending on the PWM modulation scheme shown in Fig. 2.   Fig. 2(b), where the modulation signal v mod A is compared with the triangular carried v tri1 to generate the command signals v gS1 and v gS2 for switches S 1 and S 2 , respectively. The switching pattern for switches S 3 and S 4 is generated by means of a second comparator employing a carrier signal v tri2 shifted 180º. Ideally, for the same switching period, the switches are fed with the same duty cycle. Switches S 1 and S 3 operate for the positive semi-cycle of the grid, while S 2 and S 4 operate for the negative semi-cycle.
As the duty cycle d is variable over a grid period, it can be performed according to the voltage level transition angles θ 1 and θ 2 , facilitating analysis. Thereby, the duty cycle is d > 0.5 to ωt < θ 1 and d < 0.5 to θ 1 < ωt < θ 2 .
ωt rad    3 shown the command signals v gS1 and v gS3 for switches S 1 and S 3 , respectively. The respective operational stages and their time intervals over a switching period T s , where d is the duty cycle. Fig. 4 represents the equivalent circuit to each operational stage, where r C3,A represents the capacitor series resistance.  For operational stages the capacitors are previously charged and their voltages are constant.

1) First Stage
As shown in Fig. 4(a), the command for driving switch S 1 occurs, while switch S 3 is turned off. During this period, inductor L 1 transfers energy to capacitor C 3,A , through diodes D 1 and D 2 . Capacitor C 1,A transfers energy to capacitor C 3,A through diode D 2 . Capacitor C 2,A transfers energy to the load R o , while inductor L 2 stores the energy supplied by the input inductor L. The input inductor L receives energy from the power source v g , while diode D 3 remains blocked. Applying Kirchhoff's loop law, the equations describing this stage are presented in equations by (1).

2) Second Stage
As illustrated in Fig. 4(b), switches S 1 and S 3 are turned off. The input inductor L together with inductors L 1 and L 2 transfers energy to all capacitors. The inductor L 2 transfers energy to capacitor C 3,A . Capacitor C 2,A and the load R o receive energy from capacitor C 3,A through diode D 3 . The inductor L 1 transfers energy to capacitor C 1,A through diode D 1 . The diode D 2 remains blocked. The expressions in (2) define this stage. (2)

3) Third Stage
As shown in Fig. 4(c), switch S 1 is turned off, while switch S 3 is driving. The inductor L 1 stores the energy supplied by the input inductor L, which in turn receives energy from the power source v g . The inductor L 2 transfers energy to capacitor C 3,A . Capacitor C 3,A transfers energy to the load R o , as well as to the capacitors C 2,A and C 1,A through diode D 3 , showing the switched-capacitor operation. The diodes D 1 and D 2 remain blocked. The equations for this stage are shown in (3).

4) Fourth Stage
Fig. 4(d) shows that when the duty cycle is d > 0.5. Switches S 1 and S 3 were turned on. The input inductor stores energy from the power supply through switch S 3 , as well as from capacitor C 3,A through switch S 1 . The load R o receives energy from capacitor C 2,A . Fig. 5 shown the basic waveforms from the proposed converter over a switching period T s including the four operational stages. The command signals for switches v gS1 and v gS3 , levels from switching terminal voltage v ao , voltage v L and ripple current ∆i L,pk−pk of the input inductor, where v g is the input voltage and V o is the output voltage.

B. STATE-SPACE ANALYSIS
The analysis by the state-space averaged model is presented considering the converter operating in continuous conduction mode. The analysis can be performed in matrix form by equations in (4).
where A, B e C are the matrices with the variables states in each operational stage within one switching period T s . The vectorẋ is the derivative vector of x that is the space state VOLUME 4, 2016 Operational stages of the proposed converter valid to positive semi-cycle of the grid: (a) switch S1 is turned on and S3 is turned off; (b) S1 and S2 are turned off; (c) S1 is turned off and S3 is turned on; (d) S1 and S3 are turned on. vector, u is the input vector, and y is the output vector of the system, those are expressed by the equations in (5).

Time [s]
Considering the operational stages to d < 0.5, shown in Fig. 3(a), the matrices A, B, and C are determined by the expressions in (6).
where A n , B n , C n , n ∈ {1, 2, 3}, are the matrices with state variables from each operational stage.
For the state analysis, the derivative result of the spacestate vector is zero (ẋ = 0) thus, the analytical solution for expressions in (4) . Solving for it, the state variable expressions are obtained in (7) to vector x as a function of the input voltage v g , load R o , and duty cycle d.
The grid current i g equals the input inductor current i L (i g = i L ), where i L = Σi Ln n ∈ {1, 2, 3, 4}, and the output voltage V o is determined by expression V o = Σv C j,k , j ∈ {1, 2} and k ∈ {A, B}. Therefore, the output variables matrix y results in expression (8).
Solving for it, the static gain can be written by expression (9).
Therefore, by means of expression (9), the static gain of the proposed converter is four times greater than the conventional boost gain.

C. CURRENT STRESSES ANALYSIS
To determine the semiconductors currents and voltages some considerations were adopted, which are as follows: • The converter operates in continuous conduction mode. • The switching frequency f s should be much higher than the grid frequency f g (voltage grid approximately constant within a switching period T s ). • The input current ripple is neglected. • The dc-link voltage is kept constant. • All capacitance values are sufficiently large to keep their voltages constant over a switching period T s . • All components are ideal. Considering that both input voltage v g and input current i g are purely sinusoidal and high-power factor operations, according to the equations in (10).
where V gp and I gp are the grid peak voltage and the grid peak current, respectively. Neglecting the average voltage across the input inductor L, which is calculated over a switching period T s , then v g ≈ v ao Ts , where v ao Ts is the average voltage between the nodes a and o, that is determined by equation (11) over a switching period T s .
where d is the duty cycle and sign{i L } is the signal function of i L . The duty cycle is related with modulation signals v modk k ∈ {A, B}, as shown in Fig. 2(b), which is determined through the equation , where V T is the peak of the triangular carrier. Isolating d in equation (11) it results the equation (12), that depicts the duty cycle variations.
where M is the modulation index, that is determined by the equation M = 4·Vgp Vo , and V o is the output voltage. Therefore, the input inductor current equals the input current (i L = i g ) and it depends on the duty cycle d. Given that, the quasi-instantaneous RMS current expressions are shown in Table 1 as a function of the input current i g as well as the duty cycle d.
The average current expressions for the semiconductors are listed in Table 1, and the expressions for the RMS current are presented in Table 2 for switches S 1 and S 3 , diodes D 1 , D 2 and D 3 , capacitors C 1,A , C 2,A and C 3,A . All expressions are defined as functions of the modulation index M as well as the grid peak current I gp .

D. INDUCTOR CURRENT RIPPLE
The envelope of the normalized input current through inductor L is defined by expressions in (13).
where θ 1 = arcsin 1 2M , that corresponds to the boundary of level transition, as shown in Fig. 2(a), and ∆i Lpk−pk represents the normalized input current, that is determined by equation (14).
Considering that the maximum current peak occurs when ωt = arcsin( 1 2M ), leading to the normalized input current to ∆i Lpk−pk = 0.25, with modulation index M > 0.5, that is one-fourth the input current i g . Therefore, the input inductance value L is determined by equation (15).

E. DC-LINK VOLTAGE RIPPLE
Considering that the capacitors C 3,k k ∈ {A, B} have low capacitance the dc-link voltage ripple ∆v Co is defined by the output capacitance C o through the dc-link capacitors C j,k , j ∈ {1, 2} k ∈ {A, B}, calculated by equation (16).
Considering to the dc-link voltage ripple, the output capacitance C o is determined by equation (17).
The capacitance C 3,k k ∈ {A, B} are calculated according to partial-charge operation mode, that ensures that there are no current spikes [37]. Therefore, determining the circuit time constant τ , which is calculated using the expression τ = (r C3,k · C 3,k ), and the capacitor switching time using the expression T i = (M · T s ) is necessary. Initially, the value of the switching frequency f s is defined according to the semiconductors and input inductor losses. Subsequently, the values of the capacitors C 3,k , k ∈ {A, B}, and series resistance r C3,k , k ∈ {A, B} are defined through the manufacture datasheet. Finally, the condition τ > T i must be satisfied to enable the partial-charge operation mode. In conclusion, verifying whether the switching capacitors can withstand the effective circuit current is necessary.

III. CONTROL STRATEGY
The control strategy developed for PFC operation of the proposed converter is shown in Fig. 6. The average current mode method was applied to equate the variables for the control loops of the input current i g and output voltage V o .
Owing to the interleaving connection, the input current i g is divided into four components, which are the currents VOLUME 4, 2016

Semiconductor
Effective current expression i Ln n ∈ {1, .., 4} of the interphase transformer inductors L s . Thus, the input current is the sum of these currents, that is determined by expression i g = Σi Ln n ∈ {1, .., 4}.
The output voltage control monitors the dc-link partial voltages v op and v on because the output voltage V o is determined by the sum of these voltages, that is V o = (v op +v on ).
The measurement of the input voltage v g is required to generate the control reference signal i ref L , which is applied to the current-loop to generate the modulation signals v mod k k ∈ {A, B}.
Finally, the modulation signals are compared using two comparators from the PWM scheme, as shown in Fig. 2(b), with the triangular carriers v tri1 and v tri2 to generate the command signals v gSn for the switches S n n ∈ {1, .., 4}.

A. CURRENT-LOOP CONTROL
Current-loop control is illustrated in Fig. 6, which comprises the generation of the modulation signals v mod,k k ∈ {A, B} following a sinusoidal reference i ref L , whose waveform is defined by the input voltage v g and its amplitude is defined by voltage-loop control. Subsequently, the modulation signals are compared with the triangular carriers. Finally, the command signals v gsn n ∈ {1, .., 4} are generated for the switch gates.
Therefore, by defining the small-signal model and applying the Laplace transform, the transfer function is obtained in expression (18), that depicts variations in the inductor current with duty cycle.

B. VOLTAGE-LOOP CONTROL
The voltage-loop control, shown in Fig. 6, generates the signal i ref L . The dynamics of the voltage-loop control must have a slow action, such that the sinusoidal reference signal does not oscillate.
The voltage balance loop produces a balance between the partial voltages v op and v on through the difference between them. The value corresponding to this difference is applied to a gain and then added to the input voltage signal.
To model the output voltage-loop control, it is assumed that the dc-link capacitors C j,k j ∈ {1, 2} k ∈ {A, B} have much higher capacitance than the capacitors C 3,k , k ∈ {A, B}. Capacitors C j,k j ∈ {1, 2} k ∈ {A, B} provide a low impedance path to 120 Hz ripples in instantaneous power and low ripple dc-link voltage.
Considering this, by applying the small-signal model and Laplace transform, the voltage-loop transfer function, which describes variations of the output voltage with the inductor current is provided by expression (19).

A. DESIGN CONSIDERATIONS
The experiments were carried out using the specifications of the design parameters presented in Table 3. The prototype was tested operating in a closed loop with control of the input current and output voltage under rated conditions. The component specifications used for the prototype are listed in Table 4. For practical implementation, operating the converter in the partial-charge mode is adequate, as it results in a good relation between the peak current and capacitance [21]. The capacitors C 3,k k ∈ {A, B} have low capacitance value, then film capacitors were employed because they have low resistance and low parasitic inductance, leading to good performance in high frequency. The dc-link capacitors C j,k j ∈ {1, 2} k ∈ {A, B} electrolytic technologies were already used to absorb the oscillating power present at the frequency of 120Hz. Fig. 7 shows the input voltage v g , input current i g , partial voltages v op and v on , and output voltage V o . The output voltage is according to the desirable value, that is V o = 800 V, with the partial voltages balanced v op = v on ≈ 400 V, indicating good voltage regulation. In addition, the PFC operation is Capacitor voltages are shown in Fig. 9. The voltage is onefourth of the output voltage, which are v C 1, The switch voltages v Sn , n ∈ {1, .., 4} are shown in Fig. 10 and they are one-fourth of the output voltage. Fig. 11 represents the interphase transformer cell current i Ln n ∈ {1, .., 4}. This confirm the reduction in current efforts owing to the use of the interleaving technique.
. Interphase transformer cell current i Ln n ∈ {1, .., 4} (5 A/div). Fig. 11 shows that the i L1 and i L2 waveforms out of phase, so they tend to cancel each other out, thereby reducing the high frequency input ripple current, which is caused by the boost switching action.
The input current harmonic spectrum as a percentage of the fundamental component for the proposed converter operating at the rated power is shown in Fig. 12. The current spectrum is obtained from the current shown in Fig. 7, showing a current sinusoidal shape and in phase with the respective voltage. It has a THD ≈ 8.5%, that is accordingly IEC 61000-3-2 standard [38], and a power factor of 0.986. The harmonic components are compared with the harmonic limits of the IEC 61000-3-2 standard for class A equipment that have been measured for the load condition.  The converter efficiency was measured with a FLUKE Norma 4000 power analyzer and the results are shown in Fig. 13. When the converter operated under the rated condition the maximum efficiency achieved was η ≈ 95.1%. The experimental results indicate that the proposed converter is viable because it corresponds to the expected values according to the specifications in Table 3.  Table 5 presents a qualitative comparison of the proposed converter with other topologies. The topologies presented in [34]- [36] submit the semiconductors to (0.5 V o ), the static gain is twice the conventional boost topology, and are not designed for PFC operation. The converter presented in [21] has higher similarities with the proposed converter. It provides a static gain four times greater than the boost conventional topology, and the voltage across the semiconductors is (0.25 V o ), leading to lower voltage efforts. Although the proposed converter uses more components, owing to the use of the interleaving method the input inductor operates at twice switching frequency, reducing its bulk. The inductors of interphase transformers also have a bulk reduction because they only have a high frequency magnetic flux. In addition, it provides lower current efforts, allowing for higher power applications for PFC operation.

VI. CONCLUSION
In this paper a single-phase HSC interleaved AC-DC boost converter topology is proposed. The topology is derived from a family of high voltage gain single-phase HSC PFC rectifiers. All switches support one-fourth output voltage and low current efforts, owing to the use of the interleaving technique, leading to low conduction losses.
Through an extensive mathematical analysis and experimental results, is demonstrated the feasibility of the converter, that presents a low input current ripple, low harmonic distortion, and regulated output voltage. The converter has an efficiency of η ≈ 95.1% under rated conditions. The proposed converter is suitable for unidirectional applications that require high voltage gain, low current and voltage efforts, PFC operation, and an output voltage above 800 V.