Reconnection–less Reconfigurable Fractional–Order Current–Mode Integrator Design With Simple Control

A design of a fractional-order (FO) integrator is introduced for the operation of the resulting solution in the current mode (CM). The solution of the integrator is based on the utilization of RC structures, but in comparison to other RC structure based FO designs, the proposed integrator offers the electronic control of the order. Moreover, the control of the proposed integrator does not require multiple specific and accurate values of the control voltages/currents in comparison to the topologies based on the approximation of the FO Laplacian operator. The electronic control of a gain level (gain adjustment) of the proposed integrator is available. The paper offers the results of Cadence IC6 (spectre) simulations and more importantly experimental measurements to support the presented design. The proposed integrator can be used to build various FO circuits as demonstrated by the utilization of the integrator into a structure of a frequency filter in order to provide FO characteristics.


I. INTRODUCTION
The research of fractional-order (FO) systems and circuits became an important and widespread area of interest in the last decade. This is due to the fact that FO systems can offer the ability to follow the required parameters more accurately and thus to extend possibilities of different applications in comparison to the integer-order systems. Fractional-order systems have found their application in diverse industry branches such as medicine [1], [2], modeling and measurement of various signals [3]- [5], agriculture [6], car industry [7], etc. In case of the electrical engineering, the utilization of FO calculus covers circuits filtering the spectrum [8]- [17], FO oscillators [18]- [23] and other circuits with fractional-order characteristics [24]- [29], which then can be implemented and find their purpose in applications of above-mentioned industry areas.
The associate editor coordinating the review of this manuscript and approving it for publication was Wenjie Feng.
There are different ways how to approach the design of FO circuits and systems. The most common way uses so-called Fractional-Order Elements (FOEs). The FOE represents a non-integer element with its behavior between either a standard resistor and capacitor with the resulting impedance given as Z C = 1/s α C α [30], or a standard resistor and inductor with the resulting impedance of Z L = s α L α [31], where s α is fractional-order Laplacian operator, C α is a pseudo-capacitance in Farad/sec 1−α and L α is a pseudo-inductance in sec 1−α /Farad. The phase shift of such element is given by ±90×α degrees, where α is a real number in range 0 < α < 1.
The FOEs are available in various forms. Some of these realizations are based on the physical implementation of these elements [32]- [34]. This approach has a disadvantage of commercial unavailability of these realizations and the absence of the electronic control of the resulting order. The next approach involves the substitution of the FOE by RC ladder networks [11], [13]- [17]. RC structures offer the VOLUME 9, 2021 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ possibility of simple design due to the commercial availability of building elements (only require common capacitors and resistors). The disadvantage is that the electronic control of the order is not available (the values of resistors and capacitors of the RC structure vary based on the desired FO and thus the resistors and capacitors of the RC structure need to be changed, or whole RC structure has to be redesigned and replaced). The last common technique is using emulators exhibiting specific behavior of the FOE [35]- [39]. The structure of these emulators is usually more complex and requires active elements in comparison to the previous approaches nonetheless, they often offer the electronic control of some parameter (fractional order, frequency band where the FO approximation is valid, gain adjustment, etc.). A slightly different approach to the design of FO circuits is a proposal of FO integrators and differentiators [40]- [49]. In comparison to the FOE emulators, which provide the function of a FO impedance, the FO integrators and differentiators serve as FO building blocks as they offer a FO transfer function rather than work as a FO impedance. These FO building blocks can be used to design diverse FO circuits by a simple replacement of whole building block (integer-order integrator or differentiator) of an integer-order circuit. There are a few variations of FO integrators/differentiators. Those introduced in [40]- [42] are based on the utilization of RC structures and thus, they do not allow the electronic control of the order (they still might offer the electronic control of other parameters such as the adjustment of the gain level of the output response). The change of the order is achieved by the replacement of the RC structure specifically calculated to provide results of the desired order. The solution in [43] does not offer the electronic control of the order neither the electronic control of any other parameter unless the active elements used in the design have a feature of the electronic adjustment of some parameter (not the case of the discussed design). The change of the order can be achieved by the replacement of passive parts of the structure. The FO building blocks in [44]- [49] do offer the electronic control of the resulting fractional order and possibly the electronic control of other parameters as well. Nevertheless, the control of these structures can be rather complex and problematic (further discussed in chapter V).
This text presents a design of a fractional-order integrator. The design of a FO integrator working in the current mode (CM) is offered. The solution provides a simple electronic control of the order and gain adjustment in comparison to other previously introduced integrator/differentiator designs. The design is based on a chip developed in CMOS I3T25 0.35 µm ON Semiconductor process offering multiple operational cells within. The introduced proposal is supported by Cadence IC6 (spectre) platform simulations alongside with experimental measurements of the implemented structure. A possible utilization of the proposed FO integrator in an application is shown for a 1 + α (see equation (4)) frequency filter design. The paper has the following organization: section I provides a background for the discussed matter. Section II introduces the proposed CM FO integrator which is then followed by the part (section III) showing the simulation and experimental results of this integrator. A possible utilization of the proposed CM FO integrator in a FO filter is shown in section VI. Discussion and comparison of the introduced design, in comparison to other previously presented solutions, is given in section V. The paper is concluded by section VI -the conclusion.

II. CURRENT-MODE FRACTIONAL-ORDER INTEGRATOR PROPOSAL
The design of the proposed integrator is based on the utilization of a chip introduced in [50]. The chip is implemented in CMOS 0.35 µm I3T25 ON Semiconductor technology. It contains several analogue cells, namely a second-generation current-controlled current conveyor (CCCII) with four outputs, current amplifier (CA), voltage multiplication units (MLTs) with a current output (one in CMOS and one with a bipolar core) and a voltage differencing differential buffer (VDDB). The transistor-level topologies of individual active elements are available in [50]. The presence of multiple cells in the chips allows a modular interconnection of these cells in order to construct diverse circuits or advanced active elements with multiple electronically controllable features. The proposed CM FO integrator is depicted in Fig. 1. The structure involves one current follower (CF) and a number of operational transconductance amplifiers (OTAs). The CF element has been created by the CCCII cell of the chip. For the CCCII working as a CF, the X terminal is used as a current input and the Y terminal is grounded. The relation of this element is given as I OUT± = ±I IN . As for the OTA elements, the CMOS multiplication units have been used. This particular implementation of the OTA element provides the electronic control of its transconductance by a DC control voltage (V SET_gm ). The behavior of the OTA can be described as The number of OTAs is depending on how many orders we want to obtain, the required variety of the desired orders, respectively. For the design introduced in this paper, we consider the orders 0.1, 0.3, 0.5, 0.7, and 0.9 (five orders). This requires five branches of the proposed integrator and thus five OTAs. We consider such variety of possible orders sufficient for our needs. If a higher variety of available orders is required, the number of branches can be increased (theoretically indefinitely according to the required variety). For the integrator providing five orders, it means 1 additional output for the CF element, nonetheless for the on-chip implementation this causes no significant issue (for the used implementation it means 4 additional transistors of the internal topology of CCCII cell). Each branch also contains an RC structure of specific values corresponding with the particular order. The resulting order of the integrator is depending on the setting of control of the OTAs. Each order is available by setting a specific OTA (other OTAs are set to zero). For example, if we want the order of the integrator to be equal to 0.3, OTA 2 is used and the control of the remaining OTAs is set to zero. That way, we will obtain the response of the desired order at the output of the integrator with other branches of remaining orders not being used at the moment. Thus, the control of the resulting order is simple (either being switched on or off). In such case, it would be easier to use simple electronically controllable switches rather than comparably complex CMOS structure of the OTAs, however, using the OTAs offers a possibility of additional electronic adjustment of the integrator parameters (possibility of the gain adjustment in this particular case). Also, as the used multiplication unit can work in all four quadrants, it can offer a possibility to invert the polarity of the output response. The specific setting of the integrator, in correspondence with the desired order, is presented in Table 1. The default used value of the transconductance when the OTA is set was chosen to be 0.5 mS.
The transfer function of the integrator from Fig. 1 is expressed as: where g mi and C αi denote the specific transconductance and FO capacitance depending on which order is currently used thus, i = {1, 2, 3, 4, 5}.
From (1), it is evident that the integrator is lossless. Fig. 2 shows a possible modification of the proposed CM integrator from Fig. 1. This modification consists of one additional CF (CF 2 ) and one adjustable current amplifier (ACA) added into the structure of the proposed integrator. The ACA element is described by the equation I OUT± = ±B · I IN , where B is the current gain of this element. The advantage of this modification is that we can easily switch between the integrator behaving as lossless or lossy by electronic means (current gain B controlled either by DC voltage or DC current depending on specific implementation of the ACA). This means two more active elements in the structure, nonetheless, the presence of the CF with multiple outputs (more than two) at the output of the integrator is desirable as the design of CM circuits, frequency filters in particular, often requires the necessity of multiple outputs of the building block (integrator) for feedback loops. The CF at the output also provides an impedance separation. The transfer function of the modified integrator is given by: From (2), it can be seen that, the integrator behaves as lossless for B = 0, when the integrator follows the equation (1), or lossy for B = 1.

III. SIMULATION AND EXPERIMENTAL RESULTS OF THE PROPOSED CM FO INTEGRATOR
The simulation results were carried out in Cadence IC6 (spectre) software using the simulation model in VOLUME 9, 2021 CMOS 0.35 µm I3T25 ON Semiconductor technology. The experimental measurements were performed with help of a network analyzer Agilent 4395A and simple V-I/I-V converters based around commercially available OPA860 device [51]. The measurement arrangement using a testing board, which can include up to four chips, is displayed in Fig. 3 (the board also includes the converters and trimmers to set bias currents). RC structures of required orders have been implemented for the purposes of simulations and experimental measurements. A 5 th -order Foster I type RC topology shown in Fig. 4 has been used. The values of the individual parts of the RC structures depending on the order were calculated using the Oustaloup approximation [52] in Matlab software for the central frequency f C = 10 kHz. The particular values are summarized in Table 2.
The values of transconductances of individual OTA elements in the integrator structure are either set to zero or 0.5 mS as already mentioned in the previous section. The value 0.5 mS corresponds with the value V SET_gm of 0.26 V in simulations and 0.39 V in case of the experimental measurements due to differences between the simulated and measured transconductance values in dependence on the control voltage which was g m ≈ 2·V SET_gm [mS] for the simulations and g m ≈ 1.3·V SET_gm [mS] for the implemented chip (standardly expected deviations fitting process corners, voltage and temperature variations) [50]. The supply voltage of the chip is ±1.65 V and the supply voltage of the chips (OPA860) used for the converters is ±5 V. The power consumption of one CCCII is 16.8 mW, and it is 7.8 mW in case of one multiplication unit. Therefore, the power consumption of the topology in Fig. 1 is 55.8 mW and 72.6 mW + the power consumption of the ACA depending on its implementation for the modified circuit in Fig. 2. Fig. 5 shows a comparison of the theoretical expectations (black dashed lines) and simulation results (colored lines)  of the magnitude and phase characteristics of the proposed integrator for the electronic adjustment of the order (for orders 0.1, 0.3, 0.5, 0.7 and 0.9). The electronic adjustment of the order is given by Table 1. The largest differences between the theoretical expectations and simulation results can be seen mainly at lower frequencies, where the magnitude characteristics of simulation results do not reach the same gain level as the theoretical expectations which is caused by the real characteristics of the output impedances of the active elements, limitations of the linear behavior of the chip in relation to the values of used transconductances and by the DC offset being too high for used gain. Similarly, the differences between the theoretical expectations and simulation results at higher frequencies are caused by the influence of the real characteristics of the input impedances and bandwidth limitation of the chip (up to about 40 MHz). For higher orders, the difference between the theoretical expectations and the simulation results at lower frequencies increases more significantly than for lower orders. Therefore, the design (for given implementation) is more suitable for frequencies above about 300 Hz. Nonetheless, despite of these expected differences, the results confirm the intended function of the proposed circuit and agreement with the theoretical presumptions in general. In order to evaluate the performance of the proposed integrator, evaluate the accuracy of the resulting order of the integrator and its bandwidth, where the FO approximation is valid, a relative error of the phase characteristics across the frequency was carried out (Fig. 6). The error is expressed in percentage as a deviation of the value of the phase obtained from the simulations compared to the theoretical (ideal) value of phase shift for given order (e. g. −9 • , −27 • , −45 • , −63 • and −81 • (constant across all frequencies) for orders 0.1, 0,3, 0,5, 0.7 and 0.9). The usable bandwidth (f min , f max ) of given order, established for a frequency band with a relative error under 10%, is summarized in Table 3. From the table, it can be seen that the operational bandwidth, where the FO approximation is valid (for the used 5 th -order RC structure), is above 2 decades in all cases. Note that if a wider operational bandwidth is required, an RC structure of higher order can be easily designed to cover these requirements.
As mentioned earlier, the presence of OTAs in the individual branches of the proposed circuit offers a possibility of  Simulation results of a sinusoidal wave response (see Fig. 8) of the proposed integrator for used fractional orders has been carried out in order to analyze the behavior of the integrator in the time domain. The input excitation signal (black line) has the following characteristics: amplitude is   The experimental results further support the design. In case of the experimental measurements, the integrator for order 0.9 already did not work properly due to the mutual interaction of the impedance of the RC structure and real/parasitic characteristics of the output impedances of used active elements. Therefore, the experimental results for order 0.9 are not included as they do not provide any useful contribution. This issue could be solved by the recalculation of the RC structure with different values of capacitors resulting in more favorable values of resistors being used.
A relative error of the phase characteristics obtained from the experimental measurements compared to the theoretical (ideal) value of phase shift for given order (−9 • , −27 • , −45 • , −63 • and −81 • for orders 0.1, 0,3, 0,5, 0.7 and 0.9) is depicted in Fig. 10. As the characteristics of measurements for order 0.9 are not available, the error is not presented in Fig. 10 and in Table 4, where the information about usable bandwidth is given. Comparing the bandwidths obtained from the simulations and experimental measurements, the implemented integrator exhibits narrower bandwidths as the effect of real/parasitic impedances is typically more significant in case of the measurement.

IV. APPLICATION EXAMPLE OF THE PROPOSED INTEGRATOR
The integrator has been implemented into a structure of a frequency filter (in order to provide fractional-order characteristics) as a possible utilization of the introduced design. A structure used for this matter is a simple current-mode second-order low-pass filter based on Follow-the-Leader-Feedback (FLF) topology (shown in Fig. 12). It consists of one CF, two OTAs and two grounded capacitors. The transfer function for this topology is given as: For the filter to provide FO characteristics, OTA 2 and C 2 were replaced by the proposed CM FO integrator as shown in Fig 13. Thus, the modified topology behaves as a 1 + α low-pass filter. The transfer function from (3) turns into: As the proposed integrator offers only one output (not considering the modification discussed at the end of section II), the additional required outputs were obtained by the addition of a CCCII operating as a CF at the output of the integrator.
In order for the transition between of the output response of the filter having Butterworth characteristics, coefficients k need to be applied onto the general FO low-pass function as: where k 1 = 1, k 2 = 1.008α 2 + 0.2867α + 0.2366 and k 3 = 0.2171α + 0.7914.
The function of such modified filter has been tested by cadence simulations and compared to the theoretical expectations. The value of C 1 has been set to 10 nF. Together with chosen pole frequency f 0 equal to 5 kHz, the values of transconductances g m1 of the filter and g m2 (substituted by the transconductance of the integrator) have to be calculated by the comparison of (4) and (5) in respect to coefficients k depending on the value of α. The values of transconductances for given α are stated in Table 5. The characteristics (magnitude and phase) of the filter for used orders (0.1, 0,3, 0,5, 0,7 and 0.9) are presented in Fig. 14, where black dashed lines stand for the theoretical results and colored lines represent the simulation results. It can be seen that the filter is behaving as expected -providing different fractional orders based on the setting of the proposed integrator. The simulation results show good agreement with the theory up to frequency of about 2 MHz, where the influence of the real characteristics of used active elements becomes more pronounced. The ability of the electronic control of the gain adjustment of the proposed integrator can be beneficial in case of the control of the pole frequency of the filter. The pole frequency VOLUME 9, 2021 of the filter can be controlled by adjusting the value of given transconductance g mi of the integrator (substituting g m2 of the filter) together with transconductance g m1 of the filter. The ability of the electronic control of the pole frequency has been tested for three settings (specified in Table 6). The results are shown in Fig 15 for theoretical expectations (black dashed lines) and simulations (colored lines) when the order of the filter was set to 1.5 (α = 0.5). From the graphs, it can be seen that the order and quality factor of the output responses remain unaffected when changing the pole frequency. Furthermore, the simulation results are corresponding well with the theoretical expectations and support the fact that the available electronic control of the gain adjustment of the proposed integrator can find its application in circuits.   differentiator as separate circuits while papers [44], [45] and [47] propose one topology which can offer the FO integration/derivation function. Circuits in [40]- [42] use the RC structures for their function while topologies in [43]- [49] are based on the approximation of Laplacian operator of the fractional order. The circuits proposed in [41]- [43], [48] and [49] operate in the voltage mode, circuits in [44]- [47] operate in the current mode and paper [40] offers designs working in both modes. Note that the designs based on the RC structure [40]- [42] typically do not offer the electronic control of the resulting fractional order. The RC structure has to be mechanically replaced for the integrator/differentiator design in order to provide a different fractional order which is the most significant disadvantage of this approach. On the other hand, the circuits [43]- [49] based on the approximation standardly utilize the electronic control of the order (and other parameters in specific cases). Paper [43] is an exception as the introduced circuit uses passive parts of specific values in order to obtain the FO approximation rather than using electronically controllable active elements and thus, this paper does not offer any electronic control. The disadvantage of topologies based on the approximation consists in the usually complex control/adjustment because multiple quite specific and precise values of the control voltages/currents are required for the accurate approximation (see papers [44]- [49] for exact values control voltages/currents). Thus, specific values of the control voltages/currents which might be difficult to obtain (e.g. very low values of control voltage in hundredths and thousandths of volts for α closing zero or one). We also usually require rather specific values of the control voltages/currents where the change of units of mili-volts or units of micro-amperes can cause a significant difference which might lead to an inaccuracy of the FO approximation.

V. COMPARISON AND DISCUSSION
The design proposed in this paper is based on RC structures, but in comparison to other RC structure based integrators/differentiators, it offers the electronic control of the order (and the electronic control of the gain). Compared to the circuits based on the approximation, the presented design brings a simple control of the resulting fractional order as it depends on whether given branch is on or off regardless of the value of the control (control voltage in this case) as described in sections II. The value of the control only determines the gain level of the resulting output response.
Comparing the circuitry introduced in this paper with other designs, the proposed design brings following: • It is based on RC structures, but in comparison to other RC structure based designs [40]- [42] it offers the electronic control of its order.
• Unlike circuits in [40]- [42], the mechanical replacement of the RC structure in order to obtain a different fractional order is not necessary.
• In comparison to designs [43]- [49], our solution provides a simple control of its order where we do not require multiple specific and accurate values of control voltages/currents.
• Available bandwidth of the proposed solution is 2 decades where only [40] and [44] offer better results.
(Papers 41] and [42] use a RC structure of the 10 th -order and thus their available bandwidth cannot be directly compared with the proposed solutions) • The design proposed in this paper is supported not only by simulations but also by experimental measurement. This only applies for papers [42] and [46].

VI. CONCLUSION
The simulation and experimental results prove the function of the proposed CM FO integrator. The results are in good agreement with the theoretical expectations except for the order 0.9 in case of the experimental measurements (a possible solution of this issue is discuses in section III). The performance of the proposed integrator for different orders is summed in Table 3 for the simulations and Table 4 for the measurements. The integrator can offer the electronic control of the order unlike other RC structure based solutions of the FO integrators. Furthermore, the control of the order is simple and does not require specific and very accurate values of sets of many parameters in comparison to the designs based on the approximation of the FO Laplacian operator. Thus, the described research offers a different approach avoiding the disadvantages of above mentioned methods. The integrator also introduces the additional feature of the electronic control of the gain level/gain adjustment as demonstrated in Figs. 7 and 11. A possible utilization of the proposed FO integrator in a topology of a standard second-order frequency filter for obtainment of a 1+α filter is tested. Obtained results ( Fig. 14 and 15) support the intended usage of the proposed integrator in the design of further FO applications.