Interleaved Ultra-High Step-Up DC-DC Converters With Extendable Voltage Gains and ZVS Performance

This paper introduces eight novel interleaved non-isolated dc-dc converters with ultra-high step-up and zero voltage switching (ZVS) capabilities for renewable energy systems. To increase the voltage gain, the proposed converters benefit coupled inductors, high-frequency (HF) transformer, and voltage multiplier (VM) techniques. In comparison to other converters, which just benefit coupled inductors or HF transformers, these combinations of the techniques make an additional degree of freedom to achieve high voltage gains (more than 25 without extreme duty cycle). Besides, two active clamp circuits, including two stages of switch-capacitor VM cells, not only increase the voltage gain of the proposed converters but also act as an auxiliary circuit to provide ZVS. Moreover, the stored energy in the leakage inductances is absorbed and passed to the output by the clamp capacitors. The input current ripple is reduced by applying the interleaved technique. The voltage stresses across the power switches are clamped to lower values and can be controlled by the turn ratios of the coupled inductors and the HF transformer. The theoretical performance of the proposed converters is fully explained. Also, the proposed converters are compared with more than twenty latest interleaved high step-up and ultra-high step-up dc-dc converters. Finally, a 1 kW, 20 V/500 V laboratory prototype is built to prove the advantages of the proposed converters.


I. INTRODUCTION
Nowadays, the growing demand for energy from fossil fuels causes air pollution, global warming, and other environmental concerns. These problems motivate research communities to find alternative or clean energy sources. Renewable energy sources such as solar energy and wind energy are the best response to these growing demands. Among different types of renewable energy sources, photovoltaic (PV) energy is one of the most attractive types of clean energy sources [1]- [4]. Usually, the PV array terminal voltage is low. Therefore, high step-up dc-dc converters are commonly used The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao .
to step-up the PV array voltage to the grid voltage level. Besides, the high step-up dc-dc converters are widely used in many applications such as fuel cells, batteries, servo motors, etc. [5]- [8].
In these applications, in order to increase power sources' lifetime, input current ripples should be stabled in lower levels. To decrease current ripples, interleaved converters are presented [9]- [13]. In [9] and [10], two simple circuits for interleaved converters are investigated. However, due to the hard switching condition, the efficiencies of these converters are lower than similar converters. The interleaved converter, as presented in [11], uses a high frequency (HF) transformer to provide high voltage gain. In [12] and [13], the combination of coupled inductors with voltage multiplier VOLUME 9, 2021 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ cells is utilized to increase the presented converters' voltage gain. The circuit, as illustrated in [14], is based on coupled inductors, and due to interleaved structure, the input current ripple of this converter is low. Converters in [11]- [14] suffer from high cost and volume. Also, the efficiencies of these converters are low. In high step-up converters, high frequency provides low volume but increases switching losses. Under high frequencies, switching losses are more elevated and decrease efficiencies of converters [15]- [18]. Therefore, in order to achieve high efficiency with low cost and volume, switching losses should be eliminated or reduced. There are various techniques to minimize switching losses that are classified into three main types: zero voltage switching (ZVS), zero current switching (ZCS), and zero current zero voltage switching (ZCZVS). Presented converters in [19]- [21] use the ZVS technique to decrease switching losses. In these converters, switches turn on under ZVS conditions, but they turn off under hard switching conditions, which provides switching losses. Also, in [20] and [21], the reverse recovery problem of diodes is solved. In [22]- [25], in the presented interleaved converters, switches turn on under ZCS condition, and the reverse recovery problem of diodes is solved, but switches turn off under hard switching conditions. ZVS turnon condition for switches will be more effective than the ZCS turn-on condition in reducing switching losses. Structures in [26]- [31] can provide a fully soft-switching condition for switches. Also, the reverse recovery problem is eliminated in these converters.
In previous works, some kinds of diode-capacitor voltage multiplier cells have been presented to step up a low voltage to a high output voltage [32]. Figs. 1(a) and 1(b) illustrate one of the diode-capacitor voltage multiplier techniques with AC non-isolated/isolated and DC input voltages, respectively. The diode-capacitor VM techniques have been used in a number of current fed structures as dual-input and singleinput interleaved structures [15]- [18]. One of these structures is illustrated in Fig. 1(c). The voltage gain of this kind of converter depends on the number of diode-capacitor VM cells. To increase the converter voltage gain, decrease the voltage stress across the semiconductors, reduce the switching losses, and add another designing freedom degree, an HF transformer is added to the converter and combined with the diode capacitor voltage multiplier stages [22]. The combination method is presented in Fig. 1(d). In the proposed converter in this figure, the power switches turn on under ZCS conditions. In addition to the mentioned techniques, to further increase the converter voltage gain and the designing freedom degrees and decrease the voltage stress across the semiconductors, coupled inductors can be utilized instead of inductors. In this technique, the coupled inductors are combined with the HF transformer and diode-capacitor voltage multiplier cells to provide three designing freedom degrees. By adding two auxiliary switch-capacitor voltage multiplier cells, the leakage inductances of the coupled inductances and HF transformer can be utilized to provide ZVS for the power switches, ZCS for the power diodes, and increase the converter voltage gain significantly. This paper presents eight new ultra-high step-up interleaved converters with various combinations of coupled inductors, HF transformer, and diode-capacitor VM cells.
In the presented converters, two different auxiliary active switch-capacitor VM circuits are utilized to provide ZVS for all of the power switches. Also, in the proposed converter all of the power diodes turn off and on under ZCS conditions. The presented converters provide three freedom degrees for their designers to work with low-rated semiconductors and provide ultra-high voltage gain with optimum duty cycles. Also, the utilized active auxiliary VM cells act as a clamp circuit to clamp the voltage stresses across the power switches and absorb the leakage inductances' energy to pass it to the output.
In this paper, section 2 describes the eight proposed converters along with different operational modes associated with one of them. Section 3 explains the steady-state analysis. In this section, the voltage gain of one of the proposed converters is calculated. Also, components, turn ratios, and the number of VM stages are designed. Section 4 presents efficiency analysis. In section 5, the control system of the proposed converter is presented. In section 6, the proposed structures are compared with more than twenty related converters. Also, in section 7, in order to validate the theoretical analysis, experimental results of a 1kW laboratory prototype are discussed. Finally, in section 8, a brief conclusion is presented.

II. PROPOSED CONVERTER AND OPERATIONAL PRINCIPLES
The equivalent circuits of the eight presented converters with M number of diode-capacitor VM cells are illustrated in Figs. 2 and 3. The proposed converters are composed of two coupled inductors, an HF transformer, two main power switches, some stages of diode-capacitor VM cells, and two stages of active clamp switch-capacitor VM cells. In these converters, utilizing the active auxiliary switchcapacitor VM stages not only enhances the output voltage but also provides ZVS turn-on for the main power switches.
The turn ratios of the coupled inductors, n 1 = n s1 /n p1 and n 2 = n s2 /n p2 , and HF transformer, N = N S /N P can be utilized to regulate the output voltage. Besides, the diode-capacitor VM stages are utilized to increase the voltage gain. As a result, the number of used stages depends on the required output voltage. Therefore, the turn ratios n 1 = n 2 = n, N, and the number of diode-capacitor VM stages M provide three degrees of freedom to the designer, which makes the design more flexible. In Figs. 2 and 3, S 1 and S 2 are the main power of the metal oxide semiconductor field-effect transistors (MOSFETs), and S Aux1 and S Aux2 are the auxiliary power MOSFETs, C 1 and C 2 are the clamp capacitors, V in and V out are the input and output voltages, respectively, and R out is the equivalent resistance of the load.
In Figs. 2 and 3, two combination patterns to combine the coupled inductors and the HF transformer with diodecapacitor VM cells are presented. In the first pattern, the secondary sides of the coupled inductors and HF transformer are connected in series. In the second pattern, the secondary sides of the coupled inductors are connected in series with the primary side of the HF transformer. In the secondary side of the HF transformer, VM cells are utilized where the diode and capacitor of the jth cell are introduced with D j and C VM j , respectively. To simplify describing the operational modes, a sample of the proposed converters (the converter presented in Fig. 2(a)) with four stages of diodecapacitor VM cells is selected. The key waveforms of the proposed converter are illustrated in Fig. 4. As illustrated in the figure, the gate signal of each auxiliary switch is the reverse form of its corresponding main switch. This converter has ten operational modes. The equivalent circuits of the proposed converter in different operational modes are shown in Figs. 5. In this figure, L Lk1 , L Lk2 , and L Lk are the leakage inductances of the coupled inductors and HF transformer, L m1 and L m2 are the magnetizing inductances of the coupled inductors.
Mode 1 (t 0 < t < t 1 ) (see Fig. 5(a)): In this mode, both the main power switches S 1 and S 2 are in the ON state. Also, all the other semiconductors are in the OFF state. Therefore, it can be written as follows, Mode 2 (t 1 < t < t 2 ) (see Fig. 5(b)): At t 1 , the power switch S 2 turns OFF. The parallel parasitic capacitors of S 2 and the auxiliary switch S Aux2 start being charged and discharged by i Lm2 , respectively. The main power switch S 2 turns off with ZVS condition because of the existence of the parallel parasitic capacitor C S2 . Due to the small values of parasitic capacitors C S2 and C SAux2 , their charging and discharging time is very short, and it can be calculated as, Mode 3 (t 2 < t < t 3 ) (see Fig. 5(c)): At t 2 , the voltage across the auxiliary switch S Aux2 reaches zero, and its anti-parallel body diode starts conducting. Also, the gate to source signal of the auxiliary MOSFET S Aux2 is applied, and this switch turns on when the current direction changes from negative to positive. Therefore, the power switch S Aux2 turns on under ZVS condition. The stored energy in the magnetizing inductance of the second coupled inductor L m2 causes charging in capacitor C 2 and discharging in capacitor C 1 . The conducting current through the secondary windings of the coupled inductors and transformer starts to charge the evennumbered VM capacitors (C VM 2 , C VM 4 , . . .) and discharge the odd-numbered VM capacitors (C VM 1 , C VM 3 , . . .).
The currents through the leakage inductances can be obtained as, Mode 4 (t 3 < t < t 4 ) (see Fig. 5(d)): At t 3 , the auxiliary power switch S Aux2 turns off. The currents value i LK 1 and i LK 2 start to decrease and increase, respectively. The current which flows through the secondary side windings starts to decrease to zero. The negative value of the current i Lk is more than the positive value of i Lk2 . Therefore, parasitic capacitors C S2 and C SAux2 start being discharged to zero and being charged to V C2 − V C1 , respectively. As a result, due to the existence of C SAux2 , ZVS turn-off for the power MOSFET S Aux2 is achievable. The duration of this mode can be achieved as, Mode 5 (t 4 < t < t 5 ) (see Fig. 5(e)): At t 4 , the voltage across the power switch S 2 reaches zero, and its anti-parallel body diode starts conducting. The currents through the secondary side windings and VM diodes continue decreasing to zero. In order to realize the ZVS turn-on for S 2 , its gate signal should be applied in this mode.
Mode 6 (t 5 < t < t 6 ) (see Fig. 5(f)): At t 5 , the power switch S 2 turns on under ZVS condition because its parallel body diode has been conducted before. Also, all the other semiconductors are in the OFF state.
Mode 7 (t 6 < t < t 7 ) (see Fig. 5(g)): At t 6 , the power switch S 1 turns off. The parallel parasitic capacitors of the main switch S 1 and the auxiliary switch S Aux1 start to be  and be discharged by i Lm1 , respectively. The main power switch S 1 turns off under ZVS condition, because of the existence of the parallel parasitic capacitor C S1 .
Due to the small values of capacitors C S1 and C SAux1 , their charging and discharging duration is very short, and it can be obtained as, Mode 8 (t 7 < t < t 8 ) (see Fig. 5(h)): At t 7 , the voltage across the main switch S 1 reaches V C1 , which causes the conduction of the anti-parallel body diode of the auxiliary switch S Aux1 . Also, the gate to source signal of the MOSFET S Aux1 is applied, and it starts to conduct when its current direction changes from negative to positive. Therefore, the power switch S Aux1 turns on under ZVS condition. The stored energy in the magnetizing inductance of the first coupled inductor L m1 charges the capacitor C 1 . The conducting current through the secondary windings of the coupled inductors and the transformer starts to charge the odd-numbered VM capacitors (C VM 1 , C VM 3 , . . .) and discharge the even-numbered VM capacitors (C VM 2 , C VM 4 , . . .) through the odd-numbered diodes (D 1 , D 3 , . . .), respectively. The current through the leakage inductance can be achieved as, Mode 9 (t 8 < t < t 9 ) (see Fig. 5(i)): At t 8 , S Aux1 turns off. The currents value i LK 1 and i LK 2 start to increase and decrease, respectively. The current that flows through the secondary side windings starts to decrease to zero. Also, the positive value of the current i Lk is more than the negative value of the current i Lk1 . As a result, the parasitic capacitors C S1 and C SAux1 start to discharge to zero and charge to V C1 , respectively. Therefore, the existence of C SAux1 provides ZVS conditions for the power MOSFET S Aux1 . The duration of this mode can be expressed as follows: Mode 10 (t 9 < t < t 10 ) (see Fig. 5(j)): At t 9 , the voltage across S 1 reaches zero and its anti-parallel body diode starts conducting. The currents through the secondary side windings and VM diodes continue decreasing to zero. In order to achieve the ZVS turn-on for S 1 , its gate signal should be applied in this mode. At t 10 , S 1 turns on, and the converter's operational cycle is repeated.

III. STEADY-STATE OF THE PRESENTED CONVERTER
To simplify the analysis, the short time intervals (t 1 − t 2 , t 3 − t 5 , t 6 − t 7 , and t 8 − t 10 ) and the leakage inductances of the coupled inductors and HF transformer are neglected. Also, it is assumed that all the passive elements and switches are ideal, and the voltages of the capacitors are constant during a switching cycle.

A. POWER DRIVER TOPOLOGY
By using the volt-second balance law for the magnetizing inductances L m1 and L m2 , these relations can be achieved as, where d is the duty cycle of the main power switches S 1 and S 2 . By utilizing (12)(13)(14)(15), the voltages across the VM capacitors are achieved as, The output voltage is the summation of the voltages across the capacitors C 2 and C VM 4 . Therefore, the output voltage is obtained as, The above analysis can be extended to a converter with M stages of diode-capacitor VM cells. Therefore, the output voltage of the proposed converter with M stages of VM cells can be expressed as, The voltage gain of the converter presented in Fig. 2(b) can be calculated by the method presented in (12)(13)(14)(15)(16)(17)(18). Therefore, the voltage gain of the converter is obtained as, With regards to (19) and (20), it can be concluded that the voltage gains of the proposed converters depend on the turn ratios of the coupled inductors and HF transformer and diode-capacitor VM stages. Therefore, n, N , and M are the three variables that make the design of these converters more flexible.
In (18), the obtained voltage gain is ideal, and the actual voltage gain is slightly smaller than (18). In fact, the leakage inductances and transformer cause the duty cycle losses that reduce the voltage gain. Therefore, the precise voltage gain of the proposed converter with four stages of diode-capacitor VM cells can be expressed as,

B. REALIZATION OF ZVS CONDITION FOR POWER MOSFETs
Due to the presence of parallel parasitic capacitors, the power MOSFETs turn off under near to soft conditions. The ZVS turn-on for the auxiliary power MOSFETs S Aux1 and S Aux2 are naturally realized due to the conduction of their antiparallel body diodes. In order to ensure ZVS turn-on for the main power MOSFETs S 1 and S 2 , the stored energy in the equivalent leakage inductance (L Lk L Lkj )/(L Lk + L Lkj ), which charges or discharges the parasitic capacitors C Sj and C SAuxj , should be more than the stored energy in the parallel parasitic capacitors. Therefore, this relation can be achieved: To provide the required conditions for the proposed converter to operate in continuous conduction mode (CCM), the average currents of the magnetizing inductances of the coupled inductors should be more than their half current ripple. The average currents of the magnetizing inductances of the coupled inductors for M stages of VM cells are achieved as, The current ripple of the magnetizing inductances is given by: Therefore, the critical values of the magnetizing inductances to ensure the CCM operation can be obtained as, In the third operational mode, when S 1 is in on state and S 2 is in off state, the voltage across the primary side winding of the HF transformer is expressed as, where B is the magnetic flux density variation and A e is the magnetic core equivalent area. The primary and secondary windings turns can be selected based on the proper transformer designing guidelines. The current through the secondary side of the transformer is the summation of the currents which flow through the diodes. Therefore, the RMS current value of the secondary winding is expressed as, The RMS value of the primary winding's current is equal to N × I Secondary RMS−Transformer . According to (29) and (30), the diameters of the primary and secondary windings of the HF transformer can be obtained. Furthermore, the RMS voltage across the primary winding of the transformer can be expressed as, The apparent power of the HF transformer can be obtained by multiplying its primary winding RMS voltage and current.

D. SEMICONDUCTORS DESIGN
To select proper power semiconductors for the proposed converter, their voltage and current stresses should be calculated. In the proposed converter with M stages of diode-capacitor VM cells, the voltage stresses on the power semiconductors are obtained as, Also, the voltage stress across the semiconductors for the presented converter in Fig. 2(b) can be expressed as, The average currents of the power MOSFETs are given by: The current stresses of the power diodes are given by:

E. TURN RATIOS AND NUMBER OF VM STAGE
By determining the output voltage and proper duty cycle of the power switches, the values of n, N , and M can be achieved. As mentioned before, the voltage stress on the power diodes decreases by increasing the number of diodecapacitor VM cells. Therefore, the number of VM cells is selected based on the peak inverse voltage V DMax of the available diodes. The number of diode-capacitor stages can be determined as, The voltage stresses of the power switches decrease by increasing the turn ratios n and N . The turn ratio of the coupled inductors n can be determined based on the voltage stress across the power MOSFETs S 1 , S 2, and S Aux2 as, In (42), V Main DS max is the peak inverse voltage of the selected power MOSFETs for S 1 , S 2 , and S Aux2 .
The turn ratio of the HF transformer can be obtained based on the voltage stress across the auxiliary power MOSFET S Aux1 as follows: where V Auxiliary DS max is the peak inverse voltage of the selected power MOSFET for S Aux1 . Therefore, the selected n, N , and M should confirm the obtained values from (41-43).

F. CAPACITORS DESIGN
The capacitor values can be designed based on their voltage ripple. Therefore, the values of the capacitors can be determined as,

IV. EFFICIENCY ANALYSIS
The efficiency of the proposed converter is calculated by considering the parasitic resistances of different elements. Primary and secondary equivalent series resistances (ESR) of the coupled inductors (primary r Lp1 and secondary r LS1 ) and HF transformer (primary r Lp2 and secondary r LS2 ), conductive resistances of the power MOSFETs (r DS ) and diodes (r DC ), the forward voltage of diodes (V F ), and ESRs of the capacitors (r C ) are considered to calculate the efficiency of the proposed converter. To simplify the efficiency calculations, the component's conduction currents are approximated by their average values. Also, the effects of the leakage inductances and the short time intervals (t 1 − t 2 , t 3 − t 5 , t 6 − t 7 , and t 8 − t 10 ) are ignored. Therefore, considering the parasitic values, the output voltage can be achieved as, where α, γ , β, and λ can be expressed as (47), as shown at the bottom of the page. The core losses of the magnetic cores are constant and directly depend on the converter switching frequency. Therefore, the core losses should be considered at high frequencies. The core losses for each magnetic core is obtained 3.34 W from its datasheet at 100 kHz switching frequency. As a result, the total core losses at 138 kHz switching frequency is equal to PCore = 13.83 W. Therefore, With regards to (46-48), it can be concluded that if the input voltage is considerably higher than the summation of the forward voltages of the VM diodes or the equivalent resistance of the load R out is significantly larger than the combined parasitic resistance of the components, the efficiency and voltage gain of the proposed converter would be high. Fig. 6 shows the voltage gain and efficiency of the proposed converter with different ESRs of the coupled inductors and HF transformer based on the values presented in Table 1 versus various duty cycles. As can be seen, the ESRs and duty cycle of the converter affect the voltage gain and efficiency. Also, operating with a high duty cycle reduces the efficiency and voltage gain considerably. The   power loss breakdown and estimated efficiency of the proposed converter for its laboratory prototype are presented in Table 1.

V. CONTROL SYSTEM OF THE PROPOSED CONVERTER
For the proposed converters, the pole placement control method can be a proper method to control the output DC voltage. This control method is completely explained in [2], [4], [13], and [22]. This control method deals with state variables directly to design the control compensators. Therefore, it can be a proper control method in power switching converters because in this kind of converters, state variables are accessible. The control circuit schematic of the mentioned control system is shown in Fig. 7(a). In this figure, K x and K q are the control coefficient matrixes of the control system. The closed-loop poles of the desired control system should be determined to reach the optimum phase margin (PM) and gain margin (GM) (60 • ≤ PM ≤ 80 • and GM ≥ 10) in its closed-loop control path. The bode plots of the single-input-single-output system after and before implementing the control system are shown in Fig. 7(b). As it can be seen in the figure, the phase margins of the closed-loop system before and after implementing the control system are obtained 0.188 • and 67 • , respectively. This means that the PM and GM of the control system are in their optimum areas.

VI. COMPARISON STUDY OF THE PROPOSED CONVERTERS
To prove the advantages of the proposed converters, the performances of the selected proposed circuits (Converters presented in Figs. 2(a) and 2(b)) are compared to five recently presented interleaved ultra-high step-up and high step-up topologies, and their results are tabulated in Table 2. The voltage gain comparison versus various turn ratios (n 1 = n 2 = N = n) is demonstrated in Fig. 8(a). It is clear that the proposed converters with four number of VM stages M = 3 can provide significantly higher voltage gain than the ultra-high step-up and high step-up converters.
The voltage stress comparisons of the power switches and power diodes are presented in Figs. 8(b) and 8(c). Considering these figures, it can be concluded that in the proposed converters, the voltage stresses across the power switches are significantly lower than other compared structures. Also, it is clear in Fig. 8(c) that the normalized voltage stress across the power diodes is low, even lower than 0.5 for M = 4.
In comparison to the converters presented in [5] and [24], which are benefited from coupled inductors, HF transformer, and diode-capacitor voltage multiplier techniques, the proposed converters can provide higher voltage gains and lower voltage stresses across the semiconductors with a lower number of components. Also, the proposed converters can provide ZVS for all of the power switches and ZCS for all the power diodes, which cannot be realized in the presented converters in [5] and [24]. Moreover, in the proposed converters the active clamp auxiliary VM circuits provide ZVS condition, enhance the converters' voltage gain considerably, and clamp the voltage spikes across the power switches. Where in the converters presented in [5] and [24], the mentioned multi-function of the clamp circuits is not realized. Also, the proposed converters provide three designing freedom degrees n, N , and M for their designer to η = P at P out + P Lacs =   work with low-rated semiconductors at optimum duty cycles. Whereas in the presented converters in [5] and [24], only two designing freedom degrees n and N are provided. Even in the other previously presented converters compared with the proposed converters, only one designing freedom degree n or N is provided. Consequently, in the proposed converters, the ultra-high voltage gain, optimum efficiency and cost are achievable by selecting the appropriate turn-ratios n and N , the number of diode-capacitor VM cells M , and the duty cycle.
The comparison results of the eight proposed converters with each other are summarized in Table 3. Although the voltage gain of the presented converter in Fig. 2(a) is significantly high, it can be increased just by utilizing the second pattern of the coupled inductors and the HF transformer combination. Also, utilizing this combination pattern reduces the voltage stress across the power switches considerably. Besides, the voltage stress across the capacitors can be decreased significantly just by using the second pattern of diode-capacitor VM cells (Figs. 3(a)-3(d)) instead of the first pattern of VM cells (Figs. 2(a)-2(d)). But on the other hand, just an even number of diode-capacitor VM cells can be utilized with the second pattern of diode-capacitor VM cells. Therefore, the design flexibility of the number of VM stages M will be limited to even values. Furthermore, the voltage stress across the clamp capacitors can be decreased by using the second pattern of auxiliary circuit (Figs. 2(c), 2(d), 3(c), and 3(d)). But this pattern separates the input ground port from the output port.

VII. EXPERIMENTAL RESULTS
In this section, in order to validate the theoretical analysis, a 1 kW laboratory prototype of the sample proposed converter is built. The parameters of the test converter are tabulated in Table 4. Also, the experimental results of this laboratory prototype are illustrated and analyzed completely.    Figs. 9-13 illustrate the experimental results of the proposed converter at 1kW output power. Table 5 compares the calculated voltage values with experimentally measured values. Figs. 9(a) and 9(b) show the voltage and current waveforms of the main power switches S 1 and S 2 . As it can be seen, before the turn-on moment of these switches, their anti-parallel diodes conduct negative currents. Consequently, these switches turnon under ZVS conditions. At the turnoff moment, the parallel capacitors of the power switches get charged, and the switches' voltages increase with a mild slope. Therefore, a soft-switching condition is provided for switches' turn-off. Figs. 10(a) and 10(b) illustrate the voltage and current waveforms of the auxiliary power switches S AUX 1 VOLUME 9, 2021  and S AUX 2 . Similar to the main switches, auxiliary switches turn on under ZVS conditions by discharging their parallel capacitors and conducting their anti-parallel diodes. Also, due to charging of their parallel capacitors with mild slopes, the soft-switching condition is provided for the auxiliary switches' turn-off.
The experimental voltage and current waveforms of the VM diodes D 3 and D 4 are illustrated in Figs. 11(a) and 11(b). As it can be observed, the VM diodes turn on under ZCS condition, and their current falling rates are controlled by the equivalent leakage inductance of the coupled inductors and HF transformer. Therefore, the reverse recovery losses are decreased significantly. Figs. 12(a) and 12(b) show the current waveforms of the leakage inductances of HF transformer (i Lk ) and coupled inductors (i Lk1 and i Lk2 ), respectively. From 13(b), it can be seen that the currents i Lk1 and i Lk2 have reverse changes that reduce the input current ripple noticeably. Fig. 13(a) illustrates the input current and the voltage waveform of the capacitor C 2 . As can be seen, due to the reverse changes of leakage inductances' current, the input current ripple is very low. Also, the capacitor C 2 has an almost constant voltage that provides a constant dc voltage in output. Fig. 13(a) shows the input and output voltages. From this figure, it can be seen that when the duty cycle and the input voltage are 66% and 20 V, respectively, the proposed converter can provide 500 V output voltage. Finally, it can be concluded that the experimental results confirm the theoretical analysis.
The experimental and theoretical efficiencies of the proposed converter versus different output powers (0.2 kW-1 kW) with a 20 V input voltage are illustrated in Fig. 14. As can be seen, the maximum efficiency is measured 96.41% at 700 W output power. The experimental efficiency of the laboratory prototype is obtained 96.32% at 1000 W output power which is 0.76% lower than the calculated value (97.08%).

VIII. CONCLUSION
In this paper, eight interleaved ultra-high step-up dc-dc converters with ZVS performance are proposed. A detailed steady-state analysis, comparison study, and experimental results of one of the interleaved ultra-high step-up dc-dc converters are presented to verify the following features of the proposed converters: 1) The number of diode-capacitor VM cells M , turn ratios of the coupled inductors n and the HF transformer N are three designing degrees of freedom to extend the voltage gain for operating with optimum duty cycles and work with low rated semiconductors at high voltage gains.
2) The active auxiliary switch-capacitor ZVS circuit is implemented not only to provide ZVS conditions for the main power switches S 1 and S 2 but also to clamp the voltage spikes across the power switches and increase the voltage gain.
3) The voltage stresses across the power switches are low and can be lower by increasing the number of the diode-capacitor VM stages M and turn ratios n and N . Therefore, MOSFETs with low conducting resistance can be adopted, which decreases the conduction losses and cost. 4) The ZVS performance is achieved for the power switches, and the reverse recovery losses of the power diodes are reduced.

5) Utilizing coupled inductors instead of inductors leads
to optimum utilization of cores which improves the power density. 6) According to (26) and (27), the magnetizing inductances of the coupled inductors are reduced to ensure the CCM operation by simultaneous implementation of the HF transformer and coupled inductors. Therefore, the coupled inductors' core volume is reduced. 7) Recycling the stored energy in the leakage inductances and passing it to the output, which helps to achieve high efficiency. 8) Simple control and triggering the gate signals like the conventional interleaved converter. Previously, he also worked with Multimedia University as a Lecturer for three years. He has more than 22 years of academic experience and authored or coauthored 410 papers in international journals and conference proceedings. He has been cited highly for his work in the control of renewable and distributed power generation. His research interests include distributed generation, solid state transformer, power converters, power electronic applications, renewable energy, solar PV, wind turbines, wave energy, electrical vehicles, smart grids, micro-grids, standalone power supply, power grids, and power system planning and control. He is a fellow of the Institution of Engineers Australia (FIEAust) and U.K. Institution of Engineering and Technology (FIET).