A New Transformerless Ultra High Gain DC–DC Converter for DC Microgrid Application

High gain dc-dc converters are used in several applications which include solar photovoltaic system, switch-mode power supplies and fuel cells. In this paper, an ultra-high gain dc-dc boost converter is proposed and analyzed in detail. The converter has a gain of six times as compared with the boost converter. The high gain is achieved by utilizing switched inductors and switched capacitors. A modified voltage multiplier cell (VMC) with switched inductors is proposed. The converter has a single switch which makes its operation easy. Moreover, the voltage across the switch, diodes and capacitors are less than the output voltage which increases the overall efficiency of the converter. The converter performance in steady-state is analyzed in detail and it is compared with other latest high gain converters. The working of the converter in non-ideal conditions is also discussed in detail. The loss analysis is done using PLECS software by incorporating the real models of switches and diodes from the datasheet. To confirm and validate the working of the proposed converter a hardware prototype of 200 W is developed in the laboratory. The converter achieves high gain at low duty ratios and its performance is found to be good in open and closed loop conditions.


I. INTRODUCTION
Power electronics play an important role to extract maximum energy from renewable and clean energy sources. Figure 1 shows a schematic of a DC microgrid. High gain dc-dc converters act as a medium between the load and the source and boost the low voltage(12V-60V) generated by the battery, solar photovoltaic (PV) and fuel cell to high DC voltage(200-300V). Moreover, a high gain dc-dc converter in a DC microgrid maintains the dc-link voltage to the desired value [1]. A combination of supercapacitors and a high gain dc-dc converter is also employed nowadays in a DC microgrid because supercapacitors have high power density but a low voltage rating. High gain converters are nowadays used in The associate editor coordinating the review of this manuscript and approving it for publication was Ton Duc Do . level three fast charging of electric vehicle (EV). A combination of a high gain converter with an inverter can be used to feed AC loads in islanded mode operation of a DC microgrid. High gain converters have gained prominence because the traditional boost converters and their variants [1] are associated with poor efficiency and high duty cycle operation to achieve the high gain. Also, there is a problem of reverse recovery in the diode at an increased duty cycle. These converters are broadly classified into isolated and non-isolated structures. Isolated converters isolate the output from the input electrically dividing circuit into two separate sections preventing the direct flow of current. This is achieved by using a high-frequency transformer but it increases the size and cost [3]- [6] of the converter. Isolated topologies are favoured in high power applications and where common ground between source and load is required. Non-isolated converters are favoured where isolation of input from output is not required. They can be classified as coupled and non-coupled types [7]. The coupled inductor topologies can produce very high voltage gain with low stress on the semiconductor switch but the problems with leakage inductance can result in large voltage spikes across the switch for which a clamped circuit needs to be designed. To achieve a high gain capacitor-diode voltage multiplier cell and cascading of two or more converters is employed. Several new and modified topologies use voltage multiplier circuit (VMC) made of switched capacitors and inductors to increase the gain of the converter. The quadratic boost (QBC) and cubic boost topologies can produce high gain at low duty cycles with reduced stress on switching devices [8]- [10] but at higher duty ratios the efficiency may decrease with an increase in current. Further, the inductor core is more prone to enter saturation at higher duty cycles. In [11] a new quadratic boost converter is proposed with lower inductor current ripple and low stress across the switch. Another class of high gain boost converter is a quasi-z-source or z-source converter that is used to increase the gain of the converter where the inductor is replaced by an impedance network but these converters have a restricted duty cycle [12], [13] operation. Interleaved boost converters are being used to acquire high output voltage and high efficiency [14] with a lesser number of switches. In a multiphase interleaved converter is introduced along with a z-source network to achieve high gain. The input current ripple is low therefore there the need for an input filter does not arise. The problem with interleaved converters is that a voltage boost circuit is needed at the end to increase the gain [15] of the converter. Several new converter topologies have been discussed in [16] with the well-known Cockcroft-Walton voltage multiplier cell. A new single-ended primary inductor converter (SEPIC) is presented in [17] with a single switch is used to achieve high gain. Another new SEPIC converter with both buck and boost topology is presented in [18]. Single input multiport output is a good way of getting different output voltage using a single input. These converters have better voltage regulation capability and low stress across the output capacitor as compared to single input [19], [20] singleoutput (SISO) converter. They can be used as individual SISO converters.
A quadratic boost converter is proposed by using the voltage lift technique (VL) in [21]. In [22] VL technique is used to get desired value of gain but the converter utilizes two switches that are switched alternately. A hybrid converter based on voltage multiplier cell (VMC) and switched capacitor cells with high gain is presented in [23]. It overcomes shortcomings such as high voltage and current stress on the power devices. A converter with a similar gain is presented by authors in [24] but the stress on two switches is different and it uses the diode voltage capacitor multiplier and switched inductor voltage multiplier to achieve high gain. A high step-down interleaved converter is presented in [25] using a similar concept of switched/series capacitor using six switches. A novel switched impedance network-based converter is presented in [26]. It utilizes a voltage doublerswitched capacitor network to achieve higher gain at lower duty ratios. A multistage structure can significantly increase the gain but efficiency can be low due to a greater number of components. A hybrid zeta boost converter with a switched inductor is proposed in [27] but its voltage gain is not very high. A new tranformerless active switched network is presented in [28] by using two switches but the gain achieved is lower than the proposed topology in this paper. A switched capacitor network-based topology is presented in the paper [29]. In [30] the switched inductor topology has used two inductor and two switches but the voltage gain is not very high. A modified SEPIC converter is presented in [32] to achieve high voltage gain. In [34] the converter uses parallel input and series output (PISO) technique to increase voltage gain. Furthermore, the stress voltage of switches and diodes has been reduced.
In this article, the proposed high gain converter has a VMC made up of switched inductors. A combination of switched capacitors and VMC achieves ultra-high gain with only one switch and two inductors. High gain topologies proposed in [28]- [31] utilize two switches and have much less voltage gain as compared with the proposed converter in this paper. The attractive features of the proposed converter are • The converter achieves a voltage conversion ratio of six times that of the conventional boost converter.
• The converter uses a single switch that has low voltage stress i.e. one-third of output voltage.
• A coupled inductor is not used so the problem of leakage inductance is avoided.
• The voltage stress on all the semiconductor devices is equal. The devices with a uniform rating and low internal resistance can be used. The paper discusses the structure and principle of operation of the converter in section II. Steady-state operation of the proposed converter in the continuous and discontinuous mode of operation is presented in section III and IV respectively. In section V and VI non-ideal gain analysis  [29] (2021) (c) Switched-capacitor with Z network in [30] (2021) (d) Proposed (SC-SL-DC) converter. and comparative study of the proposed structure is presented respectively. Experimental results and efficiency of the converter are shown in section VII. In section VIII conclusion is presented.

II. OPERATING PRINCIPLE OF PROPOSED CONVERTER (SC-SL-DC) A. CIRCUIT DESCRIPTION
The proposed dc-dc converter topology is presented in Figure 2. The converter consists of a single switch (S), two inductors (L 1 and L 2 ), seven diodes (D 1 , D 2 , . . . , D 7 ) and six capacitors including one capacitor C o as an output filter which filters the output pulsating current and provide a smoothed output voltage. The combination of (L 1 , L 2 , D 1 , D 2 and C 1 ) is a modified switched capacitor cell while the combination of (C 1 , D 1 , C 3 and D 4 ) is switched capacitor cell. Some important waveforms for the proposed converter are shown in Figure 3. All capacitors are sufficiently large, therefore the voltage across capacitors is assumed to be constant. And all components are assumed as ideal.

B. MODES OF OPERATION
This converter can be operated in both CCM and DCM modes of operation. The CCM operation of the proposed converter has two modes. In the first mode when the switch is conducting and the second one is analyzed when the switch is turned OFF. Analysis of the proposed converter for one switching period under CCM mode and in steady-state is as follows Mode I of operation is shown in Figure 4(a). In this interval, the switch is turned ON and the diodes D 2 , D 3 , D 5 and D 7 are forward biased. The voltage across inductors L 1 and L 2 is equal to the input voltage (V in ) by which they are magnetized and therefore, inductor currents I L1 and I L2 increase linearly. In this mode, Capacitor C 1 discharges and transfer its energy through capacitor C 5 and load. During this interval, C 2 and C 3 discharge through L 2 and C 4 . Thus, related equations can be drawn out as follows: The voltage across inductors appears as shown (1) The voltage across capacitors is derived from Figure 4(a) using KVL and KCL as follows: Current relations through capacitors, inductors, diodes and switch can be estimated as follows: In this interval, the switch is turned OFF and the diodes D 1 , D 4 and D 6 are forward biased and the other three diodes are reversed biased. The circuit diagram is shown in Figure 4(b). During this interval, V in charges C 1 and L 1 charges C 2 . Inductor L 2 transfer its stored energy to C 3 . Output capacitor C 0 transfer its energy to load R.
Using KVL and KCL in mode II, the voltage across inductors come out as follows: In (2), it is derived that Equation (4) can now be written as The voltage across the capacitors can be written by applying KVL in Figure 4 Current passing through capacitors relations can be shown as follows:

A. CALCULATION OF CAPACITOR VOLTAGES AND VOLTAGE GAIN
Applying the principle of volt-second balance on inductors L 1 and L 2 and using (1), (2), (4) and (6) the voltage conversion ratio, M can be derived as shown.
where, T S is switching time period. Using this equation following results can be drawn out as.
It is clear from (8), that From (6) it can be written that Using (9) in (6) the following equation can be written Again from (2) Solving (10) and (11), it can be shown that From (2) again, Also, from (6) Putting this value in equation (13), it can be shown that Using (12) and (15), it can be drawn out easily.
From (9) and (16), voltage gain is derived as, According to (17), it can be seen that the voltage gain of the proposed converter is six times higher than that of the conventional boost converter.

B. VOLTAGE AND CURRENT STRESSES OF POWER DEVICES
In Figure 4, by applying KVL the voltage appeared across the switch (V SW ), diodes (V D ) and capacitors (V C ) when they are not conducting, can be expressed as The stress on different semiconductor devices is shown in Figure 9.
Assuming a lossless circuit, it can be written where I in and I 0 are input and output currents respectively. From (19) and (17), it can be written down: From (20), dc input current can be calculated as, Applying the principle of current balance on the capacitors C 1 and C 2 and using (3) and (7) it can be written as: After solving the above equation, the average current through inductors can be found out as The dc values of current through the semiconductor devices can be found as

C. SELECTION OF INDUCTORS AND CAPACITORS
For a given suitable value of ripple of inductor currents I L1 and I L2 at a fixed value of switching frequency f s for this converter, inductances can be extracted from (1) as: Moreover, within the valid range of voltage ripple, the value of capacitances can be calculated from (3) and (7) as: To obtain the desired output voltage at the given input voltage, duty cycle D can be calculated. From (17), the duty cycle is:

IV. EFFECT OF UNEQUAL INDUCTANCES ON VOLTAGE GAIN
The operation of the converter depends on the inductance values of inductor L 1 and L 2 . The current through the inductor will have different slopes and it will change the current waveform of the inductor due to different values of inductances of L 1 and L 2 .
The current waveform through the inductor L 1 and L 2 is shown in Figure 5. The converter SC-SL-DC is operated in three modes.
The Switch is turned ON. This mode is same as Mode I and the equivalent circuit is shown in Figure 4(a). Diode D 1 , D 4 , D 6 are reverse biased while the diodes D 2 , D 3 , D 5 and D 7 are forward biased. The voltage across the inductors L 1 and L 2 is equal to input voltage by which they are magnetized and therefore, inductor currents I L1 and I L2 increase linearly with different slopes. The slope of inductor currents of L 1 and L 2 can be achieved as In this mode the current through L 1 is less than current through L 2 because the inductance value of L 1 > L 2 .
Switch is just turned OFF. This mode occurs for a very duration of δT S as shown in Figure 5(a). The equivalent circuit in this mode is shown in Figure 5(b). Diode D 1 , D 3 , D 4 and D 6 are forward biased while the diodes D 2 , D 5 and D 7 are reverse biased. Inductor current I L1 is smaller than I L2 as shown in Figure 5(a). The current through L 1 has positive slope and magnetizes in this period and the current L 2 has large negative slope and discharge in this period. The current through D 3 will be difference between inductor current I L2 and I L1 .
The slope of inductor currents of L 1 and L 2 can be achieved as In this mode the current through L 1 is less than current through L 2 because the inductance value of L 1 > L 2 and this mode ends when I L1 = I L2 and converter operates in Mode III.
Switch is OFF. The equivalent circuit is same as Mode II in CCM as shown in Figure 4(b). Diode D 1 , D 4 , D 6 are forward biased while the diodes D 2 , D 3 , D 5 and D 7 are reverse biased. The inductors L 1 and L 2 are in series and the current through inductors L 1 and L 2 are equal and demagnetize with equal negative slope which can be achieved as follows The average of voltage across the inductor is zero. Therefore, Also, On solving (33)-(35), the voltage gain of proposed converter SC-SL-DC can be obtained as The voltage gain is same as equation (17) but the average value of inductor current L 1 is less than inductor current L 2 .
The current waveform through the inductor L 1 and L 2 is shown in Figure 6. The converter SC-SL-DC is operated in three modes as discussed below The Switch is turned ON. This mode is same as Mode I and the equivalent circuit is shown in Figure 4(a). Diode D 1 , D 4 , D 6 are reverse biased while the diodes D 2 , D 3 , D 5 and D 7 are forward biased. The voltage across the inductors L 1 and L 2 is equal to input voltage by which they are magnetized and therefore, inductor currents I L1 and I L2 increase linearly with VOLUME 9, 2021 In this mode the current through L 2 is less than current through L 2 because the inductance value of L 1 < L 2 .
Switch is just turned OFF. This mode occurs for a very duration of δT S as shown in Figure 6(a). The equivalent circuit in this mode is shown in Figure 6(b). Diode D 1 , D 2 , D 4 and D 6 are forward biased while the diodes D 3 , D 5 and D 7 are reverse biased. Inductor current I L2 is smaller than I L1 as shown in Figure 6(a). The current through L 2 has positive slope and magnetizes in this period and the current L 1 has large negative slope and discharge in this period. The current through D 2 will be difference between inductor current I L1 and I L2 .
The slope of inductor currents of L 1 and L 2 can be achieved as In this mode the current through L 2 is less than current through L 1 because the inductance value of L 1 < L 2 and this mode ends when I L1 = I L2 and converter operates in Mode III.
Switch is OFF. The equivalent circuit is same as Mode II in CCM as shown in Figure 4(b). Diode D 1 , D 4 , D 6 are forward biased while the diodes D 2 , D 3 , D 5 and D 7 are reverse biased. The inductors L 1 and L 2 are in series and the current through inductors L 1 and L 2 are equal and demagnetize with equal negative slope which can be achieved as follows The average of voltage across the inductor is null. Therefore, On solving (43)-(45), the voltage gain of proposed converter SC-SL-DC can be obtained as From equation (36) and (46) it can be seen that the voltage gain is unaffected with unequal values of inductances L 1 and L 2 i.e. six times the traditional boost converter (TBC).
However, the average value of current through the inductors are changed.

V. STEADY STATE ANALYSIS IN DCM
This mode is the same as Mode I of CCM mode and equivalent circuitry is depicted in Figure 4 This mode is equivalent to mode II of CCM. All the inductors demagnetize from their maximum value to zero at time t 2 = D 1 T.  In this mode, all diodes D 1 -D 7 are reverse biased. Inductor current in this interval (t 2 < t < t 3 ) is zero. Energy is provided by capacitor C o to load R. The equivalent circuit diagram and associated waveforms are depicted in Figure 7 and Figure 8.
Applying the volt-sec balance principle on the inductors yields the following relation Using the value of D 1 from (47) in (50) the following quadratic equation is obtained  Defining β L = 6Lf S R as normalized inductor time constant, the ideal voltage gain (M DM ) in DCM mode is calculated as If the converter is to be operated at the boundary of CCM and DCM, then the voltage gain of both modes will be equal. The normalized inductor time (β L,B ) constant at the boundary is calculated as A plot between β L,B and duty ratio D is shown illustrated in Figure 8. The converter operates in CCM mode if β L > β L,B and the reverse is true for DCM mode.

VI. PRACTICAL MODEL OF THE PROPOSED CONVERTER
The equivalent circuit of the proposed converter is shown in Figure 11. R L is the equivalent series resistance (ESR) of the inductor R SW is the switch ON-state resistance, R DS and V CN denote the diode internal resistance and voltage drop respectively. R C is the equivalent series resistance (ESR) of the capacitors.

A. EFFECT OF NON-IDEALITIES ON VOLTAGE GAIN 1) EFFECT OF NON-IDEAL INDUCTORS ON VOLTAGE GAIN
The effect of non-ideal inductors having parasitic resistances on voltage gain is analysed and other elements are assumed ideal.
The voltage across inductor L 1 and L 2 in both modes can be found as: MODE I: The useful voltage relations are:

MODE II:
The useful voltage relations are: Therefore, MODE I: The inductor voltages are

MODE II: The inductor voltages are
Since the average value of the voltage inductor is zero in the switching time interval.
The ratio of output voltage to the input voltage is derived using (58) where I L R L = V LD is the drop across R L Using the value of I L from expression (22) The effect of non-idealities on voltage gain is given by (59) and (61) in the CCM mode of operation of the converter and the plot of both the expression is presented in Figure 12 and Figure 13.

2) EFFECT OF NON-IDEAL SWITCH ON VOLTAGE GAIN
The voltages across the inductors in both modes can be found as: MODE I: The useful voltage relations are:

MODE II:
The useful voltage relations are: Since the average value of voltage across the inductor is zero. Therefore, the expression can be derived as follows The ratio of output voltage to the input voltage is derived using (66) where I S R Sw = V SD is the voltage drop across the switch.
Using the value of I SW from expression (23) The effect on voltage gain is given by (67) and (69) and the plot of both the expressions are shown in Figure 14 and 15a respectively. From Figure 15a it can be inferred that the gain rapidly decreases with an increase in the parasitic resistance of the switch, especially at higher duty ratios.

3) EFFECT OF NON-IDEAL DIODES ON VOLTAGE GAIN
The effect of non-ideal diodes (D 1 -D 7 ) having parasitic resistance (R D ) and forward cut in voltage (V CN ) on voltage gain is analysed and other elements are assumed ideal.
MODE II: The inductor voltage relations are: Since the average value of voltage across the inductor is null. Therefore, the expression can be derived as follows The effect on voltage gain is given by (75)

4) EFFECT OF ESR OF CAPACITORS ON VOLTAGE GAIN
The ON and OFF state current through the capacitors is found using (3) and (7). The effect of ESR of capacitors (C 1 to C 5 ) on voltage gain is analysed and other elements are assumed ideal.
The voltage across inductor L 1 and L 2 in both modes can be found as: MODE I: The useful voltage relations are:

MODE II:
The useful voltage relations are: Since the average value of voltage across the inductor is zero. Therefore, the expression can be derived as follows Using (77) in (84) For simplicity, it is assumed that Figure 15(b) shows the variation in gain when the capacitor resistance is increased. The gain decreases especially at higher duty ratios and low value of load resistance.

5) COMBINED EFFECT OF NON-IDEALITIES ON VOLTAGE GAIN
The combined effect of all parasitic elements on voltage gain can be found by considering all the non-idealities of components of the proposed converter.
The deviation from voltage gain can be obtained as follows where I O = V O R is output load current. The combined effect of non-idealities on the voltage gain can be derived as where,

B. POWER LOSS ANALYSIS OF THE PROPOSED CONVERTER 1) LOSSES IN PROPOSED CONVERTER DUE TO SWITCH
The practical power switch has conduction and switching losses. The conduction loss in the switch during the ON state by the parasitic resistance R SW.
where I SW rms is root mean square value of switch current and it is equal to where P O is the output power of the resistive load.
The switching loss (P Sw switching ) of the power switch can be calculated with the approximate relation shown in (95).
where, t r = total rise time of the switch, t f = total fall time, f s = switching frequency.
Total loss in the switch (P SW loss total ) is the sum of conduction and switching loss and can be expressed as As compared to conduction loss the switching loss in the diode is neglected and only conduction losses are taken into consideration. It is assumed that all diodes have equal resistance R DS and equal cut in voltage V CN . The conduction loss due to parasitic resistance (P D r ) is calculated using The conduction loss (P D CN ) due to cut in voltage in forward biased is calculated using Total conduction loss in the diode (P D loss ) is the sum of both losses P D loss = P D r + P D CN = I 2 D rms R DS + V CN I D dc (102) Total conduction losses due to in the proposed converter is the sum of all losses in the diodes The root mean square value of current through the diodes is expressed as below The total conduction losses in the two inductors are P L loss total = I 2 L1 rms r L1 + I 2 L2 rms r L2 (109) Using equation (22) to find the value of root mean square (rms) value of inductor currents.
or it can be equivalently written as It is assumed that the ESR value of both the inductors are equal (r L1 = r L2 = r L ) then total loss in the inductor can be expressed as The power loss in the capacitors due to series resistance is The total losses in the proposed converter are the sum of losses due to all the capacitors i.e.
The rms value of current through capacitors can be calculated using the formula The values of rms currents through capacitors can be earned using (3), (7) and (115) Summation of all individual losses occurring in capacitor gives total losses occurring due to capacitors in the proposed converter P C loss total = P C1 loss + P C2 loss +P C3 loss + P C4 loss +P C5 loss (117) If it is assumed that Hence total in the proposed converter is the sum of all the losses occurring in the proposed converter that is  expressed below. P loss total = P SW loss total +P D loss total +P L loss total +P C loss total (119) The efficiency (η) of the proposed converter can be expressed as below

VII. PERFORMANCE ANALYSIS WITH SIMILAR CONVERTERS
A detailed comparative analysis has been carried out and two traditional topologies and a few very recent high gain converter topologies have been considered. The analysis is based on the number of components, voltage gain and voltage stress across switches as given in Table 1. When compared to conventional boost and conventional quadratic boost converter the proposed topology can obtain a higher gain and the switch stress is considerably low. The converter in [8], adopts two switches and four inductors but its voltage gain is found to be lower than the proposed converter. The converter in [11] also has a lower voltage gain and higher switch stress than the proposed topology. The converter in [18] uses a total of four inductors which makes the converter bulky and the voltage gains are also low. Converters in [21], [22] and [28] have a relatively lower component count but the voltage gains are substantially less. The converter in [24], has a total of three switches (which could make the control of the converter complicated) but the voltage gains are less and switch stress is found to be higher. In [27] the topology has employed five inductors, two switches and a total of 18 components, and the increased count of components results in increased size of the converter and inefficiency and its voltage gain is quite low as compared to the proposed topology. Voltage gains of the converter proposed in [31] are also considerably less than the proposed converter. The converter in [32] has a total component count of 16 equal to the proposed converter including 3 inductors and 7 capacitors, but the voltage gains are considerably less than the proposed topology. Converter in [4] has adopted a total of 4 switches in its proposed circuit which can make the converter control very complex as compared to a single switch in the topology in this literature and even then, the voltage gains are lower. For comparison, a plot of the voltage gain(M) versus the duty ratio(D) for the proposed topology and other similar converters is shown in Figure 16. It can be observed that the proposed topology gives the highest voltage gain even at low values of the duty ratio(D). A gain of almost ten times can be achieved at a duty of 0.4. High gain at a lower duty ratio reduces the current stress of the converter. The voltage gain of converters in [27], [11] is slightly higher than the proposed topology when it is operated at duty ratio values close to D = 0.8 but the switch stress is also high at these extreme values of the duty ratio. The plot of voltage stress vs the voltage gain is shown in Figure 17. It can be inferred from this plot that the proposed converter has one of the lowest voltage stresses across the switch.
Based on the comparison results the proposed converter topology is more advantageous as it can achieve high voltage gain, low voltage stress and is controlled by a single switch.

VIII. STATE SPACE MODEL OF THE PROPOSED CONVERTER
To derive the small signal state space model small resistances with capacitors C 1 , C 2 and C 5 are considered. These resistances are used to simplify the analysis and to eliminate the invalid variables from the state space representation. Assuming the same value of inductors, the inductor current is represented by a single state variable. All the capacitors except the output capacitor have same value. The dynamic equations in ON and OFF state can be represented as shown in equation (123) and equation (124).
The converter operates in ON mode with a time d(t) and in OFF mode with a time (1-d(t)). The averaged model by combining (123) and (124) can be obtained and written as shown in (125), as shown at the bottom of the next page.
After perturbation when all the state variables are written in terms of dc signal and small signals as shown in (126) Table 2. is depicted in Figure 18. From the bode plot of uncompensated system it can be observed that the phase margin at the gain crossover frequency is only 10 o  which is not desirable. For closed loop stability of the system, the desirable phase margin should be between 45 o to 65 o to achieve good step response of the system.

1) VOLTAGE CONTROLLER DESIGN USING PLECS SOFTWARE
Using PLECS software the uncompensated bode plot can be observed and a proper controller can be designed. A PI controller usually works well for the lower order system. From the uncompensated bode plot it can be observed that the system is stable but it has zeroes in right half plane. To achieve proper phase margin a compensator is designed to remove the steady state error and remove the disturbances at high frequencies, for which the poles are added up at 0 rad/s and 10000 rad/s respectively. Zeroes are added at frequencies of 100rad/s and 1000 rad/s to achieve the desired phase margin. The compensator transfer function is given by (128) G c (s) = 10(s + 1/100)(s + 1/1000) s(s + 1/10000) (128) From the Figure 18 of the compensated closed loop plot it can be observed that phase margin of closed loop system is 63 o at the gain crossover frequency which shows that the closed loop system is stable.

IX. LABORATORY PERFORMANCE OF THE PROPOSED CONVERTER
The performance of the proposed converter is determined by building the hardware prototype as shown in Figure 19(a) in the laboratory. The converter is operated at a duty ratio of 40% and 30% in continuous conduction mode at a switching frequency of 50kHz. The design specifications of the presented VOLUME 9, 2021 converter are listed in Table 2 and the experimental set-up is shown in Figure 19(b). As depicted in Figure 20 measured input and output voltage are 12V and 117V respectively. The output voltage is reduced due to the effect of the parasitic resistance of the diodes, switch, capacitors and inductors. In the same Figure, the ripple observed in the output capacitor (C o ) is two per cent (2%) of V o that is about 2.24V. The drain to source voltage of the power MOSFET (S) is presented in Figure 20 with respective gate to source signals (V gs ). The maximum value  is found to be 40V which is approximately 34% of the output voltage (V o ). When the power switch is triggered using the respective gate signal both the inductor L 1 and L 2 magnetize from 1.2A to 1.6A. The inductor current peak to peak ripple is about 0.2A (15%) which is near to the value used to design the inductors and when the MOSFET is turned OFF the inductor demagnetize with the effect to reduce current linearly. The average value of both the inductor current is found to be 1.36A. The inductor currents are found to be continuous. Figure 22 and 23 shows the voltage across the capacitors C 1 , C 2 , C 3 , C 4 and C 5 and is found to be 25.8V, 10.5V, 38.8V, 78.2 and 35.5V respectively with very low voltage ripple and is much less than the output voltage. The voltage across the output diode D 7 is shown and equal to 40V which is the same as the stress across the switch and less than the output voltage equal to 34%. All the results show that the converter is smoothly working in continuous conduction mode.   Additional results to verify the working are obtained at D = 0.3 and V in = 12V. As depicted in Figure 24 for an input of 12 V the output voltage is found to 96 V. The drop in the voltage is due to parasitic and ON state resistances. As shown in Figure 25, the voltage across capacitors C 2 , C 3 and C 4 are   found to be 10.2 V, 32 V and 60 V respectively. The capacitor voltages are constant with ripple in the voltage close to 2 V.
As can be seen from Figure 26, the voltage stress across the switch (V sw ) is observed to be 32 V which is one-third of the V o .
The converter performance is also tested in dynamic conditions when the duty cycle is changed from D = 0.3 to    Figure 27, it can be seen that the output voltage varies from 132 V at D = 0.3 to 150 V at D = 0.4. From the experimental results, it can be concluded that the converter performance is satisfactory in both steady-state and dynamic conditions. Figure 28 shows the response of the converter when load is decreased to 70% at D = 0.45 at Vin = 15V. Also, the load current is increased as depicted in the same Figure. This shows that the regulation of the  converter is good when load is changed. The output voltage is maintained between 160 V and 150V. Figure 29 shows the experimental voltage gain with the change in the duty cycle. For the same value of load resistance, the gain decreases at a higher duty cycle due to an increase in losses. The efficiency at different values of output power is shown in Figure 30. It can be seen from the plot that at constant output power as the voltage is increased from 12V to 24V the efficiency of the converter increases. This is because to achieve the same power output the current decreases with the increase in output voltage. As a result, the conduction losses decreases and efficiency increases. The power loss in different components in percentage is shown in Figure 31. The maximum loss occurs in diodes as shown in Figure 32. The selection of devices with a low value of parasitic resistances increases the overall efficiency of the converter.

A. CLOSED LOOP VALIDATION USING TYPHOON-HIL REAL TIME EMULATOR
The performance of in closed loop operation is tested using hardware in loop (HIL) operation using Typhoon-HIL-402 real time emulator. The Typhoon-real time emulator is designed to check the performance of controller in real time. The results with change in input voltage and change in load are shown in Figure 32 and Figure 33. From Figure 32 it can be observed that as the input voltage is changed from  12 V to 17 V the output voltage is held constant at 120 V. Similarly, when load current is increased from 1.2 A to 2.2 A by decreasing the load resistance from 120 to 55 the output voltage is held constant by the voltage controller as shown in Figure 33. It can be concluded that the voltage controller is able to maintain the V o at reference value.

X. CONCLUSION
In the proposed work, the converter (SC-SL-DC) has produced a voltage gain with a single switch and voltage multiplier cell made up of switched inductors. The voltage gain of the converter is found to be near 9.75 times at a duty ratio of 0.4 and 8 times at a duty of 0.3. which is high as compared with the quadratic boost converter and other high gain converters. The converter utilizes only two inductors which makes the converter light in weight. It is found that the high value of parasitic resistance of switch and inductors decreases the gain of the converter. Low voltage stress across capacitors leads to the selection of low voltage rating capacitors, which increases the efficiency and decreases the cost of the converter. The converter stress profile is also good as the stress across switch and diodes is one-third of the output voltage. The efficiency of the converter is found to improve if the input voltage is increased. The maximum efficiency is found to be 95.4%. The experimental results show that the converter is working in continuous current mode and the results match with the theoretical analysis. The proposed converter belongs to the non-isolated category and hence is suitable for medium power applications.