Reduced Switch Multilevel Inverter Topologies for Renewable Energy Sources

This article proposes two generalized multilevel inverter configurations that reduce the number of switching devices, isolated DC sources, and total standing voltage on power switches, making them suitable for renewable energy sources. The main topology is a multilevel inverter that handles two isolated DC sources with ten power switches to create 25 voltage levels. Based on the main proposed topology, two generalized multilevel inverters are introduced to provide flexibility in the design and to minimize the number of elements. The optimal topologies for both extensive multilevel inverters are derived from different design objectives such as minimizing the number of elements (gate drivers, DC sources), achieving a large number of levels, and minimizing the total standing voltage. The main advantages of the proposed topologies are a reduced number of elements compared to those required by other existing multilevel inverter topologies. The power loss analysis and standalone PV application of the proposed topologies are discussed. Experimental results are presented for the proposed topology to demonstrate its correct operation.


I. INTRODUCTION
The nominal power of energy generation and distribution systems has increased significantly in recent years. This has given rise to the need for increased power in high-power systems. Multilevel power inverters (MLIs) are a suitable topology for operating high-power systems since they overcome the limitation of the voltage rating of power switches [1], [2]. MLIs can share the input DC-link voltage between the power switches and decrease the standing voltage of power semiconductors more easily than their two-level inverter counterparts. The other advantage of MLIs is that they provide a large number of levels, which leads them to have a lower voltage distortion as well as lower dv/dt and a lower common-mode voltage [3], [4]. Therefore, MLIs can The associate editor coordinating the review of this manuscript and approving it for publication was Inam Nutkani . be applied in Renewable Energy Sources (RES), Variable Frequency Drives (VFD), Flexible Alternating Current Transmission System (FACTS) Devices, and Electrical Vehicles (EV) [5], [6].
Switched-diode based MLIs (SD-MLIs), switchedcapacitor based MLIs (SC-MLI), and DC source based MLIs (DCS-MLIs) are three well-known multilevel inverter configurations [7], [8]. Discrete diodes, rather than switches, are used in SD-MLIs to minimize the number of power switches in order to incorporate a simple modulation technique. These classes of MLIs are limited in their ability to handle low power factors due to the use of diodes [9], [10]. The second class is SC-MLIs; they use capacitors rather than DC sources, which reduces the number of independent DC sources. Although SC-MLIs considerably decrease the number of isolated DC sources, they require a complicated control method to regulate the capacitor voltages. Additionally, SC-MLI capacitors store a large amount of energy, which results in high power losses [11], [12].
DCS-MLIs have two advantages over other multilevel inverters: they require neither capacitors, which involve a special voltage control technique, nor discrete diodes, which allows them to operate at low power factors. On the other hand, the drawback of DCS-MLIs is that they require a large number of power electronic devices and isolated DC sources to supply their many levels. This weakness leads to these inverters having complex control techniques, low efficiency, and high costs [13], [14]. Recently, different multilevel inverter topologies that reduce the number of components, isolated DC sources and the total standing voltage and simplify the control technique have been reported in the literature [15]- [18].
An asymmetrical multilevel inverter configuration, which was developed for cascaded MLIs, has been reported in [15], [16]. The presented topology creates 17 voltage levels with four DC power supplies, eight bidirectional switches, and two unidirectional switches. The amount of DC power supplies is so high to produce a low voltage (17-level). Therefore, each DC source requires its own capacitor in industry applications, which causes power losses and reduces the inverter's efficiency.
The ST-Type multilevel inverter [17] is another cascaded MLI topology from the literature. This MLI handles four isolated DC sources by using 12 switches to generate 17 levels. This topology has the advantage of lowering the peak switch voltage, but its 12 switches increase the complexity of the control.
The MLI developed in [18] is a K-Type inverter with an advanced topology that is described in [17]. This topology generates 13 voltage levels using 14 power switches (with two additional unidirectional switches). Its aim was to overcome the number of DC sources, which use two capacitors instead of two DC sources. Despite the fact that the number of DC sources in the K-Type inverter has been reduced, the power switches still is so high that they decrease the system's efficiency and raise its cost. [19] introduces a compact MLI topology for achieving high voltage levels. This basic structure requires ten switches for four isolated DC sources to create 17 voltage levels. In addition, this structure's connections are cascaded to minimize the number of required elements. The major weakness of this topology is that it uses four DC sources to produce its 17 levels.
A generalized MLI structure that uses a reduced basic unit has been reported in [20]. The basic MLI unit only generates nine levels using ten unidirectional switches. The basic structure has been presented in two fashions, extended and cascaded. The generalized structures reduce the total standing voltage and the number of elements. switches and four independent DC sources. The benefit of this topology is that it reduces the blocking voltage value while its drawback is that it requires a high number of DC sources.
Two reduced MLI structures have been reported in [22], [23]. The first reduced MLI [22] is a 15-level MLI that uses ten power switches and three unequal DC sources. In [23], this reduced structure has been expanded to 25 voltage levels by including two additional IGBT and one more DC supply. Although the 25-level structure reduces the number of switches, the value of the total blocking voltage is still high. In addition, the number of DC sources is also high, and they cannot be replaced by capacitors.
The aforementioned 25-level structure from [23] uses two unequal DC supplies that are controlled by 14 power switches. This structure has only been investigated for cascaded connections and not for generalized arrangements. The authors presented a simple balancing control method for charging and discharging input capacitors while increasing the number of switching devices.
[24] introduces a cascaded MLI topology based on an extendable basic unit that can generate 11 levels with eight switches and three DC sources. The advantage of this topology is that it reduces the number of switches. However, when a high level is required, many DC sources are required, which in turn necessitates the use of capacitors and leads to increased power losses.
Another MLI topology that aims to reduce the voltage stress and the component count has been reported in [25]. Even though this is a topology that can reduce voltage stress to produce high voltage levels, it still requires many DC sources to reach high voltage levels.
In [26], an extendable basic unit for multilevel inverter topologies is developed; it increases the number of levels while decreasing voltage stress. The number of switches and DC power supplies is still high, and some switches still endure high voltage stress.
Regarding switched-capacitor MLIs, different 25-level topologies have recently been reported in [27]- [30]. [27] presents a modified 5-level T-type inverter that needs only one capacitor instead of the two required in a conventional topography. By cascading two of the basic inverters, a 25-level structure is created that reduces the number of DC sources and capacitors. The disadvantage of this topology is that it still requires more DC sources to generate more voltage levels since its basic topology is not extendable.
A multi-source switched capacitor MLI has been presented in [28] for PV systems. By using two DC sources and two capacitors, it can generate 25 levels. Although the number of capacitors is reduced in this topology, the number of switches is still high. Furthermore, it needs an H-bridge inverter that increases the total standing voltage.
A grid-connected SC-MLI has been presented in [29]; it uses two PUC inverters and generates 25 levels. The advantage of this topology is its low TSV and reduced number of components. However, to charge the capacitors, it needs a proper control strategy as well as sensors, which make it complex and costly to achieve high voltage levels. VOLUME 9, 2021 In [30], an extendable switched-capacitor MLI has been developed. The main topology is a 25-level switchedcapacitor MLI that uses two DC sources and two capacitors. This MLI can be extended to reach high voltage levels by connecting the switched capacitor unit or by using multiple DC sources. This topology has reduced the voltage stress significantly, but the number of switches required to generate high voltage levels is still high. In addition, when multiple switched-capacitor units are used to achieve high voltage levels, the number of capacitors increases significantly, resulting in low efficiency.
Therefore, based on what was discussed above, the main drawbacks of MLI structures are a large number of DC sources and semiconductor devices, and high blocking voltage values. The aim of this article is to propose a new MLI configuration based on a reduced modular module that involves a low number of semiconductor devices and DC sources, thus making the proposed topology suitable for high power renewable energy sources.
First, in Section II, a basic module is suggested that produces 25 voltage levels using ten switches and two asymmetric DC sources. Then, in Section III, two MLI topologies are developed according to the modular topology. The proposed cascaded connections of the developed MLIs along with their optimal topologies are studied in sections IV and V. Section V presents the comparison studies between the proposed topologies and other MLIs to demonstrate the performance of the proposal. The power losses and PV applications of the proposed MLIs are discussed in detail in Section VI. Finally, the 25-level modular topology is tested using the experimental results to ensure that the proposed MLI operates correctly.

II. PROPOSED BASIC MODULE
The architecture of the proposed basic module is displayed in Fig. 1(a). It is based on the concept of a T-type converter. The benefit of the T-Type converter is that it uses a power switch to connect its output to the upper and lower DC-link, and it also requires an isolated DC-link to charge the input capacitors.
Specifically, the basic module is designed based on two T-Type converters that can create different paths by crossing capacitors. The proposed topology produces the inherent positive and negative levels, and it eliminates the limitation of high voltage rating on power switches in topologies that would require an h-bridge converter to change the polarity.
The proposed topology consists of ten power switches and two DC-links (four capacitors). The power switches T 1 , T 2 , T 3 , and T 4 work in complementary mode to produce negative and positive levels.
The basic module based on choosing the magnitude of DC-links can operate with symmetric and asymmetric DC sources. If the quantity of all DC-links or capacitors is considered symmetric (V 1 = V 2 = 2V dc ), the proposed converter generates nine voltage levels. If the magnitudes of the chosen DC-links are asymmetric, the proposed basic topology produces different voltage levels with the same number of components. Hence, by selecting the quantities of V 2 as multiples of V 1 , the proposed basic topology can produce different voltage levels, which are given in Table 1.
Renewable energy sources such as photovoltaic panels, fuel cells, supercapacitors, etc., can be used to supply the DC-link voltage (V 1 , V 2 ).
In order to balance the input capacitor voltages in applications that have unregulated DC sources (such as photovoltaic systems), a typical DC-DC boost multilevel converter, as described in [31], is implemented and adjusted to the proposed topology. This circuit comprises one boost converter and three discrete diodes, as shown in Fig. 2(a). The input voltage (V in ) is boosted in (V Cb ), and, through on and off states of the switch (S), the boost capacitor (C b ) is paralleled with the capacitors (C 1 ) and (C 2 ), which are charged the value of the boost capacitor voltage. As a result, the capacitors' voltages are kept in balance during the variation of unregulated DC sources.
The proposed basic topology has various operating modes that are generated by the activation of the different switching devices. Fig. 1(b) shows its operation modes in the case of 25 levels (corresponding to Table 1). Table 2 gives the synthesis of the state of the switches that generate each level; the 32 switching states are shown by the on switches. As can be seen in Table 2, some levels produce redundancy.  Table 2.
An essential element is the maximum total standing voltage (TSV) to reduce the cost of multilevel converters. If this factor is low, the converter's final price will be reduced. This factor also determines the type and rating of power electronics  devices (IGBTs, diodes). Thus, the maximum TSV of each power switch, in the proposed basic topology, is as follows: In the proposed basic topology, the total standing voltage (TSV basic ) on power switches is the sum of the maximum voltage across each switch. Therefore, for the proposed basic topology, the TSV basic value is:

III. PROPOSED MLI TOPOLOGIES
In this section, the proposed basic module is extended in two different ways. Two different MLI topologies are presented, and the relations between the number of elements, the number of voltage levels, and the maximum blocking voltage on the switches are calculated.

A. FIRST PROPOSED MLI
The first proposed MLI is illustrated in Fig. 2. In this topology, as in the basic topology, the magnitude of all DC voltages in part-a (V 1a , V 2a , . . . , V na ) are the same, and similarly, the magnitude of all DC voltages in part-b (V 1b , V 2b , . . . , V nb ) are the same. Hence, the magnitudes of the DC voltage sources are considered as follows: In the first proposed MLI, the number of components (number of DC sources (N DC ), number of drivers (N IGBT ), number of IGBTs (N Driver ) and the number of levels (N L,F )) are obtained as follows: N Driver = 2N cell + 6 (10) Here, N cell,a andN cell,b are the number of cells in part-a and part-b, respectively, and N cell is the sum of N cell,a + N cell,b .
In the first proposed MLI (Fig. 2), the maximum standing voltage (MSV) value of the switches is related to the switch locations. The MSV is the maximum stress voltage that a switch can withstand. As a criterion, the MSV value in the first proposed MLI MSV F−MLI is defined as the sum of the stress voltage of the switches. To calculate the MSV F−MLI value, the first proposed MLI is divided into three parts. The first part comprises the power switches of part-a of the converter S 1,1a , S 2,1a , S 3,1a , · · · , S 3,na , the second part comprises the switches of part-b of the converter S 1,1b , S 2,1b , S 3,1b , · · · , S 3,nb , and the third part is made up of the four fixed power switches T 1 , T 2 , T 3 , andT 4 .
The MSV F,a is the MSV value of the power switches of part-a of the converter S 1,1a , S 2,1a , · · · , S 3,na . They are calculated as follows: Similarly, the MSV F,b is the MSV value for the power switches of part-b. It is obtained as follows: MSV F,T is the maximum standing voltage of the four power switches of T 1 , T 2 , T 3 , andT 4 , which can be written as follows: Since N cell = N cell,a +N cell,b and N cell,a = N cell,b , Eq. (13) and Eq. (15) can be rewritten as follows: Similarly, Eq. (16) can be rewritten as follows: By referring to Eq. (16) and Eq. (17), the MSV value of the first proposed MLI for N cell = 2, 4, 6, · · · , can be obtained as follows:

B. SECOND PROPOSED MLI
The configuration of the second proposed MLI is illustrated in Fig. 3. In this topology, the magnitudes of the two DC voltage sources in each cell are the same, and they are different from those of other cells. Thus, the value of the DC voltage sources in each cell for part-a can be calculated as follows: And for part-b the values are as follows: In the second proposed MLI, the number of IGBTs and DC sources are the same as in the first proposed MLI (Eq. (8) and Eq. (9)), and the quantities of drivers (N Driver,S ) and levels (N L,S ) are obtained as follows: The maximum standing voltage of the switches in the second proposed MLI MSV S−MLI (Fig. 3) is calculated similarly to the method presented for the first MLI. Hence, this configuration is divided into three parts. The first part contains the power switches of part-a, the second part contains the power switches of part-b, and the third part contains four fixed power switches T 1 , · · · , T 4 . The MSV S,a is the sum of the standing voltage on the power switches in each cell of part-a of the converter MSV cell−1a , MSV cell−2a , · · · , MSV cell−na . They are calculated as follows: For cell-1a: For cell-2a: For cell-na: Therefore, MSV S,a is obtained as follows: By substituting Eq. (20) into Eq. (26), (26) can be rewritten as follows: Here, N cell,a is the total number of cells in part-a. Similarly, by considering Eq. (26) and Eq. (20), the value of MSV S,b for part-b is obtained: Here, N cell,b is the total number of cells in part-b. MSV S,T is the maximum standing voltage of the four power switches of T 1 , · · · , T 4 , which can be expressed as follows: Meanwhile, N cell = N cell,a + N cell,b and N cell,a = N cell,b , Eq. (26) and Eq. (27), can be written as follows: Also, Eq. (28) can be written as follows: According to the Eqs. (29)-(30), the MSV value for the second proposed MLI for N cell = 2, 4, 6, · · · , can be obtained as follows:

IV. PROPOSED CASCADED CONNECTION
Two cascaded configurations are submitted based on the cascaded connection of the proposed MLIs to minimize the number of elements. Fig. 4 indicates the cascaded connection of the proposed multilevel inverters with a quantity k of the proposed basic modules. Since the maximum output voltage in the output of the proposed cascaded topology is the sum of the output voltage of each basic module, the output voltage of the proposed cascaded topology can be expressed as follows:

A. FIRST PROPOSED CASCADED TOPOLOGY
The aim of the first proposed cascaded topology is to maximize the number of voltage levels. In this configuration, the magnitudes of the DC voltage sources are arranged as follows: For the first MLI: For the second MLI:  For the K th MLI: Therefore, the number of levels for the first proposed cascaded topology N L,F,cas is obtained as follows: Here, N cell,i is the total number of cells in the ith unit of the proposed cascaded topology.
As per Eq. (30), the total standing voltage of the power switches TSV F,cas in the first proposed cascaded topology can be calculated as follows: The aim of the second proposed cascaded topology is to minimize the number of levels. The magnitudes of the DC voltage sources in this configuration can be considered as follows: For the first MLI: For the second MLI: For the K th MLI: Therefore, the number of levels for the second proposed cascaded topology N L,S,cas is obtained as follows: Here, N cell,i is the total number of cells in the ith unit of the proposed cascaded topology.
As per Eq. (32), the total standing voltage of the power switches, TSV S,cas , for the second proposed cascaded topology can be calculated as follows:

V. OPTIMAL TOPOLOGIES
The objective of extracting an optimal topology in the proposed cascaded topologies is either to maximize the number of output voltage levels with a fixed number of components or to minimize the number of elements required to generate a specific level. Therefore, there are two main factors to keep in mind when designing the optimal topology: the number of cells in each proposed MLI, N cell , and the amount of series in each proposed MLI, k. Both factors impact the maximum magnitude of the output voltage. We consider the N cell variable to obtain optimal topologies and k for the peak of the output voltage.
In the proposed cascaded MLIs, the number of levels is maximized when the number of cells is equal in each proposed MLI. That is:  Therefore, the number of components of the first proposed cascaded topology, shown in Table 3, can be expressed as follows: And, considering Eq. (40) and Eq. (41), the number of levels and the TSV value can be expressed as follows: For the second proposed cascaded topology, the number of IGBTs and DC sources is given by Eq. (51) and Eq. (52), respectively. As per Table 3, the number of drivers can be expressed as follows: Taking Eq. (47) and Eq. (48) into consideration, the number of levels and the TSV value for the second proposed cascaded MLI can be expressed as follows: There are two scenarios that achieve optimality for the two proposed cascaded topologies. The purpose of the first scenario is to produce the maximum number of levels at the output with a constant number of components (drivers, IGBTs, DC source) and a fixed TSV value.
The purpose of the second scenario is to minimize the number of components and the TSV value for a fixed number of output voltage levels.
The results of these two scenarios for both proposed cascaded MLIs are given in Table 4. All the equations given in Table 4 are obtained from Eqs. (50)-(57) for both proposed cascaded topologies. As Table 4 shows, in the first scenario, the number of levels is calculated based on a fixed number of components and the TSV value.
Using the first cascaded topology in this scenario, the indexes A1, B1, C1, and D1 should be maximized to produce the maximum number of levels. Hence, these indexes are plotted against N cell , as shown in Fig. 6(a). This figure shows that the number of cells is equal to two because the equations of the second proposed MLI are obtained for an even number of cells. As Fig. 5(a) shows, indexes B1, C1, and D1 are maximized at N cell = 2, and index A1 is maximized at N cell = 2.5. Because N c ell should be an integer, the closest integer number must be chosen if an integer number is not obtained. Therefore, N cell = 2 is chosen for index A1.
The first scenario is performed using the second proposed topology as well. The results are shown in Table 4. As shown in Fig. 6(b), the indexes of A2 and B2 are maximized when N cell = 2.5 and 2.7, respectively. As previously mentioned, the number of cells should be an even integer, so N cell = 2 is chosen for indexes A2 and B2. Indexes C2 and D2 are maximized at N cell = 2.
The second scenario is performed for both proposed cascaded MLIs to minimize the number of components and the TSV value for a fixed number of levels. Table 4 and Fig. 6(c) show that, for the first proposed cascaded MLI, the number of cells for the three indexes F1, G1, and H1 is maximized when N cell = 2 while index E1 is maximized when N cell = 2.5. E1 should be an integer number, so we chose 2.0. Similarly, the second scenario is run using the second proposed cascaded MLI. Based on Table 4 and Fig. 6(d) for this configuration, indexes G2 and H2 are maximized when N cell = 2. Indexes E2 and F2 are maximized when N cell = 3.2 and 2.6, respectively; since they must be an even integer, we have chosen 2.0.
To conclude, as discussed above, the number of cells N cell in each unit of the proposed MLIs should be two cells for both proposed cascaded configurations in both scenarios. This means that the optimal topologies consist of ten switches, 12 IGBTs, and four DC sources, as indicated by Eqs. (51)-(53).

VI. COMPARISON STUDIES
To demonstrate the advantages and drawbacks of the proposed cascaded MLI topologies, a comprehensive comparison is drawn between the proposed MLI topology and other cascaded MLI topologies. The comparative study considers the number of power switches, DC voltage sources, maximum on-state switches, peak switch voltage, and magnitude of TSV to validate the capabilities of the proposed topology as compared to other existing topologies [17]- [30].
Power switches are the most important component of multilevel inverters since they define the reliability and affect the level of sophistication of the control. The number of switches facing the number of voltage levels is exhibited in Fig. 7(a) for all discussed MLIs and proposed cascaded topologies. Fig. 6(a) confirms that, in both symmetric and asymmetric modes (proposals I and II, respectively), the proposed cascaded topology requires significantly fewer switches to produce the highest number of levels than those required in other MLIs (e.g., R26 and R27, which both use asymmetric configurations). This capability is valued as a specific merit for the proposed cascaded topologies because the control of this topology will be easier to control than other MLIs.
The numbers of DC voltage sources required to generate different voltage levels are compared in Fig. 7(b) for all MLI topologies. Here, it is clear that, in both symmetric and asymmetric modes (proposals I and II, respectively), the proposed cascaded MLIs require fewer DC sources; this is another strength of the proposed topologies. It should be noted that although [30] (R26) uses only two DC voltage sources to generate high voltage levels, it utilizes a high number of capacitors. Fig. 7(c) compares the number of capacitors to the number of voltage levels, and it is clear that the proposed topology uses fewer capacitors than those required by other MLIs. The exception is [30], which needs only two capacitors but uses multiple DC sources. Fig. 7(d) compares the maximum on-state switches to the number of levels. This factor impacts the power lost by MLIs. In the proposed topology, it is reduced in both modes of operation since the proposed topology requires fewer switches.
The peak switch voltage (PSV) comparison is exhibited in Fig. 7(e). This figure shows that the proposed topology performs well in terms of peak switch voltage in the symmetric DC source. It has a lower PSV than that of other recent MLIs, and in the asymmetric DC source category, it ranks after trinary CHB and [19]- [21], [25].

VII. POWER LOSSES
The power losses of semiconductor devices are divided into two types: conduction and switching losses [9], [13]. In power electronics devices, conduction losses appear while the semiconductor devices are in on-state mode. The type of switch used is an IGBT with a unit-parallel diode that can be expanded for MLIs. In instantaneous conduction, the power losses of a power switch are identical to: Here, V IGBT , V diode , R IGBT , and R diode are the threshold IGBT voltage, the diode voltage, the IGBT resistance, and the diode resistance, respectively, and β is a constant.
The proposed MLIs have low conduction losses because they use fewer on-state switches than other MLIs, as shown in Fig. 7(c).
Switching losses are defined as power that is wasted while the power is being turned off or turned on. This loss is calculated for the switch and the anti-parallel diode, which is highly correlated with the switching frequency (f s ), and the standing voltage of the switches. The switching frequency is dependent on modulation techniques, and the standing voltage depends on the converter circuit. The switching losses of anti-parallel diodes are generally neglected due to the fast conducting of diodes. The switching losses (P ON , P OFF ) for N number of IGBTs can be obtained as follows: Here, V stand,j , I , t ON , and t OFF are the voltage of IGBT in either off-state or on-state, the flowing current of the IGBT, and the on-state and off-state of the IGBT, respectively. The switching losses (P SW ) are equal to the sum of the energy lost during turn-on and turn-off in a fundamental cycle of the output voltage; this is computed as follows: where f is the fundamental frequency, and N ON ,k and N OFF,k are the number times the switch n is turned on and off during a period. P ON ,ki and P OFF,ki are the power loss of the switch n during the i th instance that it is turned on or off, respectively. Then, considering the relationships expressed in (59) and (62), the total losses of the proposed MLIs are as follows: Therefore, the efficiency of proposed topology can be obtained as: Since the proposed topology requires a balancing circuit (two boost converters), its actual efficiency, considering the efficiency of the boost converter, can be obtained as follows: By referring to [31], η Boost can be computed as: where V C is the capacitor voltage of the boost converter.  8(c) show the power losses and temperature of each switch separately. The initial temperature is 25[ • C]. The maximum power loss is for switch T 2 , which naturally has a higher temperature. Then, the switch (S 1 , S 3 ) has experienced a greater power loss. It is worth noting that each switch (S 3 , S 4 ) consists of two IGBTs, so each IGBT of S 3 has approximately half of the shown power loss value. The total VOLUME 9, 2021

loss of the proposed 25-level inverter is 114[W]
, and it has an efficiency of 97.72% for 5[kW] output power, as shown in Fig. 8(d).

VIII. STANDALONE PV APPLICATION OF THE PROPOSED MULTILEVEL INVERTERS
One potential application of the proposed topologies is in standalone PV systems. In standalone PV systems, the critical challenge is to deliver high-quality power to the load using a highly efficient MLI [32]. The suggested topologies can enhance power quality by producing a large number of voltage levels that create a sin wave current waveform with low THD. In addition, they can increase efficiency since they use a smaller number of power semiconductor elements.

A. MODULATION TECHNIQUE
Pulse width modulation (PWM), fundamental frequency switching method, and staircase modulation are the most common modulation techniques used to commutate multilevel inverters. This article applies the staircase modulation approach to the proposed inverters [10]. The staircase modulation method utilizes a sinusoidal stepped waveform, as shown in Fig. 9. In this technique, the switching angles for 0 < αj < π/2 are computed by considering the total number of required levels (N L ) for the proposed inverters as: Then, the switching angles generate the switching pulses of the proposed multilevel inverter; these pulses are determined individually based on the switching states in Table 2. The step timing is chosen based on the output frequency, and it is calculated offline.

B. STANDALONE PV APPLICATION
The control strategy for the proposed 25-level inverter in standalone PV systems is shown in Fig. 10. Two PV panels are used as DC-link voltage with two distinct powers, and high-power efficiency is achieved using two separate boost converters. The boost converters are single-input multi-output DC-DC converters, as reported in [31], and they are configured for the proposed inverter as detailed in Fig. 10.
The capacitors' voltages can be controlled by the duty cycles of two of the boost converters' switches (S b1 , S b2 ). As a result, the magnitudes of the DC-link voltages (V 1 , V 2 ) can be expressed in terms of PV panel voltages and duty cycles, as follows: The DC-link voltage can be set to an appropriate magnitude by adjusting the power of the PV panels and the duty cycle of the boost converter switches. The Maximum Power Point (MPP) is derived by monitoring the voltage and current of the PV panels and using a proper MPPT algorithm. The duty cycles are then compared with the PWM signals to generate the switching pulses for the boost converters' switches.
The load voltage must be regulated by the proposed inverter to deliver power to the load at a constant nominal voltage. The capacitor voltages should therefore be adjusted to their reference values to maintain a constant voltage at the inverter's output. As a result, the capacitor voltages are balanced and set to their references using separate PI controllers. For the voltage drop on the filter and series impedance, an extra PI controller is coupled with the proposed voltage control system. The proper modulation index is obtained from the output of this PI controller, and the switching pulses of the proposed inverter are generated using the suggested FFM approach (see Fig. 9). The following well-known formula is used to compute the size of the inverter's capacitors: The load peak current, the ripple voltage of the capacitor, and the switching frequency of the voltage of the system are represented as I L,peak , V C , and f s , respectively.

IX. EXPERIMENTAL VALIDATION
In this section, to validate the performance of the proposal, the experimental results for the proposed 25-level topology are presented. The prototype of the proposed 25-level MLI is built using IGBTs as the switching devices. The experimental set-up diagram of the proposed 25-level MLI is shown in Fig. 11. The two circuits used to regulate the voltage of input capacitors of MLIs, such as the proposed topology, have been presented in [31]. Because the set-up of the proposed topology uses two regulated DC sources as the input DC-link, we implemented the circuit presented in [31]. The proposed control modulation technique (described in Section VIII) is applied to generate the switching pulses of the inverter. Table 6 lists the components used in the experimental set-up.
The field-programmable gate array (FPGA) is used in this study to generate pulses for the power switches. In Xiling software, the Verilog-language programs all the switching states of the proposed topology. Then, the switching states transfer to Basys 2 hardware. Eventually, the switching pulses are transferred to the gate driver circuits by optic-wires to fire the IGBTs of the proposed topology. Moreover, typical dynamic tests for MLIs connected to an R-L load consist of an unexpected load change, modulation   Fig. 12(f) shows that the proposed 25-level MLI responds well to a sudden load change and that it can handle the load current without any change in the magnitude of the load or the phase voltage. Fig. 12(g) shows the capacitor voltages during a step change in the load. As can be seen, the capacitor voltages stay balanced in the input DC source magnitudes during this change.
The tests are then performed for the modulation and frequency changes. Fig. 12(h) shows the modulation index change, which decreased from unity to 0.7 at 5[ms]. As can be seen in this figure, the experimental results are like the simulation results in that the voltage levels decreased from 25 levels to 17 levels and the magnitude of the load current is reduced due to the decrease in the output voltage magnitude.  The stress voltage distribution of the power switches of the proposed topology in the maximum total blocking voltage is shown in Fig. 11(a). This chart shows that none of the power switches used withstand the peak output voltage, which is (12×V dc ).
The experimental results of the standing voltage for all the used power switches of the proposed 25-level MLI are displayed in Figs. 13(b) to 13(d). Fig. 13(b) displays the standing voltage of the unidirectional power switches of part-a of the proposed basic module. These switches endure a low voltage magnitude of 20 [V]. The standing voltage of the power switches of part-b is shown in Fig. 13(c). These switches endure a high voltage source magnitude of 100 [V]. The standing voltage of the two bidirectional power switches, S 3 and S 4 , is indicated in Fig. 13(d). The absolute voltage magnitude that these power switches support is 5[V] and 50 [V].
The efficiency of the proposed 25-level multilevel inverter is obtained for different inverter loads. The output power is calculated by measuring the RMS value of the output voltage and current, and the input power is calculated by measuring the average value of the two DC source currents.
The efficiency from both the simulation and experimental results is depicted in Fig. 14

X. CONCLUSION
In this article, we have proposed a basic module for multilevel inverters with a reduced quantity of power electronics components for renewable energy source applications. The proposed basic module can produce 25 voltage levels by handling two unequal DC sources with ten power switches. To achieve a large number of voltage levels, the basic module was extended to two different methods, and their cascaded topologies were developed. Optimal topologies were defined based on different criteria to prove the flexibility and reliability of the proposed MLIs. We have obtained comprehensive results by comparing the proposal with other MLIs; these comparisons show that the proposed topologies required a small number of power electronics devices (switches, IGBTs, drivers, diodes) and isolated DC voltage sources. Furthermore, we have demonstrated that the proposed MLI topologies have a lower total standing voltage value than recently presented MLIs in both operation modes: symmetric and asymmetric DC sources. Finally, the experimental results were presented to verify the correct operation of the proposal. He received a scholarship from the Chilean National Research, Science and Technology Committee, in 2018. He is the author or coauthor of more than 30 published technical articles. He also holds a patent in the area of power electronics converters. His research interests include design, modeling, and control of multilevel power converters and their applications as well as advanced model predictive control of power electronic systems in e-mobility applications.
Mr. Hosseinzadeh received the Best Thesis Award from the Islamic Azad University of Tabriz EBRAHIM BABAEI (Senior Member, IEEE) received the Ph.D. degree in electrical engineering from the University of Tabriz, in 2007. He is the author or coauthor of one book and more than 550 journal articles and conference papers. He also holds 25 patents in the area of power electronics. His research interests include the analysis, modeling, design, and control of power electronics converters and their applications, renewable energy sources, and FACTS devices. He has been the technical program chair, track chair, organizer of different special sessions, and technical program committee member in the most important international conferences organized in the field of power electronics. Several times, he was a recipient of the Best Researcher Award from the University of Tabriz. He also received the 2016 Outstanding Reviewer Award from IEEE TRANSACTIONS ON  Since 1977, he has been with the Department of Electronics Engineering, Universidad Tecnica Federico Santa Maria, where he was a Full Professor and the President. Since 2015, he has been the President of the Universidad Andres Bello in Santiago, Chile, where he has also been a Full Professor, since 2019. He has coauthored two books, several book chapters, and more than 400 journal articles and conference papers. His research interests include multilevel inverters, new converter topologies, control of power converters, and adjustable-speed drives. He is a member of the Chilean Academy of Engineering. He has received a number of best paper awards from various IEEE journals. He was a recipient of the National Award of Applied Sciences and Technology from the Government of Chile, in 2014, and the Eugene Mittelmann Award from the IEEE Industrial Electronics Society, in 2015. From 2014 to 2019, he was included in the list of Highly Cited Researchers published by Web of Science.