Output Capacitance Minimization for Converters in DC Microgrids via Multi-Objective Tuning of Droop-Based Controllers

This paper proposes a controller tuning methodology for voltage-current droop-based DC-DC converters in DC microgrids to reduce the output capacitance. This minimization is cost saving and implies lower fault currents. However, it leads to higher DC voltage variability during load transients, which requires an output impedance shaping by control means to reduce over or undershoot. The proposed control structure and problem definition simultaneously takes into account that the solution must achieve the impedance shaping, performance and stand-alone stability objectives. This comprises a multi-objective problem which is effectively formulated here and, then, solved by a non-smooth $\mathcal {H}_\infty $ optimization technique that tunes all free parameters. For comparison purposes, this tuning methodology is applied to several droop proposals, and the proposed droop is able to reduce the output capacitance of bidirectional buck-type and boost-type half-bridge converters by 37.5% and 23.08%, respectively, with respect to previous proposals. The designs are validated in time and frequency domains by means of theoretical analysis and experimental results on DC microgrid prototypes with bidirectional buck-type or boost-type half-bridge converters.


I. INTRODUCTION
The development of power electronic converters for Distributed Energy Resources (DERs) has led to the evolution of microgrids, which are the association of DERs with local customers loads. Most microgrids have adopted AC distribution as consequence of conventional power systems. However, DC microgrids have some advantages when facing DC output sources, such as photovoltaic or energy storage elements [1]. The connection of energy storage elements or interlinking between DC buses [2] is accomplished by DC-DC bidirectional topologies, such as the half-bridge converter (or The associate editor coordinating the review of this manuscript and approving it for publication was Zhuang Xu . bidirectional buck-boost converter) [3], which is the simplest topology to fulfill the requirements. In order to ensure stable and well-performing control of microgrids, these converters usually regulate the DC bus voltage with droop strategies [4], [5].
Droop control is a decentralized control strategy that allows an automatic load distribution among parallel sources by varying the DC bus voltage within a predefined range. Both voltage-current (V-I) and current-voltage (I-V) droops strategies share the same steady-state behavior with loads, but their dynamic performances are different [6], [7]. The V-I droop method is preferable for parallel operation because the converter behaves like a voltage source following a reference, given by the secondary control, with an output impedance characterized by the controller capabilities and output capacitance. Then, the DC bus voltage is restored to its nominal value, and power sharing is guaranteed regardless of cable impedance [8], [9]. For reliable DC bus voltage, the total DC bus impedance [10] may be characterized by each converter output impedance to avoid excessive voltage sags or surges during transients.
By increasing the output capacitance, the DC microgrid inertia increases, and the system voltage variations during load changes are negligible. However, it increases the weight, size, and cost of power converters, which are determinant in some applications like, for example, aircrafts [11]. Besides, large bus capacitance leads to more energy stored on the bus. In case of a DC bus short-circuit fault, it would induce a high fault current in magnitude and duration. This makes fault isolation difficult [12].
As long as the voltage is within the admissible range during any transient, the bus capacitance could be reduced. One of the first approaches, involving low output capacitance, constrained the load rate of change to fulfill the bus voltage objective [13], and described these systems as voltage weak DC microgrids [14]. However, such proposal is impractical considering the unknown behavior of loads. Then, it is more convenient to shape the output impedance by control means.
Previous control solutions looked for diminishing the output impedance magnitude in certain frequencies by means of additional output voltage feedback loops [15] or frequency-dependent droop loops [16]- [20]. This last technique is the Virtual-Capacitor (VC) control, which is also known as integral droop control or virtual inertia control. In droop-controlled converters, the desired output impedance should have a resistive-capacitive behavior because the output voltage variations related to load step changes need to be damped. Following this idea and output capacitance minimization, reference [21] and its extension [22] give a design guideline. However, both lack a systematic problem formulation that encompasses the whole controller tuning to reach the minimum capacitance for that specific power electronic converter. Besides, the controller design faces a trade-off between performance objectives and output impedance shaping. This multi-objective approach requires controller synthesis methodologies that can cope with it.
When looking for optimal controller designs, the design preference is always convex formulations because they ensure a global optimum solution for the specified problem. For instance, Linear Matrix Inequalities (LMIs) for each specification [23], [24] or, if all of them are gain constraints, a mixed-sensitivity H ∞ design approach [25]. However, an actual multi-objective control problem following convex formulations has some difficulties as conservatism [24] and high-order structures. Besides, industrial applications are more keen to fixed-structure control system like proportional-integral (PI) loops that facilitate implementation, validation, and re-tuning. Then, non-smooth optimization techniques [26] are a very convenient option to find feasible solutions for multi-objective fixed-structure controller tuning [27], [28].
Our contributions in terms of droop-based controller design procedure are: 1) it is performed in a single-step, minimizing iterations over current and voltage loops because they are jointly designed; 2) it synthesizes low-order industrysuitable fixed-structure controllers; 3) it minimizes output capacitance; and 4) it guarantees the converter output voltage within the DC bus nominal range. The methodology is applied to control a bidirectional half-bridge converter operating as buck and boost, where the desired behavior depends on the application. For instance, Figure 1.(a) depicts a DC microgrid, where an interlinking half-bridge converter regulates the low DC voltage bus (buck-type), whereas another half-bridge converter interfacing an energy storage element regulates the high DC voltage bus (boost-type). Section II introduces the proposal and underlying control objectives. Section III describes the theoretical limit for output impedance shaping. Section IV presents the controller tuning methodology. The experimental results for DC microgrids are given in Section V.

II. PROPOSAL DESCRIPTION
Detailed descriptions of bidirectional half-bridge converters operating as buck and boost are depicted in Figure 1.(a) and the corresponding controller for both in Figure 1.(b). VOLUME 8, 2020 The selected DC-DC converter topology is bidirectional, so that the mode of operation is always continuous current mode (CCM) because there is path for the inductor current on every possible switching state.

A. CONTROL OBJECTIVES
The ideal droop-controlled converter should behave as a voltage source with an output impedance, Z o (s), which is the parallel of the droop resistance, r d , and output capacitance, C o . Then, an output current, i o , step leads to a smooth change of output voltage, v o , because Z o (s) behaves as a first-order system. Simple control solutions imply undesired dynamics or additional capacitance leads to unnecessary oversizing. Alternatively, this proposal looks for output capacitance minimization and Z o (s) shaping by control means while keeping acceptable performances.
The most practical controller scheme for droop-based converters, see where v r o is the output voltage reference, Z d (s) is the generalized frequency-dependent droop impedance to vary the output voltage depending on the load, and v r b is the DC bus voltage set point. This proposal will also use i L instead of i o at equation (1) because it is very convenient for Z o (s) shaping in buck-type converters.
Summarizing, this proposal aims to minimize C o , while achieving the following control objectives by tuning only the parameters of G i (s), G v (s) and Z d (s): 1) Output impedance with resistive-capacitive behavior in order to reduce bus voltage sags and surges. 2) Good stand-alone robustness.
3) Damped tracking of v r o .

B. MULTI-OBJECTIVE CONTROLLER DESIGN
The control proposal will be approached within the framework of the generalized control problem shown in Figure 2 [29]. The generalized plant, P(s), is a dynamic multiple-input multiple-output (MIMO) model composed of: the system to be controlled; and interconnected weighting functions that serve as a vehicle to translate design(er) control objectives into a design problem. Variable u (controller actuation vector) and y (measured output vector available for control) define the input-output structure of the controller. The relationship between w (disturbance input vector, including references) and z (error output vector desired to be kept small, specially on certain frequencies) defines the performance objectives. The synthesized controller, K (s), complies with the specifications or constraints which are imposed over each channel of w and z, that is w j → z j , by using frequency-dependent proper weighting functions identified by W (s) and proper subscripts.
The proposed K has a predefined fixed-structure, see Figure 1.(b), and it is composed of tunable real-valued parameters. Then, any convex formulation [23]- [25] to synthesize K is not a possibility. The selected option is a non-smooth optimization technique using a first-order descent method explained in [26]. This computational tool is able to evaluate and enforce H ∞ (peak gain), H 2 (average gain) as well as other frequency-based objectives for controller tuning [28]. This tool is fully implemented in systune and hinfstruct [27], [30].
Considering that a good gain objective achievement would be z j w −1 j ∞ ≤ 1, our goals are translated as: 1) The control objectives 2) and 3) are defined between reference, w 1 = v r b , and voltage error, In order to ensure zero steady-state error in the inner current controller, an additional channel is projected between w 1 = v r b , and current error, where i r L is the inductor current reference. Besides, these objectives need an actuation constraint between reference, w 2 = v r b , and duty cycle, 2) The control objective 1) is defined over output current, w 3 = i o , and output voltage, The selection of what channels should be soft, function to be minimized, or hard, design constraints, requirements is up to the designer decision for a well-defined optimization problem. Taking into account the non-smooth H ∞ optimization framework, the local solution is a locally optimal controller in the set of hard requirements feasible controllers. Then, we must carefully select the constraints.

III. OUTPUT IMPEDANCE SHAPING BY THE DROOP LOOP
This section generalizes the output impedance shaping analysis for a general linearized DC-DC converter. Then, considering the shaping capabilities of the controller, a minimum capacitance value is derived. Additionally, the analysis allow us to define a droop impedance transfer function for achieving the required output impedance shaping. The diacritic markˆindicates small-signal, and it will be removed in the following for the sake of clarity.
Following Figure 3, the current open-loop and closed-loop tracking transfer functions respectively are where the zero-order-hold (ZOH) with sampling period T s and the overall time delay T d are given by For controller synthesis purposes, a first-order Padé approximation is enough for the exponential expressions of G dl (s).
The selection of i L as input for Z d implies that the Taking into account that the open-loop output impedance can be expressed as the closed-loop output impedance using i L or i o for droop, respectively, are where S i (s) = 1 − T i (s) and S v (s) = 1 − T v (s) are the sensitivity transfer functions for the current and voltage loops, respectively. Let us define the voltage closed-loop bandwidth, ω Bv , as the frequency where |S v (jω)| = 1/ √ 2 first crosses from below. Besides, the bandwidth in terms of T v , ω BTv , is the highest frequency at which |T v (jω)| = 1/ √ 2 from above. Then, up to ω Bv , control is still effective improving the performance and allowing output impedance shaping. From ω Bv to ω BTv , control still affects response, but it degrades. Finally, at frequencies higher than ω BTv control has no significant effect on the response [29]. The gain crossover frequency, ω cv = 2πf cv , defined as the frequency where |L v (jω)| first crosses from above, usually lies between ω Bv and ω BTv . Although T v depends on Z d in expression (9), the closed-loop behavior is mainly commanded by G v . Moreover, the effect of Z d on the denominator of T v , see expression (7) by using (5), could be neglected because, usually, |G vi (jω)| |Z d (jω)| at low and medium frequencies for buck-type converters. Consequently, the second addend of expressions (9) and (10) show that T v lets Z d to shape the low frequency behavior of Z o in both cases. The medium and high frequency are determined by the first addend of expressions (9) and (10) because it is multiplied by S v . Then, the actual output impedance shaping control limit is set to ω Bv , and the controller should be able to shape the output impedance as a resistance, r d , up to that frequency.
Considering the previous analysis and the parallel of r d and C o as ideal Z o , the theoretical minimum output capacitance is derived from this first-order system pole as The maximum attainable bandwidth, ω Bv , may be limited by the time delay as well as the magnitude of the non-minimum phase zero of the system on the real axis in the right-half s-plane (real RHP-zero) [29], [31]. Usually, ω Bv < 1/T d for the former and ω Bv < z s /2 for the latter, where z s is the location of the real RHP-zero. Therefore, we will push the controller design up to these limits to reach the minimum capacitance. This minimum value is higher than the one required by the desired output voltage ripple and maximum output current of the application [32], [33].

B. DROOP IMPEDANCE PROPOSAL
The current and voltage controller structures have been defined, thus we must select a structure for Z d . Considering Z o (s) = r d on expressions (9) and (10), the droop impedance using i L or i o should be, respectively: Within ω < ω Bv , T v and T i can be approximately considered as a unit gain, which respectively leads expressions (12) and (13) to: Then, Z d depends on r d , the voltage controller and converter topology via G vi and G vi o [22]. It is deduced from (14) that not all DC-DC converters can use i L measurement for droop because expression G vi /G vi o may depend on the operating point. This paper analyzes both cases: i L for droop on buck-type converters; i o for droop on boost-type converters.
Expressions (14) and (15) demonstrate that a frequencydependent droop is required to achieve the desired performance, so that we are going to generalized the droop impedance, Z d (s), as where d 0 defines the location of the pole, D z1 sets a zero and D z2 adds a theoretical derivative term. They are tunable parameters and L is the power filter inductance. The inductor voltage, v L , is an indirect measurement to improve the output impedance shaping capabilities when i L is used for droop because of its derivative behavior to counteract the gain falling of T v in (9). In our case of study for buck-type, such derivative is indirectly defined by s If the operating conditions require a different r d , the control system can change its value according to (16). Although it will change the dynamic behavior of Z o , the system stability is ensured without changing the designed control parameters. Controller and capacitance are going to be tuned for a given operating point, so that lower r d will lead to higher over or undershoot, whereas higher r d will lead to totally damped voltage transients.

IV. CONTROLLER DESIGN BY MULTI-OBJECTIVE OPTIMIZATION
The proposed multi-objective controller design is applied to buck-type and boost-type converters. Here, we introduce both linearized models and constraints over the droop impedance proposal for each case as well as the optimization problem formulation to tune the controllers.

A. CASES UNDER STUDY
The linearized state-space model of buck-type half-bridge converter, G(s), see Figure 1.(a), is given as follows [34]: where V in is considered constant. The cases under study for buck-type converter use i L as input on (16) and the following constraints: 1) TR-BK: Traditional approach where Z d (s) = r d .
2) C1-BK: Reference case where the tunable variables are constrained, according to [22] and (14), as the value of other tunable parameters, that is d 0 = k iv /k pv , D z1 = r d − 1/k pv and D z2 = 0. 3) C2-BK: Proposed case for additional C o minimization capabilities where d 0 , D z1 and D z2 are independently tunable.
The linearized state-space model of boost-type half-bridge converter, G(s), see Figure 1.(a), is given as follows [34]: where V op is the static output voltage, I lp is the static inductor current, and D p is the static duty cycle. In steady state, , being R load the equivalent resistive load, and I op = V op /R load . We will consider the full load model for controller analysis because the dynamics does not change a lot with respect half or null load [22]. The cases under study for boost-type converter use i o as input on (16) and the following constraints: 1) TR-BT: Traditional approach where Z d (s) = r d .
2) C1-BT: Modified proposed case inspired by [22] where d 0 is independently tunable and D z1 = 0 and D z2 = 0. 3) C2-BT: Proposed case with a zero to counteract the gain falling of T v , where d 0 and D z1 are independently tunable and D z2 = 0. For buck-type cases, the sampling period equals the switching period, T s = T sw , and T d = T s /2. For boost-type cases, the sampling period is half the switching period, T s = T sw /2, and T d = T s .

B. OPTIMIZATION PROBLEM FORMULATION
The objectives presented in Section II-A can be translated to a formal definition by using the corresponding plant model, weighting functions and controller as Figure 4 depicts. Such definition helps to find feasible solutions because known structures from controller K are encapsulated into P. System K c encloses tunable parameters as K ic = [k pi , k ii ] T , K vc = [k pv , k iv ] T , and those involved in Z d as d 0 , D z1 and D z2 . Please note that x ri and x ru are the integrator states of the current and voltage controllers, respectively. It also let us weight the current control error, e i , to ensure zero steady-state value.
The multi-objective optimization problem that formally defines the goals in Section II-B becomes where W s (s), W u (s) and W z (s) are the tracking, control effort and output impedance weights, respectively. The control action sensitivity transfer function from v r b to d is defined as Cases TR-BK, C1-BK, TR-BT and C2-BT may not be able to fulfill the hard requirement, so that Z o ∞ ≤ r d becomes a soft requirement. Besides, the structure on case C1-BK only depends on the voltage controller, and it is ready to shape the output impedance. The multi-objective optimization problem is posed as This non-smooth optimization tool allows multi-model problem definition, so that it is able to synthesize a static controller that fulfills all objectives for a set of R load in the boost-type cases. The resulting controllers, even considering negative R load when the converter operates as load, are similar to the ones designed with the full load model for boost-type.

C. WEIGHTING FUNCTION SELECTION
The desired tracking performance objective is defined [29] by where ω * Bv is the desired voltage closed-loop bandwidth, which is associated to the minimum C o as expressed by (11). Let us recall that the selection ω * Bv depends on the presence of time delays and/or RHP-zeros. This weighting function shapes S v by multiplying by its ideal inverse. If W s has infinity DC gain, the controller K must be synthesized so that S v has zero DC gain. This would mean that the system follows references. In order to ensure zero steady current control error, this function serves to independently weight both e u and e i . Both current and voltage loops are simultaneously tuned, so that this approach will let us to tighten their bandwidths and achieve the best output voltage tracking response in a one-step design. Besides, we consider that this weight also tries to minimize the stand-alone robustness indicator given by S v ∞ = 1/(1 + L v ) ∞ < 6 dB, which guarantees a gain margin, GM ≥ 6 dB, and phase margin, PM ≥ 29 • [29].
For C2-BK, S vt (s) = 1 − T v (s) is not exactly the sensitivity transfer function, S v , due to v o measurement for Z d , but they are similar.
The control effort objective is imposed with W u (s) = k u , where k u is the inverse of the desired S ur ∞ . Additionally, the maximum spectral radius for stabilized dynamics has been set to the Nyquist frequency, ω N = πT s . Both definitions constrain all stabilized poles and zeros from going to infinity as a result of algebraic loops becoming singular or control effort growing unbounded.
The output impedance objective is defined by the inverse of the maximum allowed droop value, that is W z (s) = 1/r d .
All gain objectives are evaluated by computing a normalized scalar value of the infinity norm via a fast algorithm [30]. Please note that this is a offline tuning methodology for static controllers.
Finally, we must evaluate the main tuning goals, that is, the gain requirements over Z o ∞ ≤ r d and S v ∞ < 6 dB. If they are not accomplished, it means that the output capacitance cannot be further reduced using this control structure, filter inductor, switching frequency and selected closed-loop bandwidth, ω * Bv , among other factors. In our case, we only iterate over ω * Bv and its related C o , by using (11). The resulting closed-loop bandwidths may be lower than the ones selected, ω * Bv , using (21). However, as long as the control requirements are fulfilled, we accept the resulting bandwidth and keep the desired C o .

D. CONTROL PARAMETERS TUNING
The initial tunable parameters values are key point to find acceptable solutions. The initial values can be given by previous knowledge about them or random values for every new run of the optimization problem. However, a mix of both of them is considered here by constraining the possible random values for each parameter as: k pi , k ii , k pv , k iv ∈ R + ; 0 < d 0 < ω * Bv ; and D z1 , D z2 ∈ R. The parameter d 0 is constrained so that the pole introduced by Z d is stable and slow enough.
The optimization problem (20) always falls in exactly the same solution, whereas (19) requires at least 100 random initial points to ensure finding an acceptable solution.

V. RESULTS
This section presents the results of the selected cases with the aim of demonstrate the capabilities of the proposed controller design methodology to reduce C o .
The time-domain results are collected considering a DC microgrid with two equivalently controlled half-bridge converters, see Figure 5, connected to a load. The system parameters are collected in Table 1, and they have been selected to compare this proposal with the methodology and droop structures presented in [22]. We are following two comparison methodologies to demonstrate the improvement of proposed cases, C2-BT and C2-BK. For boost-type, C o is kept constant to show better results, while, for buck-type, C o is reduced to show the same results.

A. BOOST-TYPE DC MICROGRID
Cases TR-BT, C1-BT and C2-BT are designed with the same objectives. The maximum desired voltage closed-loop bandwidth that fulfills the objectives for the latter case is ω * Bv = 2π628 rad/s, which is lower than the theoretical limit considering the RHP-zero location with full load, ω Bv < z s /2 = V 2 in R load /(2LV 2 op ) = 2π 1061 rad/s, which is the most restrictive situation. Please note that such limit is expressed for an ideal controller [29], and we are dealing with a cascaded voltage control which is only able to achieve a bandwidth close to that limit. Following equation (11), the minimum output capacitance is 100 µF, if we round it up. The constants for the other weighting function are k u = 10 and r d = 2.53.
The optimization solution for both current and voltage controller are summed up in Table 2. Figure 6 compares the main closed-loop dynamics. Figure 6.(a) depicts the frequency response in magnitude of W −1 s against the resulting S v for each case. All cases accomplish objective S v ∞ < 6 dB with considerably good phase and gain margins, see Table 2. Both cases C1-BT and C2-BT share similar dynamics because they have reached similar current controller solutions, while TR-BT is slower than both of them. Figure 6.(b) shows that both C1-BT and C2-BT have high S ur ∞ , which means a high control effort because of their higher bandwidth, see f cv in Table 2.

1) FREQUENCY-DOMAIN ANALYSIS
The output impedance, Z o , Bode plots are compared in Figure 6.(c). It also displays the measured Z o in a switching simulation, where all cases match the theoretical characteristic up to 5 kHz. On the one hand, C2-BT is the most similar one to a first-order system and Z o (s) < r d , so that the load changes cause minimum under or overshoot.
On the other hand, TR-BT completely fails on the requirement of Z o ∞ < r d , and any load change will lead to significant under or overshoot, whereas C1-BT only reduced Z o ∞ . These results demonstrate that low output capacitance requires a well-designed controller and, specifically, the droop control structure, Z d . Please note the differences on S v and Z o between C1-BT and C2-BT The tracking, T v , Bode plots are compared in Figure 6.(d), where TR-BT is expected to have a small overshoot on step changes of v r b . Cases C1-BT and C2-BT share similar tracking characteristics. However, C2-BT is the most damped case. Table 2 sums up the evaluation indices, where the stand-alone stability margins of the voltage loop come from the definition L v (s) = 1/S v (s) − 1 for the voltage open-loop considering the whole system. Case C2-BT is able to achieve the objectives with good stability margins and reduce the output capacitance by 23.08% with respect to [22], which is a considerable value by control means. Figure 7 depicts the DC bus voltage, V H bus , or, equivalently, the output voltage of each converter, v o1 and v o2 , variation under the same load step for each boost-type case. When both converters are designed following case TR-BT, V H bus has a significant transient sag of 13.75 V and a settling time, within a ±2%, of 12.5 ms, see Figure 7.(a). Considering that the voltage droop variation is 5.06 V, the voltage undershoot is 171.74%, which is unacceptable. For case C1-BT, see Figure 7.(b), the voltage sag is lower than the previous case with an undershoot of 97.6% and a settling time of 45 ms. Still, the voltage is kept within the admissible range in 10 ms, which is acceptable. Case C2-BT, see Figure 7.(c), leads to a very low undershoot of 24.7% and the voltage reaches steady-state in 5 ms. Then, only case C2-BT has an acceptable response with a considerably low output capacitance.

2) EXPERIMENTAL RESULTS
As conclusion, C2-BT performs generally better because it strictly achieves all control objectives with a 23.08% lower C o with respect to reference [22]. Please note that the considered switching frequency, f sw , is half the one considered in reference [22]. Case C1-BT replicates the controller structure proposal in such reference. However, the solution does not achieve the requirements because the overall time delay, T d , is higher.

B. BUCK-TYPE DC MICROGRID
The maximum voltage closed-loop bandwidth that fulfills the objectives for TR-BK and C1-BK is ω * Bv = 2π 750 rad/s, which corresponds to C o = 160 µF. Case C2-BK achieves the objectives with ω * Bv = 2π1150 rad/s, which corresponds to C o = 100 µF, if we round it down. Both desired bandwidths are lower than the theoretical limit considering the time delay, ω Bv < 1/T d = 2π3979 rad/s. The constants for the other weighting function are k u = 10 and r d = 1. 33 The optimization solution for both current and voltage controller are summed up in Table 3.    Figure 8.(a) depicts the frequency response in magnitude of two ideal sensitivity goals, W −1 s , against the resulting one, S v , for each case, which are close for cases C1-BK and C2-BK, respectively. Still, C1-BK with even more capacitance than C2-BK, fails to accomplish the objective S v ∞ < 6 dB. Figure 8.(b) shows that C2-BK requires higher S ur ∞ at higher frequencies, which means a high control effort. A lower capacitance requires higher voltage loop bandwidth, and it leads to higher control efforts, that is, a faster control action.

1) FREQUENCY-DOMAIN ANALYSIS
The output impedance, Z o , Bode plots are also compared in Figure 8.(c). The actual output impedance, which is also depicted, is experimentally measured using the Software Frequency Response Analyzer (SFRA) library embedded in the Texas Instruments digital controllers. Under a steady-state operation point, one converter injects sinusoidal small-signal perturbation into the DC microgrid for each frequency. Meanwhile, the converter under measurement collects its output current and output voltage signals. Then, the fast Fourier transform is applied on the collected data. We may anticipate that case TR-BK has under or overshoot with any load step   change because the requirement Z o (s) < r d is unaccomplished. On the other hand, although its closed-loop dynamics are characterized by two complex conjugate poles, C2-BK is the most similar one to a first-order system. Then, along with case C1-BK, minimum under or overshoot is expected. Figure 8.(d) depicts the voltage tracking, T v , frequency responses agreement with Z o , as expression (9) establishes. It demonstrates that Z d must be frequency-dependent to keep the output impedance gain below the maximum value. Besides, T v is slightly more damped in C2-BK than C1-BK. Table 3 sums up the evaluation indices. Case C2-BK has been able to partly achieve the objectives (high control effort) and reduce the output capacitance by 37.5% with respect to case C1-BK [22].

2) EXPERIMENTAL RESULTS
The experimental tests are carried out in a laboratory-scale DC microgrid prototype with bus voltage V L bus . The load, i load , is changed using a Chroma DC electronic load 63204A. The system parameters for both converters are reported in Table 1. Figure 9 depicts the DC bus voltage variation under the same load step for each droop impedance case. When both converters are designed as TR-BK, V L bus has a significant transient sag of 10.8 V, as depicted in Figure 9.(a).
The steady-state voltage variation caused by the droop is 7.5 V, which means a considerably high voltage undershoot of 44%. For C1-BK, the bus voltage sag is 8.85 V, as depicted in Figure 9.(b). The voltage undershoot is 18%, which is a significant reduction of the voltage sag only by control means. Besides, the voltage sag lasts 1 ms, whereas in the previous case it lasts 3 ms. A slightly higher capacitance would damp even better the voltage variations. However, the objective of this research is to find the output capacitance limit. Finally, Figure 9.(c) depicts the bus voltage sag of case C2-BK. This experiment shows a voltage sag of 9.2 V, that is translated into a 22.66% undershoot. This voltage sag lasts 1 ms with less oscillations, which equals C1-BK case. The dynamic behavior of the proposed design droop, C2-BK, is very similar to C1-BK [22], but it must be noted that the output capacitance is a 37.5% lower.

VI. CONCLUSION
This systematic controller design approach has been proven to be helpful on limiting the capacitance oversizing that designers tend to do. This approach is repeatable and it is not only based on simple common sense and trial and error. Cascaded controllers tuning is usually performed loop by loop. However, once the droop loop is closed, the designed voltage closed-loop response changes, because the droop is out of the analysis. Therefore, it is interesting to design the controller as a whole that complies with the desired voltage control loop performance and output impedance objectives.
The proposed design has explored the limits of this control structure by means of multi-objective optimization techniques that can manage such designs in an automatic fashion. The multi-objective optimization problem proposed here may be extrapolated for other controller organizations and hardware characteristics. However, the designer should always take into account that the objectives must be in accordance with the proposed control structure and plant.