Designs of Branch-Line Couplers by Considering the Parasitic Effects of P-I-N Diodes

Branch-line couplers (BLCs) are commonly used in the wireless systems. To achieve reconfigurable applications, switchable BLCs with p-i-n diodes can be used. Several studies have used diode parasitic reverse-biased capacitor and forward-biased inductor to approach off and on states. Although the capacitance and inductance are usually low, the parasitic effect may degrade predicted switching responses. This study proposes five reconfigurable switching microstrip BLCs. Each of the first two presented BLCs uses shunt to ground diodes for realizing two switching modes. The first mode with reverse-biased capacitors for perfect matching design is equivalent to a conventional branch-line coupler (BLC). The second mode uses low forward-biased inductances to approach shunt to ground, which transfers most signal power from Port 1 to Port 2/4; however, parasitic inductors produce some mismatches. To improve this problem, the proposed third or fourth BLC achieves two perfect matching modes by using shunt stub-loaded diodes. Specifically, by using four stub-loaded diodes, the proposed final BLC exhibits three perfect matching modes and one perfect isolation mode under a lossless ideal circuit condition.

For a switchable circuit, achieving one of its different mode perfect matching conditions may not be difficult; however, simultaneously meeting all mode perfect matching designs are usually challenging. Furthermore, control The associate editor coordinating the review of this manuscript and approving it for publication was Francesco Della Corte . changing response components, such as p-i-n diode, usually cannot prevent unwanted parasitic effects (reverse-biased capacitor and forward-biased inductor), which may highly degrade different mode matching performances of a reconfigurable device. For example, [7] and [8] used p-i-n diodes to approach off and on states. In practical design, approaching p-i-n diode on and off states exhibit parasitic inductance and capacitance. The parasitic inductance and capacitance could affect the predicted lengths of transmission lines and short/open circuit quality. Although [7] mentioned the parasitic effects of p-i-n diodes have to be compensated by additional tuning networks, there is no clear systematic design process to discuss this issue. Therefore, time-consuming optimization processes might be required after completing the initial circuit design. [12] added extra shunt capacitances to compensate p-i-n diode inductances; however, its parasitic capacitances were not solved.
This study proposes five microstrip 4-port switchable BLCs, namely BLC A, BLC B, BLC C, BLC D, and BLC E. BLC A and BLC B are exactly equivalent to a VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ conventional BLC when p-i-n diodes are reverse biased, and most signal power is transferred from Port 1 to Port 4 or Port 1 to Port 2 when diodes are forward biased. However, non-zero parasitic inductances are not avoided in BLC A and BLC B for forward-biased diodes, which degrade predicted performances. BLC C and BLC D substantially improve the performance by using shunt stub-loaded diodes. Finally, BLC E demonstrates perfect responses for three matching modes and one blocking mode from Port 1 to each of the other three ports by using four shunt stub-loaded diodes. Compared with [7]/ [8] has two operation modes, BLC B and BLC D provides detailed designs for solving one and both of the two mode parasitic effects, respectively.    diodes are operated by using reverse-and forward-biased states, respectively. Mode 1 A is equivalent to the conventional BLC. Most signal power is transferred from Port 1 to Port 4 in Mode 2 A . Infineon's BAR65-02 V p-i-n diode is used to design each switching circuit of proposed couplers. Fig. 4 illustrates the diode model, in which the forward-biased state is a series resistor of R D resistance and an inductor of L D inductance, and the reverse-biased state is a capacitor of C D capacitance, with L D = 0.7 nH and C D = 0.34 pF. The practical value of R D is small and slightly affects performances of proposed BLCs, wherein R D = 1 is extracted for each diode of the proposed circuits. To simplify the analysis, R D is considered 0 for all proposed BLC ideal circuit models. Fig. 5(a) and Fig. 5(b) present Mode 1 A and Mode 2 A circuits of BLC A, respectively. In Fig. 5(a), the four capacitances C

II. DESIGN OF PROPOSED BLC A
2 with two parallel capacitors of C A capacitance is equivalent to series two lines X 2 and X 4 of conventional BLC (Fig. 1). They can be derived to form the following equations by using their ABCD matrices.   = 51 are obtained by substituting C A = 0.345 pF and designed center frequency f 0 = 1.8 GHz in (1) and (2). By using the BLC A design, Mode 1 A response is perfectly match with the conventional BLC ( Fig. 1), i.e., |S 21 | = |S 31 | = −3dB, and the phase difference of S 21 to S 31 is 90 • at center frequency. For Mode 2 A , L A = 1 nH and the input impedance of the inductance are low. Therefore, Port 2 and Port 3 approach short circuits. Because θ (A) 1 = 90 • , the input impedance from Port 1 to Port 2 or Port 4 to Port 3 is large. In other words, from Port 1 to Port 2 and Port 4 to Port 3 direction loading effects are negligible. X (A) 2 with its two end shunt capacitors is equivalent to series two lines X 2 and X 4 of the conventional BLC ( Fig. 1). Consequently, |S 21 | and |S 31 | are small and |S 41 | is approximately 1(0dB) because each of Port 1/Port 4 load impedance and characteristic impedance of X 2 /X 4 is 50 , i.e., signal approaches the impedance match at Port 1 or Port 4. Fig. 6 presents the layout and photograph of BLC A. Fig. 6(a) indicates that the signal and biasing circuit are nearly isolated by a resistor of R = 5.6k , which is also used for all other proposed circuits. Fig. 6  supporting the R D neglect in the ideal circuit design. The small R D and minor affections are also included in corresponding responses of all other ideal circuits. Consequently, R D = 0 is used to facilitate all designs of the proposed ideal circuits. For Mode 1 A , the measured insertion losses of both −20log|S 21 Fig. 7(a) and its S 21 to S 31 phase difference is 90 • , as illustrated in Fig. 8(a). However, Mode 2 A ideal circuit responses exhibits some mismatches such as |S 21 | ≈ |S 31 | ≈ −11dB and |S 41 | ≈ −0.75dB at f 0 . Although Mode 2 A can transfer most signal energy from Port 1 to Port 4, some applications may not be accepted by these level mismatches. This problem is occurred because L A = 0 at f 0 , i.e., Port 2 or Port 3 are not exactly equivalent to a short circuit at f 0 . Moreover, when the L A value is zero, phase of  S 41 is −90 • . The third proposed circuit BLC C can solve these parasitic effect problems of non-zero L A value.

III. DESIGN OF PROPOSED BLC B
S parameters S 11 , S 21 , S 31 , and S 41 of four-port symmetric circuit, such as locations of ports in Fig. 1, can be obtained using following equations.
where S 11e/o and S 21e/o are the even-and odd-mode circuit S parameters of the four-port symmetric circuit, respectively. S 11e/o and S 21e/o for Fig. 2 are calculated as follows: In the conventional BLC ( Fig. 1), Points A 1 and A 2 are connected to ground, as illustrated in Fig. 9. The even-mode or odd-mode circuit presented in Fig. 9 is equivalent to the odd-mode circuit presented in Fig. 2 (1 − j) and S 11e = S 11o = 0 for Fig. 9. By using (3)-(6), S 11 , S 21 , S 31 , and S 41 of Fig. 9 are obtained as follows:  Fig. 11(a) and 11(b) illustrate the even-and odd-mode top half equivalent circuits of Mode 1 B , respectively, wherein Z ino2 are input impedances. The design conditions are as follows: where Z ine1 , Z ine2 , Z ino1 , and Z ino2 of (17) and (18) are the input impedances of Fig. 2. From the design conditions (15)-(18), Fig. 2(a) and 2(b) are equivalent to Fig. 11(a) and 11(b), respectively. By using (17) and (18), the following design equations are derived.
All the determined parameters of transmission lines in Mode 2 B are same as those in Mode 1 B . Therefore, the odd-mode circuit of Mode 2 B is same as that of Mode 1 B , which is equivalent to that of the conventional BLC [ Fig. 2(b)] or the even-mode/odd-mode circuit of Fig. 9. When the inductance L B is low, i.e., Points A (B) 1 and A (B) 2 approach short circuits at f 0 , the even-mode circuit of Mode 2 B approaches the odd-mode circuit of Mode 1 B . Thus, Mode 2 B is nearly equivalent to Fig. 9 and approaches the S parameters of (11)- (14). Each of the diodes D  (19) and (20). Fig. 12 presents the layout and photograph of BLC B. In Fig. 12 Fig. 13(a) and its S 21 to S 31 phase difference is 90 • , as illustrated in Fig. 14(a). However, Mode 2 B ideal circuit responses exhibit some mismatches such as Type A of [7] is an equal power splitting conventional BLC (Fig. 1) which can connect shunt to ground p-i-n diode to each of Points A 1 and A 2 . Type A of [7] used ideal open and short to design each diode switching model. However, the model deviates from the practical design situation. Figs. 15 and 16 show ideal circuit simulations of BLC B and Type A of [7] wherein each diode uses the proposed model of Fig. 4 (C D = 0.34 pF, L D = 0.7 nH, and R D = 0 ), i.e., each diode in Type A of [7] replaces ideal open and short with C D = 0.34 pF and L D = 0.7 nH for representing reverse-and forward-biased states, respectively. Fig. 15(a)    Type A of [7]. In other words, only BLC B achieves perfect the phase specification ( S 21 = −90 • and S 31 = −180 • ) of the conventional BLC. The transmission line parameters of BLC B need to be properly designed according to parasitic capacitance C D , but those of Type A in [7] didn't provide a clear systematic procedure to modify them although [7] mentioned the parasitic effects of p-i-n diodes could be compensated by additional tuning networks. In addition, the two BLCs have the similar mismatches when all diodes are operated in forward-biased states as shown in Fig. 15(b) and Fig. 16(b) because the two circuits don't modify the parameters of transmission lines according to the forward-biased parasitic inductances of diodes. Both of the reverse-and forward-biased parasitic effects can be included in the fourth circuit design of BLC D to achieve perfect matches in the two operated modes.

IV. DESIGN OF PROPOSED BLC C
In (21), f 0 is the operating center frequency and L D is determined when the diode is selected. One of Z (C) S and θ (C) S can be arbitrarily designed and the other one can be solved using (21). The second step is Mode 1 C design. In Mode 1 C , each of Z inD2 designs to equal the input impedance of shunt capacitor at each of Port 1 and Port 4, i.e., the design equation can be written as follows: In (22), Z S and θ (C) S are determined for Mode 2 C , and C D is a well-known parameter when the diode is used in Mode 2 C . Thus, C C is determined. θ are solved using (1) and (2) because f 0 and C C has been determined. Therefore, Mode 1 C is equivalent to Mode 1 A as the conventional BLC of Fig. 1 at the center frequency f 0 , i.e., X = 79.25 • , and C C = 0.33 pF are obtained using the BLC C design. Fig. 18 presents the layout and photograph of BLC C. The three biasing lines BL 1C , BL 2C , and BL 3C presented in Fig. 18    2 are short circuits. The even-and odd-mode circuits of Mode 2 D are same and equivalent to the Mode 1 B odd-mode circuit of BLC B, which is equivalent to the conventional BLC odd-mode circuit of Fig. 2(b). Based on the analysis presented in Section III, the S parameters of (11)- (14) are successfully achieved in Mode 2 D , i.e., all signal power is perfectly transferred from Port 1 to Port 2 and the phase of = 42 • are obtained using the BLC D design. Fig. 22 presents the layout and photograph of BLC D. The three biasing lines BL 1D , BL 2D , and BL 3D presented in Fig. 22      in BLC C (Fig. 17), respectively, i.e., θ By substituting θ inD2 are equivalent to the input impedance of a shunt to ground capacitor with C SE (C SE = C E = C C ), and the even-or odd-mode circuit of Mode 2 E is equivalent to the odd-mode circuit of Mode 1 C in BLC C. Because Mode 1 C is equivalent to the conventional BLC, even-and odd-mode circuits of Mode 2 E are equivalent to the odd-mode circuit of the conventional BLC. Therefore, the S parameters of (11)- (14) can be achieved in Mode 2 E . After above BLC E design, all parameters of BLC E have been determined and Mode 3 E is equivalent to Mode 1 C of BLC C, i.e., Mode 3 E is equivalent to the conventional BLC. In Mode 4 E , Z 4 ), i.e., signals are not transferred between adjacent ports because they are blocked by these short circuits. Fig. 26 presents the layout and photograph of BLC E. The five biasing lines BL 1E , BL 2E , BL 3E , BL 4E , and BL 5E presented in Fig. 26(b) are sourced by V 1E , V 2E , V 3E , V 4E , and V 5E voltages, respectively.   Table 1 presents a comparison between the proposed and previous switchable couplers with p-i-n diodes. The perfect matching and perfect blocking modes are under lossless condition for transmission lines, via holes, and diodes. [7]/ [8] and [25] used reverse-and forward-biased states of each VOLUME 8, 2020  diode to approach off and on states, respectively; however, the reverse-biased capacitance and forward-biased inductance that might degrade the predicted performances were not given a detailed discussion or solution. [12] used an extra capacitor in parallel with p-i-n diode to compensate the undesired inductance; however, the extra capacitor and reverse-biased capacitance of each diode were not considered in the circuit, which could affect the predicted line lengths. Although [26] included the reverse-biased capacitance and forward-biased inductance of each diode in simulation, the capacitance and inductance did not in the design equations, i.e., each diode circuit model was added after following proposed design equations. This design procedure could require time-consuming optimization. Compared with BLC A/B, BLC C/D provided two perfect similar matching design modes; however, they require extra open stubs. The size of BLC C/D is larger than that of BLC A/B. Therefore, a trade-off selection may be required between BLC A/B and BLC C/D. BLC E achieves three perfect matching modes and one perfect blocking mode, which successfully includes complicated diode parasitic effects in the multifunction circuit design. However, compared with BLC C/D, BLC E requires extra two stubs and two diodes, i.e., BLC E needs additional circuit size and costs of elements. There still exists a trade-off selection value between BLC E and BLC C/D. This study including the five circuits in one paper can demonstrate several switching designs of similar BLCs by considering parasitic effects of p-i-n diodes and trade-off designs between the BLCs. Compared with [7], this study gives the detailed design discussion in parasitic resistor, inductor, and capacitor of p-i-n diode for affections of switching BLCs. Besides, systematic and trade-off designs considering parasitic effects are included in the manuscript.

VIII. SWITCHING EXAMPLES USING PROPOSED BLCS
This section demonstrates switching examples using proposed BLCs with signal source at Port 1 of each BLC. BLC C can connect a vertical polarization dipole antenna at each of Ports 2, 3, and 4. For Mode 1 C , the antenna beam pattern can be indicated a certain direction because |S 21 | = |S 31 | and the phase difference between S 21 and S 31 of BLC C are 3 dB and 90 • , respectively, i.e., this mode is an 1 × 2 antenna array. Mode 2 C is an omni-directional antenna at Port 4 and no antenna radiation at Port 2/3 because

IX. CONCLUSION
This paper presents five reconfigurable switching BLCs (BLC A to E). BLC A and BLC B use shunt to ground diodes to realize two operation modes. One mode is equivalent to a conventional BLC and the other mode can transfer most signal power from Port 1 to Port 2/4. However, BLC A and BLC B present one mode mismatch problem caused by the forward-biased state non-zero inductances of diodes. To overcome this problem, BLC C and BLC D with stub-loaded diodes successfully exhibit two perfect matching modes in ideal circuit. By using design concepts of BLC C and BLC D, the final coupler proposed is BLC E, which exhibits three perfect matching modes and one perfect blocking mode from Port 1 to the other three ports. All the proposed BLCs are carefully verified for measured and simulated results.