A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC

This article presents an accurate quadrature phase-locked loop (PLL) with quadrature phase mismatch calibration for 32 GS/s analog-to-digital converter (ADC). Due to the mismatches of clock distribution in layout and variations of the active devices, the quadrature phase of the sampling clock is significantly deteriorated. To solve the problem, a novel quadrature divider with phase calibration is induced in PLL loop. Moreover, a theoretical model of the quadrature divider is proposed to predict the performance and potential ability for phase calibration. Based on the theoretical and model analysis, the proposed PLL can realize accurate quadrature phase for high-speed real-time sampling system. The output frequency of PLL is 8 GHz with quadrature phases for 32 GS/s sampling rate. The proposed clock can realize 8-bit signal to noise ratio requirement with 16 GHz bandwidth. The proposed PLL was fabricated in 65-nm CMOS process with 28 mW dc power consumption under 1.2 V supply voltage. Testing results show that the phase noise of the clock is −127 dBc/Hz @10 MHz-offset frequency when the sampling speed is 27.4 GS/s. With proposed methods, the range of the phase error calibration is around ±20°.


I. INTRODUCTION
Nowadays, with the large amount of internet of thing (IoT) and wideband of 5G-communication technology, the bandwidth of the signals is getting wider and wider. To analyze these wideband signals with complex modulation types, the broadband analog to digital converters (ADCs) [1]- [3] are widely utilized to sampling the signals. The chips related to the sampling systems of the ADCs are widely implemented by GaAs process due to their high-speed characteristics. However, due to the limited integration capability, the price of the module for high-speed sampling is too expensive to be widely utilized. High-speed and real-time sampling circuits are the front-end part of oscilloscope, which consists of the high-speed track-and-hold amplifier (THA) and sampling clock. The function of the THA is to sample the wideband analog signals and the sampled voltages are converted into digital codes by analog to digital converter (ADC).
The associate editor coordinating the review of this manuscript and approving it for publication was Yong Chen . Due to the limited conversion speed of a single-channel ADC, time-interleaved technique is widely utilized. For example, article [3] shows a 56 GS/s ADC with 256 parallel channels and speed of each channel is only several hundred MS/s. With this time-interleaved structure, the high-speed sampling system design challenge moves to front-end THA design and clock distribution. Because the signal to noise ratio (SNR) of the sampling system performance is dramatically related to the clock jitter and clock skew between these channels, the clock sources are very important. A timeinterleaved 6-bit THAs with 32 GS/s for high-speed sampling system is implemented in article [4] and the clock generation for the time-interleaved sampling system is analyzed and optimized in this article. The time-interleaved sampling clock generally requires multiple phases and each phase is utilized to sample the signal for an individual THA.
The sampling structure can be classified into three structures based on the clock distribution structure. The most widely utilized structure is directly multi-phase sampling [5] with low resolution. There is a trade-off between the number of the THA and its SNR. Because the sampling time error between channels dramatically increases with large number of the channels due to the circuit variation and the asymmetry clock tree. Though the clock skews between differences sampling channels can be calibrated and the clock locates exactly sampling time to reduce the sampling error, the calibration algorithm is complex and needs extra chip area and power [6]. The SNR of this structure is limited to 6∼8 bits after calibration. The secondly structure is full-rate sampling structure. Compared with the directing multi-phase sampling, the fullrate system can reduce the phase error without calibration. However, the front-end high-speed sampler is sensitive to the jitter of the sampling clock and the speed of the THA is difficult to implement. Based the above system analysis, quadrature-rate samplers with hierarchy sampling structure can unify two superiorities and the design challenge of the sampling system is quadrature phase clock with low clock jitter, low clock skew and high stability over process, voltage and temperature (PVT) variation [6]- [10].
Compared with the clock implemented by the voltagecontrolled oscillator (VCO), phase locked loop (PLL) has more advantages because it can stabilize the frequency and phase over long time and PVT variation. Moreover, the PLL loop can filter the low frequency jitter of the VCO and optimize integration root mean square (RMS) jitter of the clock. Compared with the deterministic phase error, the jitter of the sampling system is random and difficult to suppress. In this article, the phase noise of the PLL is systematically optimize. However, the sampling phase error of the quadrature signals cannot be calibrated which are induced by the asymmetry layout and device mismatches.
In traditional method, the phase error calibrations require complex calibration algorithms that are complicated and power consumption in digital domain. In this article, the proposed chip is verified the phase skew calibration with an efficient structure with good results. To realize the phase skew calibration, the resolution of phase skew calibration circuit should be good enough. Traditional phase error calibration is realized by tuning the time delay of the inverter chain or phase of the phase shifter. However, resolution of conventional method is limited to picosecond. To overcome this limitation, this article overcome above problems and proposed an injection-locked quadrature divider with quadrature phase mismatch calibration as shown in Fig. 1.
This article is organized as follows. Section II presents the phase noise optimum of each blocks in PLL. Section III proposed the working principle and quadrature divider model for phase error calibration based on injection locking structure. Section IV shows circuits implements of the proposed quadrature PLL. Measurements results are shown in Section V and conclusions will be drawn in Section VI.

II. PHASE NOISE AND CLOCK JITTER ANALYSIS
With 32 GS/s sampling speed and 48 dB signal-to-noise ratios (SNR) requirements, an extremely low aperture jitter sampling clocks is essential. In this section, the theoretical phase noise optimizing of each block for sampling clock will be presented.

A. ANALYSIS OF THE SNR PERFORMANCE RELATED TO CLOCK JITTER AND PHASE NOISE
The spectrum purity of the PLL is often described in terms of phase noise rather than time jitter [4]. The phase noise shows the noise power in a 1-Hz bandwidth as a function of frequency as shown in Fig. 2(a)-(b) and it is defined as the ratio of the noise in a 1-Hz bandwidth at a specified frequency offset f m to the sampling clock signal amplitude at frequency f c . Compared to jitter characterizing time domain uncertainty, phase noise describing the signal purity in frequency domain is more widely used in radio frequency. The reason is that the phase noise is easier to be captured and measured by equipment with many practical methods. However, the accurate measurement of jitter needs high-speed oscilloscope whose sampling speed is at least 5 times of single bandwidth. What is more, enough sampling data is required to capture the history of data to analyze. Because the phase noise of each building blocks in PLL loop can be well calculated, it is meaningful to develop an accurate method for converting the time jitter in into phase noise of sampling clocks. The performances (SNR, SFDR, and THD) of time-interleaved ADCs are degraded by the jitter and phase skew of the clock [7].
Jitter in the sampling clock means uncertainty in the exact sample moment and the deviation from the ideal sampling moment leads to a voltage error in the sampled voltage. The sampling process is a multiplication of the sampling clock and the analog input signal. The multiplication is realized in the time domain and it is equivalent of the sampling clock is convolved with the input. For a full-scale sinusoid with frequency f in the signal-to-noise ratio can be expressed: where the σ ( t) is sampling time error which can be jitter or phase skew, f in is the input full-scale sinusoid. The SNR and effective number of bits (ENOB) are the function of the time error. Generally, jitter is classified into absolute jitter and cycle-to-cycle jitter which can be expressed as Compared to the absolute jitter, cycle-to-cycle jitter describes the short-term dynamics of the period and represents the RMS difference between two consecutive periods that is more meaningful for sampling system.
Article [11] shows that cycle-to-cycle jitter can be converted phase noise when the noise is white. However, the cycle-to-cycle jitter is not accurately to evaluate the SNR performance because the flicker noise is relative larger than white noise. RMS requirement for a time-interleaving sampling system is enough for sampling system [8]. Thus, each phase noise contributes to RMS phase jitter that can be expressed as where f c is carrier frequency, L(f ) is the function of the phase noise. The low f m phase noise degrades the fundamental signal into several frequency bins and reduce the overall spectral resolution. The flat and high f m phase noise increases the noise floor and degrades overall SNR. To optimize the SNR, PLL can be utilized to reduce the low f m by filtering the low f m of the oscillator. The flat and high f m phase noise is realized by reducing the phase noise in each block.

B. PHASE NOISE ANALYSIS OF EACH BLOCKS AND NOISE OPTIMIZING
In this article, the quadrature PLL is utilized the linear phase noise analysis model [12] as shown in Fig. 3. K pd is the gain of PFD and charge pump. K vco is the VCO conversion gain. Z lf (s) is the impedance of the loop filter. N is the ratio of the divider. The PLL open-loop phase transfer function can be expressed as Phase noise induced by each building block is referred to its output θ out (s). Based on the phase noise analysis, the phase noise contribution of each block is analyzed and optimized.

1) PHASE NOISE FROM REFERENCE in (s)
The phase-noise contribution of the reference oscillator as a function of the frequency offset f m is modeled by where the f c is reference frequency and an electrostaticdischarge-protected CMOS inverter is utilized for ESD protection as shown in Fig. 4. The reference buffer converts the crystal oscillator signal into a rectangular signal. To reduce the noise contribution by the buffer. The transconductance of the transistors should be large enough to reduce the transition VOLUME 8, 2020  time from sinusoidal wave to rectangle waveform making this noise negligible. Its noise transfer function is expressed as It is low pass filter for input reference phase noise. The only way to reduce it is using high quality crystal oscillator and high gain input buffer to reduce the transition time.

2) CHARGE PUMP (CP) NOISE i cp (s)
The model of CP is shown in Fig. 5 It converts the instantaneous the phase difference to current pulses and the charge box is delivered to the loop filter. The nonlinearity of the CP will induce the incorrect amount of charge and this distorts the CP current introduces reference spur. The reference spur can also degrade the purity of the PLL output. A CP has both broadband noise and flicker noise. After the PLL locked, the CP output pulse width τ is a certain value determined by the reset time of the PFD and its frequency is same as the input reference frequency. The current source consists of the flicker noise and white noise which can be expressed as where k is Boltzmann's constant, T is temperature, the g m is the transconductance of the current source, the W /L is the geometry of the devices, C ox is the unity capacitance of the gate, and K is an empirical number. Typically, the flicker noise corner is below the reference frequency and the flicker noise oversampled. The broadband white noise is under-sampled. To derive the output spectrum of sampled broadband noise of the CP, the output PSD of the sampled broadband noise and flicker noise can be expressed as where the T ref is the period of the reference clock, i 2 cp,w is the white noise spectrum and the i 2 cp,1/f is the flicker noise. Its noise transfer function is expressed as It is low pass characteristic. After noise optimum, the current is 200 µ A.

3) LP FILTER NOISE ANALYSIS
For the sake of simplicity and completeness a three-order passive loop filter as shown in Fig. 6. This noise analysis due to thermal noise of the resistors, is given by where R 1,3 are resistors and C 1,2,3 are capacitors.
Its noise transfer function is band-pass characteristic. The noise is optimized by reduced the value of the resistors. However, the size of the capacitor will be enlarged. As a result, there is a traded-off between the area and the noise. After optimizing the phase noise, the loop filter parameters are as follows: C1 = 86pF, C2 = 4.3pF, C3 = 4.3pF, R1 = 6.2k ohms and R3 = 3.1k ohms.

4) VCO PHASE NOISE ANALYSIS θ vco (s)
Cross-coupled transistors are utilized in VCO and the noise are contributed by the active devices. The phase noise performance of the VCO is also determined by quality factor of the inductor and capacitor and its phase noise can be expressed as where P s is average power dissipated in the resistive part of the tank, Q L is quality factor of the VCO, f m is frequency offset from carrier, f c is oscillator carrier frequency, and F is the empirical parameter. Its noise transfer function is expressed as Its noise transfer function is high-pass characteristic. Thus, lower loop bandwidth can filter more low frequency noise of the VCO. However, it is sacrificing the locking time.

5) DIVIDER PHASE NOISE ANALYSIS θ div (s)
The divider structures are static source-coupled logic (SCL) dividers and true single-phase clock logic (TSPC) divider. The noise sources of SCL are mainly contributed by the loading resistors and the phase noise of the TSPC divider is sensitive to the slow slope of the waveform at the zero crossings. The resulting jitter and transfer function are expressed as where the C L is the loading capacitor and I B is the bias current as shown in Fig. 7. The noise transfer function is also low pass filter characteristic. The jitter is the ratio between the noise power of the capacitors and the square of the bias current. Because the load capacitor is certain, and the noise is inverse proportional to the bias current, thus increasing the bias current reduces the jitter.  Because different blocks noise has different transfer function and several trade-offs exists in the loop. Based on the system analysis, the phase noise of the total is shown in Fig. 8.

III. QUADRATURE PHASE MISMATCH CALIBRATION
The quadrature phase error degrades the SNR and cannot be filtered by the PLL loop. After the phase noise optimizing, the phase skew should be minimized for time-interleaved sampling. The quadrature phase can be generated by three methods. First method is utilizing the differential outputs of the VCO to drive a passive RC-CR phase shifter [13], [14]. However, the phase shifter attenuates the high frequency signals and has weak drivability. Thus, high gain buffers are needed which consume large power and degrade the phase noise performance. The second method is using QVCO to generate quadrature signals [15]. However, its quadrature phase and phase noise are highly correlated. Thus, the quadrature phase is difficult to be calibrated. The third method is using quadrature divider to generate quadrature signals. Because its quadrature phase and phase noise are independently [16]- [19]. With the novel divider circuit structure, the quadrature phase error can be calibrated.

A. CONVENTIONAL PHASE SKEW CALIBRATION METHODS
Due to the asymmetry of clock distribution in layout and active devices variation in CMOS process variation, the quadrature phase has mismatches. Traditional method to VOLUME 8, 2020  calibrate the phase skew in low frequency is inserting tunable delay cells in clock tree. The delay chain is consisted of several stage inverters. The delay of the inverter is determined by the bias current as shown in Fig. 9. With different delay cells inserted into the quadrature clock phase, the phase skew can be calibrated. However, this method is widely used in low speed digital circuit whose clock frequency is limited to several hundred MHz due to the limited bandwidth of the delay cells. Moreover, its phase skew resolution is limited to picosecond that cannot meet the requirement of this article.
The phase skew calibration for radio or even mm-wave frequency is a completely different method. Passive phase shifter [20]- [22] is widely for phase tuning due to its simple structure, low power consumption and good power linearity. Its phase tuning is realized by changing the electrical characteristics of its path or switching between different paths. Passive phase shifter consists of high-pass/low-pass network for phase shifter as shown in Fig. 10.
For the low-pass π network in Fig. 10, the normalized transmission (ABCD) matrix of the circuit can be expressed as With the normalized impedance and admittance of these lumped elements, where ω 0 is the center frequency and Z 0 is the characteristic impendence. The forward transmission coefficient S 21 and the phase ϕ of S 21 are expressed with the following equations The loss of the phase shifter (S 21 ) in different channels are different in different phase state, as a result the phase shifter will introduce amplitude error. Moreover, its phase skew resolution and accurate is highly determined by the device matching. The passive devices also take large areas and not suit for multi-phase time-interleaved structure. Based on above analysis, the conventional methods do not meet the specification requirements.

B. PHASE SHIFT MODEL OF INJECTION LOCKED OSCILLATOR
A simplified model for the oscillator is shown as Fig. 11(a). The LC-tank oscillates at f 0 = 1/

√
LC if the parasitic is neglected. Transistor M 1 compensates the energy losses in R 1 and offers a 180 • phase shift. Then the closed-loop phase shift is 360 • . When a signal is injected into the oscillator, the phase shift α occurs due to the disturbance and the output frequency of the LC-tank is forced to follow the input frequency [23]- [25]. When the injection frequency is in the locking frequency range, according to the phase difference in Fig. 11(a), the input and output voltage are respectively expressed as: where the V in is input frequency, whose frequency is ω inj . α is the phase shifter induced by the injecting-locked oscillator. According to the model in Fig. 11(b), based on the model and its equations for the output voltage amplitude A and output voltage phase θ as expressed as where I is the tail current of the cross-coupled oscillator, I inj is the injection current. It is a compact differential equation [23] of phase that applies to any strength of injection, assuming only that the transconductors are hard-limited.

C. PHASE SHIFT MODEL OF INJECTION LOCKED DIVIDER
Based on the model of the injection-locked oscillator, the model of injection locked divider is composed of mixers for frequency conversion. The cross-coupled pair is modeled as a hard-switching mixer driven by the output voltage. The mixer output current is injected into an LC load. Assuming a signal with 2ω inj2 frequency is coupled to the gate of transistor current source, then it injects a current I mix with the frequency of ω inj2 into the LC tanks. Then, the output voltage of the LC-tanks is fed back to the mixer. Higher harmonics current injected into the LC-tanks are filtered due the narrow band-pass characteristic of the LC tank. Based on above model as shown in Fig. 11(c), when two LC-dividers are driven by differential signals whose oscillation frequency is the twice of the desired frequency, the two LC-dividers output phases have 90 • phase shifted which shown in Fig. 12. Its model can be simplified two divider models because there is no coupling between the two dividers. Based the model analysis, the equations can be expressed as: where V in/ip are input differential signals and V I ,Q are the output quadrature signals. α I is the phase shift generated by the divider. This structure has two drawbacks [26]- [29]. Firstly, the quadrature phases are sensitive to device mismatches. Secondly, the quadrature phases are highly related to its input anti-phase signals. If input signals are not ideal anti-phase signals with phase error, the quadrature outputs have phase error. The input signals of the divider are not ideal anti-phase due to the asymmetry layout and devices mismatches of VCO and its asymmetry signals distribution.

D. PROPOSED DIVIDER MODEL WITH MATHEMATICAL ANALYSIS
In this article, we proposed a quadrature model with tunable coupling coefficient and injection coefficient between the two parts of the dividers. To make the quadrature phase insensitive to the input anti-phase signals, the other injection locked loop is induced between the two LC-dividers as shown in Fig. 13. To build a model for the quadrature LC divider, it is important to define how the two divider cores are coupled. Fig. 13 shows the quadrature divider model. We denote the two differential output voltages by A 1 exp (jθ 1 ) and A 2 exp (jθ 2 ). After a phase lag of φ 1 and φ 2 , each output voltage determines the injection current into the other tanks which are expressed as The output current of mixer is made of the mixed current of the tank and the synchronizing double frequency injected signal which are expressed as where R 1,2 and C 1,2 are resistance and capacitance of the two tanks, respectively, A 1,2 are the amplitudes of the two tanks and ω 01,2 are the self-oscillation of the tanks which are 1/ L 1,2 C 1,2 . λ 1,2 are the current ratio which can be expressed as Even though the analytical solution of (31) ∼ (36) is not evident, numerical solution can show us some intuitive information. The building blocks of the equations are basic mathematic symbol and an implementation in Matlab Simulink is shown in Fig. 14. If the two oscillator cores are perfectly matched, then the phase difference between V out1 and V out2 is 90 • as shown in Fig. 15.

E. QUADRATURE PHASE MISMATCH CALIBRATION
The phase difference deviates from 90 • unless the two circuits are perfectly matched. Mismatches happen between pairs of coupling currents, regenerative currents, phase-shifters, and tank resonance frequencies, as well as in quality factors. Mismatches are characterized as follows: ω 01 = ω 0 + ω/2, ω 02 = ω 0 + ω/2, R I = R 0 + R/2, R Q = R 0 + R/2, I 1 = I 0 + I /2, I 2 = I 0 + I /2, I c1 = I c0 + I c /2, I c2 = I c0 + I c /2, I m1 = I m0 + I m /2,I m2 =  φ m0 + φ m0 /2,φ 4 = φ m0 + φ m0 /2 and assume that the mismatches are small enough that the two oscillators remain locked at a common frequency. Inserting all the mismatches in (31)∼(36), the quadrature phase error θ is expressed as The higher the coupling factor m = I c /2I , r = I mo /2I , the smaller the quadrature error. Phase error analytical expressions (36)-(37) can be derived to optimize the circuit parameters and shows the simulation results when the inductors and capacitors have mismatches as shown in Fig. 16. By tuning the bias voltage VB_I/Q to compensate the I mismatch as shown in Fig. 17, the θ can be calibrated to realize phase adjustment based on the analysis of expressions (37). Thus, it is a feasible method to compensate the phase shift due to various mismatches.

IV. CIRCUIT IMPLEMENTATION
The quadrature PLL can guarantee a long-time stability of the output frequency and the quadrature phase calibration can guarantee the quadrature phase accuracy. The section will introduce the circuit design of the proposed quadrature PLL.

A. FREQUENCY AND PHASE DETECTOR (PFD) DESIGN
Based on The inputs of the tri-state PFD are the single-end reference clock from input reference clock and the last stage divider output from the divider chain. Inverter is utilized to sharp the edge of the clock signals. The outputs of the PFD are two pairs of differential signals that are connected to the charge pump. Symmetry layout and a transmission gate are utilized to compensate the time mismatch between UP signals and DOWN signals. Based on the phase noise analysis, the PFD dead zone is eliminated with a 200 ps delay implemented by inverter chains before the reset of the D flip-flop.

B. CHARGE PUMP (CP) CIRCUIT DESIGN
A fully differential CP is utilized to reject the commonmode signals and noise. The sink and source currents source mismatch are reduced by utilized a rail-to-rail operational amplifier that can also reduce the charge sharing effect, simultaneously. As a result, mismatch of the charge pump is less than 1% and the output voltage range cover of 90% the power supply as shown in Fig. 18. A capacitor with one resistor is utilized to compensate the phase margin of the amplifier over the 0.1-1.1 V output voltage range. A low pass filter is utilized to filter the low frequency flicker noise and the output current of CP is 200 µA.

C. VOLTAGE CONTROLLED OSCILLATOR (VCO) CIRCUIT DESIGN
This article utilizes traditional VCO structure with single LC tank structure including inductor and negative resistor as shown in Fig. 19(a). To realize a wideband VCO that is preferred to overcome PVT variation and improve sampling frequency range. However, there is a trade-off between the phase noise and frequency tuning range because large tuning range results in high gain of VCO [30]. The VCO is sensitive to the noise due to the high gain. In order to break the trade off, digital controlled capacitor arrays (DCCA) are used. Then, several tuning curves are realized to replace one curve. In this article, two switched controlled (DCCA) are utilized to realize four tuning curves for frequency tuning. Thus, it can realize wide frequency range with low phase noise.

D. QUADRATURE DIVIDER DESIGN
The proposed quadrature divider consists of two mixers (M 9 and M 10 ) and two LC divider coupled by transistors (M 3 , M 4 , M 7 , and M 8 ) as shown in Fig. 17. Because the coupled transistors (M 3,4 ) and (M 7,8 ) are biased at VB I −Q voltages, another injection locked loop exists in the dividers itself which reduce the sensitive to the mismatch of the input anti-phase signal. The bias of the injection signals VI I ,Q also can be adjusted to compensate the phase of the mixer. A programmable divider chain is implemented to realize different the output frequency range under a same input reference frequency. Following the quadrature divider structure is current mode logic that is implemented due to its wide frequency working range [31]. True single-phase clock (TSPC) logic divider with two modes  is utilized to realize the programmable divider ratio (8∼15) as shown in Fig. 19(b).

V. MEASUREMENT RESULTS
The chip photo is shown in Fig. 20. The chip is connected to the testing boards by the bonding wires as shown in Fig. 21. The inductance of the bonding wires is simulated and optimized with 3-D electromagnetic High-Frequency Structure Simulator (HFSS). After the measurement is setup, the PLL feedback loop stability is measured. After PLL is locked, the phase noise and phase calibration are measured, respectively.

A. PHASE LOCKED LOOP STABILITY MEASUREMENT RESULTS
The output voltage of the last stage divider is captured to check phase alignment with the input reference clock. The control voltage of the VCO is measured to check the PLL stability. The transient signals are measured by Agilent DSOX91304A oscilloscope with 2GS/s as shown in Fig. 22. Based on the analysis of the control voltage ripple, the phase margin of the PLL is larger than 45 • .

B. PHASE NOISE MEASUREMENT RESULTS
The phase noise is measured by Keysight E5052A which can measure the phase noise of the signal frequency up to VOLUME 8, 2020   26.5 GHz. The output pads are bonded to transmission lines with 50-ohms characteristic impedance the on-PCB traces. The insertion loss of cable, bonding wires and SMA is around 3-4 dB at 8 GHz. The measurement phase noise is -101 dBc/Hz @1 MHz offset frequency at 6.85 GHz center frequency. The phase noise is measured as shown in Fig. 23. Compared to the summation results, the in-band phase noise is larger than the simulation. The reason is the CP noise is  larger than the simulation results. The time-domain measurement is shown in Fig. 24.

C. QUADRATURE PHASE AND CALIBRATION MEASUREMENT RESULTS
The transient quadrature phase measurement of the quadrature divider is difficult to measure due to the high frequency and the mismatches of bonding wires, connectors and cables. The transient signals are measured by Keysight DSOX91304A oscilloscope with 40 GS/s and 13 GHz bandwidth.
The output swings of the quadrature signals are around 200 mV from 5.4 to 8 GHz. The measured I/Q phase error caused mismatches including devices, bonding wire, PCB traces and connection cable are within −20 • ∼20 • without quadrature phase calibration. The measurement shows that the calibration range is ±20 • which can fully cover the above PVT variation and meets the sampling system requirement as shown in Fig. 25-26.

VI. CONCLUSION
In this article, a design methodology for quadrature PLL for 32 GS/s time-interleaved ADC is proposed. Based on the proposed model and simulation results, the quadrature phase error is well predicted and calibrated. With the proposed calibrated methodology, the mismatches induced by the asymmetry of the layout, bonding wires, connectors and cables are well calibrated with range of ±20 • phase mismatch capability. Due to above good performance, the quadrature PLL can is suitable for four-channel time-interleaved sampling system with 8-bit SNR requirements and 16 GHz bandwidth.
SHUNLI MA (Member, IEEE) received the B.S. degree in microelectronics engineering from Shanghai Jiaotong University, Shanghai, China, in 2011, and the Ph.D. degree in micro-electronics engineering from Fudan University, Shanghai, in 2016. From 2012 to 2014, he was a Project Officer with Nanyang Technological University, Singapore. From 2016 to 2017, he worked in industry and designed 77-GHz FMCW PLL for automotive radar sensor. He received the Distinguished Designer Award for mm-wave PLL design for automotive radar.
He is currently an Assistant Professor with the State Key Laboratory of ASIC and Systems, Fudan University. He has authored or coauthored many high performances mm-wave circuits articles on top conferences, including ESSCIRC, CICC, RFIC, ASSCC, and IMS. His research interests are millimeter-wave integrated-circuit design, including mm-wave imaging sensing, mm-wave PLL and high-speed sampler in ADC, and biomedical RF circuits for cancer detection. His article has received finalist at IMS '