A Four-Phase Passive Mixer-First Receiver With a Low-Power Complementary Common-Gate TIA

This paper presents a four-phase passive mixer-first receiver using a common-gate (CG) trans-impedance amplifier (TIA), instead of a conventional shunt-feedback amplifier. The four-transistor TIA used in this work combines current-reuse with cross-coupled $g_{m}$ -boosting to achieve a reduced noise figure (NF) at low power levels. Moreover, complementary derivative-superposition (CDS) linearization within the TIA helps to improve the linearity with no additional power overhead. A prototype receiver is implemented in a 180 nm CMOS technology. The receiver operates from 0.3 to 1.3 GHz with a conversion gain of 21.9 dB. In measurements, the receiver achieved a noise figure of 5.8 dB and an in-band (IB) IIP3 of +7.2 dBm while consuming 0.34 mW power per TIA at 1 GHz. The measured spurious-free dynamic range (SFDR) at 1 GHz is 76.9 dB.


I. INTRODUCTION
Several new wireless communication standards are being proposed to satisfy the ever-increasing user requirements. In order to support more than one communication standard (existing or new), modern-day radio receivers need to be frequency agile. Since most of these receiver front-ends are used in portable devices, reducing the power consumption is necessary to increase battery life. Typically, two types of power consumption are associated with a receiver [1]- [7]: dynamic and static. The dynamic power consumption is due to the clock buffers driving the mixer switches, while the static power consumption is due to the radio frequency (RF) low noise amplifier (LNA) [8]- [11] and the baseband (BB) trans-impedance amplifier (TIA). In recent years, [12]- [39] have employed a passive mixer as the first block of the receiver instead of an LNA. Mixer-first receivers [12]- [39] offer many advantages over traditional LNA-first receiver architectures [1]- [3], [5], [6], making them suitable for next-generation software-defined radios (SDRs). Some of these advantages include frequency tunability, high linearity, and blocker resilience. A typical four-phase passive mixer-first receiver is shown in Fig. 1(a). In a mixer-first receiver, the TIA provides the input-match and has a major The associate editor coordinating the review of this manuscript and approving it for publication was Yong Chen . (b) Trade-offs in the design of the TIA for a mixer-first receiver [40]. effect on the overall noise and linearity performance of the receiver. Typical trade-offs involved in the design of the TIA for a mixer-first receiver are shown in Fig. 1(b) [40]. In highlinearity mixer-first receivers presented in [20], [23], [24], the BB TIAs consume a significant portion of the total power budget.
Various techniques are proposed in [13]- [15], [34]- [36] to reduce the power consumption in passive mixer-first receivers. The mixer-first receiver in [15] uses a noise-power optimized multi-path current-reused baseband amplifier. An RF-to-BB current-reuse technique is proposed in [34] to reduce the power consumption in N-phase mixerfirst receivers. [14] proposed a low-power blockertolerant receiver with a gain-boosted mixer-first topology.
An optimized supply voltage is used to reduce the power consumption in the mixer-first receiver that is demonstrated in [35]. [13] proposed a low-power gain-boosted N-path mixer-first receiver with switched BB extraction. [36] proposed a passive mixer-first low-power wake-up-receiver using a ring-based local oscillator (LO). Overall, the inband (IB) linearity of low-power mixer-first receivers demonstrated in [13]- [15], [34]- [36] is lower than that of the high-linearity mixer-first receivers [20], [23], [24]. Similarly, the power consumption of the high-linearity mixer-first receivers demonstrated in the literature is higher than that of the low power mixer-first receivers. The objective of the current work is to investigate a TIA topology that is suitable for a high-linearity and low power mixer-first receiver.
The shunt-feedback topology is the most commonly used TIA in mixer-first receivers. Opamp (or OTA) based shunt-feedback TIAs usually exhibit poor linearity and require an additional linearization technique, such as noiseand-distortion cancellation [40], to improve the in-band linearity. The noise-and-distortion canceling technique, which is also frequently used in the design of RF LNAs [10], [11], requires significantly high power to be dissipated in the auxiliary stage. There are not many low power linearization techniques available in the literature [41]. One particular linearization technique that requires zero additional power is the complementary derivative superposition (CDS) [41]. In this work, a capacitor-cross-coupled (CCC) complementary-common-gate (CCG) amplifier is used as a TIA. The four-transistor-TIA presented in this work achieves a high transconductance efficiency. The CDS technique is used to improve the IB linearity with no additional power overhead. The combination of CCC-CCG topology with CDS is not explored previously, even in RF low noise amplifiers [42]- [44]. In this work, the proposed TIA is used to design a frequency-agile receiver front-end working in the frequency range 0.3 − 1.3 GHz.
The rest of the paper is organized as follows. Section II presents the receiver architecture and describes the proposed baseband TIA. Analysis and design details of the implemented receiver are presented in section III and section IV, respectively. Measurement results are presented in section V. Section VI summarizes the work and concludes the paper. Fig. 2 shows the block diagram of the implemented four-phase mixer-first receiver using the CCC-CCG TIA in the baseband. In Fig. 2, R s denotes the source resistance, C sh is the shunt capacitance at the input of the TIA, and C b is an off-chip dc blocking capacitor at the RF input. The mixer switches are implemented using nMOS transistors. The mixer is dc-coupled to the TIA. The gates of the mixer transistors are biased to resolve the dc-offset problem caused by the dc-coupling. An on-chip frequency divider (/2) and a set of combinational logic circuits are used to generate the four non-overlapping LO signals (p 1 − p 4 ) required for the mixer. The design details of each of these blocks are discussed in section IV. In the next subsection, we present the analysis and working principle of the proposed baseband TIA.

A. TIA ARCHITECTURE
The low-power fully-differential complementary common gate TIA used in this work, is shown in Fig. 3(a). The four transistors M 1p,n and M 2p,n act both as common gate (CG) as well as common source (CS) amplifiers. The two nMOS transistors (M 1n , M 2n ) in Fig. 3(a) form a capacitor-crosscoupled CG pair and enhances the effective g m of each transistor by a factor of two [45]- [49]. Similarly, the two pMOS transistors (M 1p , M 2p ) form another cross-coupled CG pair. These two cross-coupled CG pairs are vertically stacked so that the dc current is reused. The pMOS and nMOS drain voltages are combined using two output capacitors C o . The output is taken differentially, as shown in Fig. 3(a). Fig. 3(b) shows the component values used in the implementation of the TIA. Let g mp and g mn represent the transconductances of pMOS and nMOS transistors, respectively. Similarly, r op and r on represent the drain-to-source resistances of pMOS and nMOS transistors, respectively. For a given differential input (v ip − v in ), the effective transconductance of the circuit can be shown to be equal to 2(g mp + g mn ), which is approximately four times more than the transconductance of a single CG amplifier biased at the same current.
For the purpose of analysis, the circuit can be folded along either the x-axis or the y-axis. Fig. 3(c) shows a reduced circuit obtained by folding the circuit along the x-axis. The transistors M 1n and M 1p from Fig. 3(a) are combined into a single transistor M 1 in Fig. 3(c), such that the transconductance of M 1 is g 1 = (g mp + g mn ). Similarly, M 2n and M 2p are combined into a single transistor M 2 . The effective load resistance at each output node of the equivalent circuit is R L /2. C x represents the effective capacitance present at the output node, where C x = (2C o C L )/(2C o + C L ) and C L is the load capacitance. The bias network, consisting of resistor R c and capacitor C c , is also scaled, as shown in Fig. 3(c). One can reduce the circuit in Fig. 3(c) further to get the single-ended equivalent version shown in Fig. 3(d). The effective transconductance of the circuit in Fig. 3 (1) VOLUME 8, 2020 The voltage gain of the circuit in Fig. 3

(d) can be obtained as
A magnitude Bode plot of the voltage gain is shown in Fig. 3(f). The mid-band voltage gain of the circuit is ≈ g 1 R L = (g mp +g mn )R L . Assuming r op , r on R L , the input impedance of the circuit in the passband can be shown to be as follows.
From equation (3), for a given input impedance, the CCC-CCG TIA requires approximately four-times smaller current compared to a single CG amplifier. This current is also much smaller than what is typically needed in a shunt-feedback TIA [23], [24].
One key advantage of the CCC-CCG TIA is the inherent linearization possibility using complementary derivative superposition [41], [43]. In the proposed TIA, the distortion is mainly caused by the nonlinear transconductance of the MOS transistors. Considering up to a third-order nonlinearity, the small-signal drain current of a MOS transistor is [50]: where g m = ∂i ds ∂v gs , g m = ∂ 2 i ds ∂v gs 2 and g m = ∂ 3 i ds ∂v gs 3 . The pMOS and nMOS drain currents are combined using two capacitors (C o ) to generate the output current as follows [41].
where g 2 = (g mp − g mn ) and g 3 = (g mp + g mn ). From the output-current expression in (4), the second-order nonlinear terms can be canceled if g mp and g mn are properly matched. Moreover, the intrinsic third-order nonlinearity of the TIA can be reduced by biasing the pMOS and nMOS transistors near the zero-crossings of g mp and g mn , respectively. More discussion on the linearization technique is presented during the linearity analysis of the receiver in section III.

III. RECEIVER ANALYSIS
In this section, we present the theoretical analysis of the receiver. Fig. 4 shows an LTI model of the proposed mixer-first receiver [25]. In Fig. 4, R sw is the on-resistance of the mixer switches, and R sh accounts for the power loss due to the up-conversion by harmonics of the LO. In the model, the shunt capacitance (C sh ) and the baseband inputimpedance (Z B ) are scaled by a factor γ [25], which is topology dependent. For a four-path mixer-first receiver, γ ≈ 0.203 and R sh ≈ 4.3(R s + R sw ) [25]. The LTI model shown in Fig. 4 is used in the following subsections to derive different performance parameters of the proposed mixer-first receiver.

A. INPUT IMPEDANCE
The input impedance of the TIA is γ Z B , where Z B = 1/(2g 1 ) (from equation (3)). Hence, the input impedance of the receiver is where ω = (ω RF − ω LO ). Typically a low resistance is chosen for the mixer switches to achieve a low noise figure.
Leaving R sw aside, the designers can vary the transconductance g 1 to achieve impedance matching at the RF input. Fig. 5(a) shows a comparison of analytical (Eq. (5)) and simulated real part of Z in with varying g 1 . In this simulation, all ideal components are used, with their values being those corresponding to the actual implementation. From Fig. 5(a), we need a transconductance of around 2 m for a ≈ 50 input impedance. Fig. 5(b) and 5(c) show a comparison of analytical (Eq. (5)) and simulated real and imaginary parts of the input impedance at 1 GHz LO frequency for three different g 1 values.

B. CONVERSION GAIN
Let R a = (R s + R sw ). The impedance seen from the baseband input node towards the mixer is From Fig. 4, the voltage at the input of the baseband TIA (v i ) can be represented as The conversion gain of a single-path of the receiver (including the source resistance) is where A v is the gain of the baseband TIA and is given by (2). Fig. 6 shows a comparison of the analytical (Eq. (6)) and simulated conversion gain of the receiver with varying g 1 . C. NOISE Fig. 7 shows all the noise sources present in the proposed mixer-first receiver. As per the receiver LTI model [25], we need to scale all the baseband components, including g 1 , by the factor γ . In Fig. 7, i n1 represents the instantaneous noise current of the baseband transconductor. The total noise voltage at the TIA output is Let v 2 n,s = 4kTR s , v 2 n,sw = 4kTR sw and v 2 n,sh = 4kTR sh represent the mean square thermal noise voltage densities of the resistors R s , R sw and R sh respectively. The output noise voltage of the receiver is VOLUME 8, 2020 From (8), the noise factor of the receiver can be derived as Fig. 8 shows a comparison of analytical (Eq. (9)) and simulated noise figures for different values of g 1 . In this work, a g 1 of 2.28 m is chosen for the implementation. This design choice ensures a good input match, a single-path conversion gain of ≈ 12 dB (including the source resistance), and an estimated NF < 4 dB.

D. LINEARITY
In general, the mixer-switches are highly linear [17], and the overall in-band linearity of a mixer-first receiver is dominated by the linearity of the baseband TIA. In the present analysis, it is assumed that the mixer switches are completely linear, and distortion is caused by the baseband transconductors only. Fig. 9 shows an in-band LTI model of the mixer-first receiver, including the nonlinear current components in the TIA. The following equation can be written using the nodal analysis on the circuit shown in Fig. 9.
Using the output current equation in (4), the output voltage can be represented as Using equations (10) and (11), the fundamental and third harmonic coefficients of the gain are Hence, the in-band input third-order intercept point (IIP3) of the receiver is In the above expression, the term 3g 2 2 in the denominator is due to the second-order interaction [41], [43]. The even-order harmonics, due to feedback, gets multiplied by the input tones to generate this distortion term. This term degrades the IIP3 because g 1 and g 3 usually have opposite signs. However, if g mp and g mn are properly matched, then g 2 is almost equal to zero. g 3 can be reduced if pMOS and nMOS transistors are appropriately biased, such that both g mp and g mn have near-zero values. Fig. 10(a) shows a comparison of simulated and analytical (Eq. (12)) IB-IIP3 of the receiver with varying g 3 . The second-order distortion coefficient (g 2 ) is assumed to be zero in the analysis shown in Fig. 10(a). Fig. 10(b) shows the effect of second-order distortion on the receiver IIP3. It is observed that the IB-IIP3 of the receiver decreases with an increase in second-order distortion. The CDS linearization technique is not effective in improving the out-of-band (OOB) IIP3 of the receiver. One can set  Fig. 3(b). |g 2 | ≈ 0 (by proper design of the transconductors) at low frequencies, but |g 2 | increases with frequency due to parasitic feedback paths [41]. Also, the optimum gate-bias voltage for a MOS transistor changes with varying input-tone frequency [51]. Hence, for a specific gate-bias voltage, the linearity improvement may not be uniform with varying input tone frequencies. Fig. 11 shows the simulated IIP3 of the designed TIA with varying input-tone frequency. The component values and the bias-voltages used in the TIA implementation are given in the following section. From Fig. 11, it is observed that the linearity performance of the TIA degrades beyond its bandwidth (which is 10 MHz in the current design).
In order to understand the effect of input tone frequency on the IIP3 of the baseband TIA, the linear {P f 1 , P f 2 } and IM3 {P (2f 1 −f 2 ) , P (2f 2 −f 1 ) } output components are plotted in Fig. 12 with varying input power and for different input tone combinations. The magnitudes of the two IM3 components are completely identical when the two input tones are in-band, as shown in Fig. 12(a) and 12(b). Even when the tones are just outside the bandwidth of the TIA, the IM3 components show good symmetry (as shown in Fig. 12(c)). However, as the tones move further away from the TIA-bandwidth, some IM3 mismatch starts to appear, as shown in Fig. 12(d). When the two input tones are within the bandwidth of the system, the even-order terms go through identical responses, and good symmetry can be observed between the higher (2f 2 −f 1 ) and lower (2f 1 − f 2 ) IM3 components [52]. However, when the input tones are out-of-band, the different even-order terms experience different amplitude and phase responses, eventually leading to the asymmetry in the IM3 components [52]. This asymmetry becomes larger as the offset between the two input tones increases [52].

IV. RECEIVER DESIGN A. DESIGN OF NON-OVERLAPPING CLOCK GENERATOR
An on-chip clock divider and a set of combinational logic circuits are used to generate the four non-overlapping clock signals p 1 − p 4 . Fig. 13 shows the gate-level schematic of the non-overlapping clock generator. An external clock signal is converted to a differential clock using an off-chip splitter  (SYPJ-2-33+) and then fed to the non-overlapping clock generating circuit. The first stage of the non-overlapping clock generator is a shunt-feedback LNA that provides a broadband input match. The high-frequency clock (at 2f LO ) is then converted to a square wave using a two-stage inverter chain and fed to the divide by two circuit. The frequency divider consists of back-to-back connected two D-latches, as shown in Fig. 13. The output of the divide by two circuit is a set of four 50% duty-cycled clocks at f LO . These 50% duty-cycled clocks are combined with the 2f LO clocks to generate the non-overlapping 25% duty-cycled clocks at f LO . A chain of inverter is used at each output of the non-overlapping clock generator to drive the mixer switches. VOLUME 8, 2020 B. MIXER DESIGN Switches of the mixer are realized using nMOS transistors. Separate biasing is applied at the gates of the nMOS transistors using a resistor of 11 k and a capacitor of 3.3 pF, as shown in Fig. 2. The gate biasing helps to overcome the dc offset present at the source nodes of mixer-switches. The size of the switches pose a trade-off between the dynamic power consumption and the noise figure of the receiver. The IIP3 of the receiver is also a strong function of the switch width below a threshold value. Fig. 14 shows the variation of noise figure and IIP3 of the mixer switches with varying gate-width in 180 nm CMOS process. Ideal TIAs are used in this simulation. A size of 120µm/0.18µm is chosen for the nMOS transistors in this implementation. From Fig. 14, the theoretical bounds defined by the mixer are NF ≥ 1.9 dB and an IIP3 of ≤ +18 dBm. Each mixer switch is followed by a shunt capacitor (C sh ) of 9 pF in the current implementation.

C. BASEBAND TIA DESIGN
The baseband TIA is the only block that consumes the static power in a mixer-first receiver. Since the objective of the current work is to design a low power mixer-first receiver, the TIA is optimized for the smallest power consumption possible. For 50 impedance matching at the RF input, we need a transconductance of ≈ 1.14 m per transistor (g 1 = 2.28 m ) in the TIA. The bias network (as shown in Fig. 3(a)) of the TIA is implemented using a resistor (R c ) of 20 k and a capacitor (C c ) of 20 pF. The drain nodes of the MOS transistors are terminated with load resistances (R L ) of 4.1 k . The pMOS and nMOS drain voltages are combined using two output capacitors (C o ) of 23 pF.
The dimensions and the biasing voltages of the transistors are chosen to optimize the linearity. In this design, nMOS transistors of (W /L) n = 30µm/0.5µm and pMOS transistors of (W /L) p = 88.5µm/0.5µm are used. Fig. 15(a), 15(b), and 15(c) show the first-order, second-order, and third-order transconductances of the nMOS and pMOS transistors used in this design. For best linearity, one has to operate the nMOS and pMOS transistors at bias voltages, which results in g mn ≈ g mp ≈ 0. One also has to ensure g mn ≈ g mp to mitigate the second-order interaction induced third-order nonlinearity. From Fig. 15, the optimum gate-to-source voltages are found to be ≈ 555 mV for nMOS and ≈ 563 mV for pMOS transistors.
The optimum gate-to-source voltage for best linearity also depends on the channel length of the transistors. Let, V zc,n and V zc,p represent the g m -zero-crossing gate-to-source voltage of the nMOS and pMOS transistor, respectively. Fig. 16(a), 16(b) shows the typical variations of g m -zero- crossing voltage and threshold voltage with varying channel length. From Fig. 16, it can be observed that V zc,n (or V zc,p ) is lower than the threshold voltage V Th,n (or V Th,p ) for small channel length devices. Therefore, one has to operate the transistors in sub-threshold in small channel-length designs for the CDS linearization technique to be effective. In general, sub-threshold operation leads to reduced bandwidth and increased noise. As a result, the implementation of the CDS linearization technique in advanced technology nodes while maintaining the required bandwidth and noise performance is a challenging task. In the present implementation, 0.5 µm channel length is chosen to avoid sub-threshold operation, and also to reduce the flicker noise.
In the proposed TIA, one can set V gs,n ≈ 555 mV and V sg,p ≈ 563 mV by different combinations of V bn and V bp values. Fig. 17(a) shows the variation of TIA IIP3 with bias voltages V bn and V bp . In the present implementation, we have chosen V bn = 1.45 V, and V bp = 0.33 V. Fig. 17(b) and 17(c) show the IIP3 variation at extreme PVT corners. From Fig. 17, the TIA can achieve high linearity performance at any given PVT condition subject to the proper selection of the bias voltages. The automatic setting of bias voltages for high IIP3 requires further research and is not explored in this work. Fig. 18 shows the distribution of TIA IIP3 under the statistical variation of process and device mismatches. The obtained

V. MEASUREMENTS
A prototype receiver is implemented in a standard 180 nm CMOS technology. The chip is enclosed in a 56-pin QFN package and mounted on an FR-4 PCB for testing. The testing PCB and the chip micrograph is shown in Fig. 19(a) and 19(b), respectively. All bias voltages (for switches and transconductors) are supplied externally. If not mentioned otherwise, the following TIA bias voltages are used in all the measurements: V bn = 1.45 V and V bp = 0.33 V. The receiver is tunable from 0.3 GHz to 1.3 GHz. Depending on the frequency of operation, the clock path consumes 21.6-75 mA of current from a 1.8 V supply voltage. Each baseband TIA consumes around 188.9 µA from a 1.8 V power supply resulting in a 0.68 mW of power consumption for the receiver (Rx). The non-overlapping clock generator consumes ≈ 100 mW/GHz from a 1.8 V supply voltage. Table 1 shows the dynamic power distribution of the non-overlapping clock generator at 1 GHz. Fig. 20 shows the measured |S11| of the receiver. The receiver has an |S11| < −15 dB and a conversion gain greater than 20 dB over the frequency range 0.3-to-1.3 GHz. Fig. 21 shows the measured conversion gain and noise figure of  the receiver at 1 GHz LO with varying IF frequency. The measured BB bandwidth is ≈ 10 MHz. The designed receiver has an almost flat noise figure for > 3 MHz IF frequency. The measured conversion gain and NF of the receiver at different LO frequencies are shown in Fig. 22. The measured NF varies from 5.7 dB to 6.3 dB over the LO frequency range 0.3-to-1.3 GHz for an IF frequency of 4 MHz. Fig. 23 shows the simulated NF of the receiver at 1 GHz LO frequency in the presence of a blocker at two different offset frequencies: f /BW = 5 and f /BW = 10. Fig. 24(a) and 24(b) show the measured receiver gain with varying bias voltage V bp and V bn , respectively.
The imbalance between the in-phase (I) and the quadrature-phase (Q) output paths are characterized using the test setup shown in Fig. 25(a). The gain and phase mismatches are estimated from the time-domain waveforms of the output signals using an oscilloscope. Fig. 25(b) shows the four output signals (I +, I −, Q+, Q−) when the LO is at 500 MHz, and the RF input is at 498 MHz. For 500 MHz LO,   the measured gain and phase errors are ≈ 0.1 dB and ≈ 3.6 • , respectively, which leads to an estimated image rejection of ≈ 30 dB [53]. Fig. 26(a) and 26(b) show the measured I/Q gain and phase errors at different LO frequencies, respectively. Between 0.4-1.1 GHz, the gain error is ≤0.5 dB, and the phase error is ≤ 5.5 • . The current implementation of the receiver does not have an I/Q calibration circuitry, which, if present, can reduce the I/Q mismatches. Fig. 27 shows the measured IB-IIP3 of the receiver at different LO frequencies. The receiver has ≈ +7.2 dBm    frequency offset from the LO frequency. The receiver has an OOB-IIP3 of 4.5 dBm at an offset of twice the band-  width. Fig. 29 shows the measured OOB-IIP3 of the receiver at 1 GHz LO frequency for varying f /BW . Similarly, OOB-IIP3 points are measured at various LO frequencies for a fixed frequency offset f /BW = 2. Fig. 30 shows the variation of OOB-IIP3 across the LO frequency range (for a f /BW = 2). Table 2 shows a comparison of this work with different mixer-first receivers reported in the literature. The IB-IIP3 of the proposed receiver is on par with the high-linearity mixerfirst receivers and much better than the low-power mixerfirst receivers or noise-canceling mixer-first receivers. The clock power consumption of the proposed receiver is slightly on a higher side, but can be significantly reduced if implemented in an advanced CMOS process (because of reduced parasitic capacitances in an advanced CMOS process). Although [12], [20] achieve a better noise figure by employing the RF noise-canceling technique, their Rx power consumption is much higher than the proposed work. The proposed receiver has achieved a wider frequency tuning range with similar noise performance as compared to  recent discrete-time mixer-first receivers [16], [22]. Overall, the mixer-first receiver presented in this work achieved a good in-band SFDR while consuming the lowest Rx power.

VI. CONCLUSION
In this paper, we have demonstrated a four-phase passive mixer-first receiver with a low-power complementary common-gate TIA. The TIA is designed to exploit cross-coupled g m -boosting along with complementary derivative superposition linearization. The receiver presented in this work has achieved an NF of 5.8 dB and an IB-IIP3 of +7.2 dBm with the lowest power consumption of 0.68 mW for baseband circuitry. Overall, the receiver achieved a measured IB-SFDR of 76.9 dB at 1 GHz.