Evaluation Model of Loop Stray Parameters for Energy Storage Converter of Hybrid Electric Locomotive

When the silicon carbide (SiC) power module is applied to the energy storage converter of a hybrid locomotive, under the action of di/dt and loop stray inductance, it is easy to produce excessively high voltage overshoot, which affects the battery life and stimulates high-frequency oscillations, causing power devices to withstand greater electrical stress. In order to optimize the system layout and improve system performance, it is extremely necessary to accurately extract and evaluate the loop inductance. This paper takes the typical high-frequency converter structure as the object, establishes an equivalent model of the circuit, and quantitatively analyzes the loop inductance from a mathematical point of view. For the circuit after the parallel of absorption capacitor, the small signal model is used to analyze and reveal the role and influence of the absorption capacitor. Finally, the calculation results of the model are compared through a double-pulse experiment. The results show that the error between the model and the experimental results is about 1%, and the effect of evaluating the stray parameters of the converter circuit is good, and it can provide a theoretical support for the selection and design of the absorption capacitor.


I. INTRODUCTION
Bidirectional DC/DC converters are widely used in energy storage converters of hybrid locomotive, connecting power batteries or super capacitors as auxiliary power [1], [2]. With the development of power electronic devices, reducing volume, reducing cost and improving reliability have become research hotspots. Silicon carbide (SiC) devices have the characteristics of high thermal conductivity, fast switching speed and high blocking voltage [3]. Power electronic devices based on SiC modules solve the contradiction between high converter operating voltage and low power module withstand voltage, and also greatly increase the switching frequency of the converter and reduce the volume of the output filter devic [4], [5], which has extremely broad potential in the application of energy storage converters for hybrid locomotives.
The associate editor coordinating the review of this manuscript and approving it for publication was Yijie Wang .
Under the high-frequency and high-voltage working environment, the action of SiC MOSFET switching momentary excessive di/dt and loop inductance will induce higher electrical stress and reduce battery life. In addition, high-order harmonics are generated, which affects the performance of the system, and may also cause problems such as switching losses [6], electromagnetic interference [7], and noise pollution [8], and even endanger the normal operation of the system in severe cases. In order to implement targeted suppression measures, it is extremely necessary to accurately extract and evaluate the stray inductance of the power loop.
Loop inductance mainly includes device parasitic inductance, stray inductance of connecting parts and bus capacitance parasitic inductance [9]- [11], etc. Existing literature researches on the extraction method of stray inductance are mostly for laminated busbars. Literature [12] sorts out the transient process of turn-on and turn-off, and finds the most favorable stage for the extraction of stray inductance, combining the method of integral operation to extract the stray VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ inductance. Literature [13] studies the laminated busbar of the five-level converter module, and tests the proposed method by comparing simulation and experiment. Reference [14] improves the traditional integration method by considering stray resistance and measurement offset, and improves the calculation accuracy. Literature [15] proposes to use the oscillation frequency during the turn-on and turn-off process to extract the loop inductance by analyzing the switching transient process of SiC MOSFET, which improves the accuracy. Although many literatures have proposed the optimization of the extraction method of stray inductance, most of the analysis is to improve the accuracy of the experimental extraction method from the analysis of the transient process of the device switching. The mathematical quantitative analysis of the power loop stray parameter model is not performed. In order to enrich the theoretical basis and reduce the test cost, based on the previous research, this paper takes the bidirectional DC/DC converter based on SiC power module as the object, and establishes the stray parameter mathematical model of the power loop in sections. We quantitatively calculate the stray inductance of each part of the loop, and evaluate the proportion and influence of each section of stray parameters in the power loop. Finally, a double-pulse experiment is conducted to verify the accuracy of the theoretical analysis and the applicability of the evaluation model. Figure 1(a) is the main circuit diagram of the bidirectional DC/DC converter, including support capacitor C dc , support capacitor parasitic inductance L dc , stacked bus bar L bus , parallel SiC power module, filter inductor L b and filter capacitor C b , L d1 is SiC module parasitic inductance. This article takes the typical structure of the DC/DC converter shown in Figure 1(b) as the object, and builds the test platform shown in Figure 1(c) to extract the stray inductance of the converter power loop. Including DC voltage V DC , support capacitance C dc1 , C dc2 , support capacitance parasitic inductance L dc1 , L dc2 , laminated bus bar L bus , load inductance L load and DUT.

II. EXPERIMENTAL PLATFORM BASED ON SiC MOSFET
The device under test is selected from Cree's CAS300M17BM2 half-bridge power module. The support capacitor and the power module are connected by a busbar. The busbar adopts a laminated structure, and the current between the positive and negative plates is reversed, which makes the magnetic field cancel and the busbar inductance reduced. In order to further reduce the loop inductance, absorption capacitors can be connected in parallel at the positive and negative ports of the power device. The absorption capacitor, the support capacitor and the power device are connected to the bus bar through bolts. The DC input terminal is supported by two supporting capacitors in parallel; during the test, the two ends of the upper tube gate source are turned off by applying negative pressure.
The test method is the traditional double-pulse test method. Figure 2 shows the timing diagram of the double-pulse test. After the device under test is pressurized to stability, at time t 0 , the SiC MOSFET is turned on for the first time, and the drain current rises; At the first turn-off at time t 1 , the current change rate di/dt acts on the loop stray inductance and forms a voltage spike at both ends of the device after being superimposed with the bus voltage; At time t 2 , the device is turned on for the second time, and the reverse parallel diode of the upper tube reversely recovers, resulting in an overshoot of the drain current; at t 3 , the device is turned off, and a large voltage overshoot is formed again across the device under test. At this moment, the current change rate changes significantly, and the SiC junction capacitance has little effect, which is suitable for the extraction of stray parameters.

III. MODEL OF CONVERTER CIRCUIT CONSIDERING PARASITIC PARAMETERS
The converter circuit includes four parts as shown in Figure 3: support capacitor, laminated busbar, absorption capacitor and power module. The parasitic inductance of the power module can be obtained from the data sheet. This article mainly analyzes the other three parts.

A. SUPPORT CAPACITANCE PARASITIC INDUCTANCE
The wide-band characteristic of the support capacitor is characterized by an RLC circuit, where R dc1 , C dc1 , and L dc1 are the stray resistance, main capacitance, and parasitic inductance of the support capacitor, respectively. Single support capacitors are directly connected in series by RLC. In this paper, two support capacitors are connected in parallel as an example for analysis. The equivalent circuit is shown in Figure 4.
Before the test process, first charge the supporting capacitor. Therefore, the positive electrodes of C dc1 and C dc2 are equipotential points. Equations (1)∼(3) give the parameter values of each element in the process of equivalent transformation. (2)

B. STRAY INDUCTANCE OF LAMINATED BUSBAR
According to the circuit structure of FIG. 1, FIG. 5 draws a schematic diagram of each stray inductance branch in the bus bar. In the figure, L 1d , L 2s , L 3d , L 4s , L pd and L ns are the inductance from C dc1 to SiC MOSFET positive electrode, from C dc1 to SiC MOSFET negative electrode, from C dc2 to SiC MOSFET positive electrode, from C dc2 to SiC MOSFET negative electrode, from DC power supply to SiC MOSFET positive electrode, from DC power supply to SiC MOS-FET negative, respectively. There is direct mutual inductance in each branch inductance. Figure 6 shows the topology of the double-pulse test circuit. v 1d , v 3d , v s4 , v s2 are the terminal voltages of L 1d , L 3d , L 2s , L 4s , respectively. The volt-ampere characteristic formula of the stacked busbar with two supporting capacitors VOLUME 8, 2020 in parallel is shown in equation (4).
In equation (4), L bus is a 4 × 4 inductance matrix, and the inductance in FIG. 6(b) can be expressed using equation (5). Decouple the two parallel coupled inductors to obtain a structure in which L 12 -M ds and L 34 -M ds are connected in parallel and then in series with M ds . The calculation formula of the two parallel coupled inductors is shown in equation (6).
For a single support capacitor loop, the model calculation formula is: In the inverter commutation circuit, the branches L pd and L ns between the DC power supply and the busbar should also be considered. Figure 7 shows the distribution of the stray inductance of each branch of the inverter commutation 212592 VOLUME 8, 2020 circuit. The analysis method is the same as that of the test platform with double supporting capacitors in parallel. According to equation (8), the inductance of the power supply branch can be obtained: For the coupled inductance of three branches in parallel, there is independence during decoupling conversion, and only one or a few of them can be decoupled. The circuit after decoupling the star-connected circuit is shown in Figure 7(c).
Due to the parasitic inductance of the supporting capacitor, the DC side ends of the three equivalent branch inductances are no longer equipotential points. The two branches connecting the support capacitor and the positive pole of the power module should be connected in series with the support capacitor first, and then in parallel with the equivalent inductance of the DC voltage branch in the laminated busbar. At this time, the equivalent inductance of the inverter commutation loop can be obtained as shown in equation (9).

C. THE FUNCTION AND INFLUENCE OF ABSORPTION CAPACITOR
After absorbing capacitors in parallel, the overvoltage phenomenon caused by stray inductance can be suppressed, but at the same time, the circuit structure is changed, making the circuit into a higher-order system, and it is difficult to obtain an analytical expression using time-domain analysis. This paper analyzes the circuit using the small-signal model of SiC MOSFET in the complex frequency domain. SiC MOSFTE is approximately a constant current source with a certain increase. According to the principles of DC current source open circuit and voltage source short circuit, Figure 8 shows the small signal equivalent model of the test platform. The expression of loop inductance is: According to the equivalent circuit, the input admittance of the circuit is: When the imaginary part is 0, the circuit resonates. Therefore, the resonance condition of the circuit is: The resonance frequency is: In order to ensure that the circuit resonates, it should be guaranteed R dc < (L loop /C oss ) 1/2 . When R dc (L loop /C oss ) 1/2 , the resonance frequency of the circuit is approximately: At this time, the circuit is approximately GCL parallel, and its equivalent admittance is: The loop impedance is: The closer the absorption capacitor is to the SiC module, the better the absorption effect. Figure 9 is a test platform circuit and its equivalent model of parallel absorption capacitors.
After the parallel absorption capacitor, during the switching process, the support capacitor will first charge the absorption capacitor, and then the absorption capacitor will discharge to the power module, so Figure 9(a) can be equivalent to Figure 9(b). According to the foregoing, when the absorption capacitor is close to the port of the power module, selecting an absorption capacitor with a sufficient value can completely absorb the voltage spike introduced by the parasitic inductance of the support capacitor and the stray inductance of the busbar, but at the same time, it will introduce parasitic inductance of the absorption capacitor.
When the voltage spikes caused by L dc and L bus are completely absorbed, the resonance impedance of L dc , L bus VOLUME 8, 2020 and the absorption capacitor is much smaller than the L stray impedance at the resonance frequency.
Simultaneous (17) and (18): In addition, the absorption capacitor is connected in parallel at both ends of the device. After complete absorption, only the absorption capacitor parasitic inductance L snub and power device stray inductance L stray are in the loop. Therefore, the selection of the absorption capacitor is based on the two principles of capacitance and parasitic inductance. When L snub < L stray /10, the influence of L snub can be ignored, so the requirement for its parasitic inductance when selecting the absorption capacitor is L sn = nL snub , L sn is the parasitic inductance of a single absorption capacitor, n is the number of parallel absorption capacitors.
At this time, the loop stray inductance is:

IV. STRAY PARAMERER EXTRACTION BASED ON CALCULATION MODEL AND Q3D
The stray parameters include four parts: supporting capacitance parasitic inductance, stacked busbar stray inductance, absorption capacitance parasitic inductance and power module parasitic inductance. Two supporting capacitors are connected in parallel and three absorption capacitors are connected in parallel. The parameters in the analysis model are shown in Table 1. According to formula (1) ∼ formula (3), the supporting capacitance parasitic inductance L dc can be calculated as 20nH; The inductance of the laminated busbar is composed of mutual inductance and self-inductance. Figure 10 shows the busbar model built in Q3D software according to Figure (1 The principle of applying the excitation source is based on the actual test. For example, the supporting capacitor and power device are connected to the busbar with bolts, so the excitation source can be applied to the corresponding screw hole of the positive and negative busbars, and the simulation step and frequency are set according to the double pulse test time. After the inductance of each branch is obtained, calculation is performed according to equation (7), and the result is 25.1 nH. The parasitic inductance of the power device is obtained from the data sheet. According to equation (10), the loop inductance of the test platform can be obtained as 60.1nH.

V. EXPERIMENTAL EXTRACTION AND VERIFICATION OF STRAY PARAMETERS
Build a dual-pulse test platform based on the dual-pulse test schematic shown in Figure 1(b), and extract the stray  inductance of each part of the power loop according to the waveform of the SiC MOSFET module off process.

A. STRAY PARAMETERS WITHOUT ABSORPTION CAPACITANCE
Select the positive-negative port, output-negative (down tube DS) and supporting capacitor port of the power module as the voltage test points to obtain the experiment waveform of voltage V DS across the lower tube of the SiC MOSFET, the power module terminal voltage V pn , the supporting capacitor terminal voltage V dc and the drain current I d , which is shown in Figure 11.
1) The stray inductance of the power loop is extracted according to the relationship between the volt-ampere characteristics of the inductor given by equation (22).
Among them, V Rdc is the voltage drop of the stray resistance.
Similarly, equation (24) gives the calculation formulas for the supporting capacitance parasitic inductance and the stray inductance of the laminated busbar.

B. STRAY PARAMETERS AFTER PARALLEL ABSORPTION CAPACITORS
After the parallel absorption capacitors at the positive and negative ports of the power module, the experimental waveforms of the voltage V DS across the lower tube of the SiC MOSFET, the voltage V pn at the power module terminal, and the drain current I d are shown in Figure 11. Table 3 statistics the inductance values of each part after theoretical analysis and experimental measurement after parallel absorption capacitors. After the parallel absorption capacitor, the absorption capacitor absorbs the overvoltage caused by the bus capacitor and the laminated bus bar, but at the same time introduces parasitic inductance. According to the experimental results, after a 1uF absorption capacitor is connected in parallel, the loop inductance is reduced by 21.95nH, and an absorption capacitance parasitic inductance of 13.6nH is introduced at the same time.

C. COMPARATIVE ANALYSIS OF EXPERIMENTAL RESULTS AND MODELS
When there is no parallel absorption capacitor, the measured loop inductance is basically consistent with the theoretical calculation. The parasitic inductance of the supporting capacitor and the parasitic inductance of the power device are VOLUME 8, 2020  slightly larger than the theoretical value. This is due to the fact that the voltage probe is clamped on the busbar and bolts are introduced during the experimental measurement, which causes the terminal voltage generated by the busbar inductance to be small and L dc and L d too large. The equivalent inductance of the bus capacitor and the stacked busbar series is 44.1nH. After the absorption capacitor absorbs it completely, the parasitic inductance of 13.6nH is introduced, which is close to the theoretical analysis. This error is caused by the position where the probe is clamped during the measurement. Because the actual structure uses bolt connection, the probe can only be clamped inside the busbar, causing the measured value of the voltage spike at both ends of the busbar inductance to be small, and the L dc and L d ends are measured The value is too large. This is an inherent measurement error. Combined with the ANSYS Q3D simulation results of the busbar, the analysis of the error is correct and reasonable, and the measured value of the total loop inductance is consistent with the theoretical analysis, which can prove the effectiveness of the method. The existence of this error can better prove the value of the calculation model proposed in this article, because it can compensate for the inherent error of the measurement. We have further analyzed the mechanism of this error in the updated article. Table 4 makes statistics on the proportion of inductance of each part in the power loop inductance before and after the parallel absorption capacitor. The parasitic inductance of the power module is based on the measured value when there is no parallel absorption capacitor. Before the parallel absorption capacitor, the parasitic inductance of the supporting capacitor accounted for the highest proportion of 38.3%, followed by the laminated busbar, accounting for 34.5%, and the parasitic inductance of the SiC module depends on the manufacturing process. When the busbar structure is fixed, the more supporting capacitors are connected in parallel, the smaller the loop equivalent inductance value. Therefore, we can try to use more supporting capacitors in parallel to reduce the loop inductance.
After the parallel absorption capacitor, the parasitic inductance introduced by the absorption capacitor accounted for the highest proportion, and the extra stray parameters due to insufficient contact of the absorption capacitor pin and contact accounted for 23.4%. When installing the absorption capacitor, multiple capacitors with small parasitic inductance should be connected in parallel as much as possible, and the capacitor can be fully contacted with the SiC module. In addition, attention should be paid to the parasitic inductance of the capacitor pin when selecting.

VI. CONCLUSION
In this paper, based on the SiC module-based hybrid locomotive energy storage converter converter circuit, a loop stray parameter evaluation model is established, and the stray inductance of each part of the power circuit is quantitatively calculated from a mathematical point of view. Firstly, the distribution of loop stray inductance is analyzed, and then the mathematical model of supporting capacitance equivalent circuit and laminated busbar considering the self-inductance and mutual inductance of the branch is established, and the effect of the absorption capacitance on the converter circuit is revealed through the small signal model. And influence. Finally, the results of model calculation and experiment extraction are compared to verify the accuracy and practicability of the model. The model can be used to calculate the power loop inductance of the converter in sections, clarify the distribution of stray parameters in the loop, and provide strong support for further optimization of the system structure layout. The model is still applicable to other similar topologies.
YUNXIN FAN (Member, IEEE) is currently the Director of the State Key Laboratory of Heavy Duty AC Drive Electric Locomotive Systems Integration. He is also a Professor Level Senior Engineer. He was selected into the second batch of national ten thousand talents program leading talents, in 2016. He has been committed to the research and development of rail transit traction power equipment technology, and has made outstanding contributions to the research and development of heavy haul traction equipment and the mastery of key technologies, the upgrading of passenger rail transit equipment and the research and development of high-end equipment. His current research interests include theory of rail transit electrical traction systems and optimization of energy matching strategy for hybrid locomotive. Integration. His current research interests include simulation theory of rail transit electrical traction systems, optimization algorithm of energy matching strategy for hybrid locomotive, and high-performance auxiliary system of urban rail vehicles.
XIAOYU REN received the B.Eng. degree in electrical engineering and automation from Xinjiang University, in 2018. He is currently pursuing the master's degree in power electronic and ac drives with Beijing Jiaotong University. His research interests include energy management strategies, heterogeneous multi-power drive systems (HMDS), and power electronic drive.
CHUNMEI XU received the Ph.D. degree in control theory and control engineering from Beihang University, Beijing, China, in 2004. She was an Associate Professor and a Graduate Supervisor of the School of Electrical Engineering, Beijing Jiaotong University. From August 2014 to August 2015, she was an Academic Visitor of the University of Wisconsin Madison. Her major research interests include control theory and its applications, including intelligent control, predictive control, servo system control, and control of traction drive system for urban mass transit.