79 GHz Active Array FMCW Radar System on Low-Cost FR-4 Substrates

This work, for the first time to our best knowledge, presents a W-band multi-channel frequency-modulated continuous-wave (FMCW) radar system on low-cost FR-4 substrates. A center-fed patch array antenna on an FR-4 substrate can achieve a maximum gain of 10.8 dBi. It is enabled by aperture coupled feeding using an on-chip feeder implemented on a CMOS radar transmitter (Tx) and receiver (Rx). The proposed radar system consists of one Tx and four Rx channels placed in the back cavity of a microstrip array antenna like an active array antenna system. Additionally, Tx and Rx chipsets include a wideband frequency multiplier with high multiplication ratio of 63, making it easy to distribute reference FMCW waveform synthesized at a very low frequency about 1.25 GHz for 79 GHz output using direct digital synthesis (DDS). Extending the number of channels and implementing various waveforms can be easily accomplished with very good phase noise. The functionality of the proposed radar system on low-cost substrates is confirmed by distance and angle measurements.


I. INTRODUCTION
The use of mm-wave radars for civil and commercial applications has increased due to improvements of low-cost silicon semiconductor technology with mass production capability and good yield. One of the mm-wave radar sensor applications is the advanced driver-assistance system (ADAS) in vehicles. The mm-wave front-end of an ADAS radar sensor requires high performance, high density integration, and low manufacturing cost. Early-stage commercialization of The associate editor coordinating the review of this manuscript and approving it for publication was Dušan Grujić . a car radar sensor was initiated by SiGe technology. However, recent market is moving toward CMOS technology that shows a higher level of integration at a more competitive price than SiGe technology [1], [2]. Additionally, CMOS radar transceiver designs are continuously progressing to implement high-resolution imaging radars to support complete autonomous driving [3]. In addition to mm-wave semiconductor technologies, mm-wave packaging technology is also essential for the overall performance, cost, and yield of a product. Traditional metallic packaging composed of waveguides, antennas, and cavities has been an unbeatable solution due to its low-loss nature and high-power capability. However, due to its bulky volume, heavy weight, inconvenient interface from chip-to-package, and high manufacturing cost, recent mm-wave packaging for small power applications up to W-band adopts a planar technology utilizing low-loss substrates and flip-chip bonding. Flip-chip bonding for chip-to-board inter-connection shows lower loss and better matching performance than low-cost wire bonding. However, it requires more complicated and expensive processes. Additionally, it is almost impossible to repair a flip-chip bonded system, which could be a problem for massive channel radars. While the mass production capability and continuous scaling of CMOS technology enable gradual cost reduction of active components, the cost for low-loss substrates and its packaging process are marginally decreasing. These packaging issues will become more prominent as the number of radar transceiver channels increases for high resolution.
Compared to a low-loss substrate for mm-wave applications such as liquid-crystal polymers [4], ceramics, and RT/Duriod [5], a low-cost FR-4 substrate has not been an option to implement mm-wave front-end systems. FR-4 substrate has good mechanical and electrical properties. It has been widely used in consumer electronics. However, the loss tangent of FR-4 is about 0.02, which is too high to design mm-wave high gain antennas and low-loss feeding networks. Instead, a modern approach is to laminate low-loss substrates on an FR-4 printed circuit board (PCB). The former is used to form antenna arrays and feeding networks, and the latter is to integrate baseband analog and digital circuits. Even for hybrid stacked PCBs, using a single low-loss layer is preferred in terms of cost and yield [6]. Therefore, recent planar radar systems mount multi-channel transceivers on the same layer on which an antenna array is formed. Therefore, end feeding of series microstrip arrays is unavoidable. When FR-4 substrates are used to implement multi-channel microstrip array antennas, end feeding of series arrays can cause a huge loss due to a long-distance signal distribution network. A 60 GHz mm-wave antenna system on an FR-4 substrate has been proposed in [7]. However, an additional process is required to form the air cavity and a feed line loss is inevitable. A solution to reduce feed line losses on the FR-4 substrate in W-band is to use active antenna arrays [8] where the antenna should be directly fed by active components as close as possible.
This work presents a 79 GHz multi-channel FMCW radar system implemented on FR-4 substrates as shown in Fig. 1. The series patch array antenna on FR-4 substrate is directly fed from the backside through aperture coupling by on-chip feeders on Tx and Rx chips developed in the previous work [5]. These Tx and Rx chips are newly developed for high-ratio frequency multiplication and wideband operation using a 65-nm low-power (LP) RF CMOS process. This paper is organized as follows. Section II describes design details of 79 GHz Tx and Rx chipsets. Section III shows design optimization of center-fed patch antenna arrays and feeding structure on FR-4 substrates. In section IV, implementation of the 1-Tx and 4-Rx FMCW radar system is described.
Section V demonstrates measurement results of antenna gain and radar detection capability. Section VI concludes this paper.

II. CIRCUIT DESIGN
Radar Tx and Rx chips are designed using a 65-nm LP CMOS process with 1-poly 9-metal layers. Their architectures are shown in Fig. 1, similar to those of the previous works [5], [9]. However, all circuit blocks, including a low noise amplifier (LNA), power amplifier (PA), and frequency multiplier, have been newly designed for a wide bandwidth of 5 GHz. Especially, the frequency multiplier has been completely redesigned for low power operation with a high multiplication ratio and a wide bandwidth. Details of each circuit block design are explained in the following.

A. FREQUENCY MULTIPLIER
Since the FMCW reference signal is the highest frequency delivered on FR-4 substrates, its frequency should be made as low as possible for good signal integrity and low power delivery, especially for massive array radars. Theoretically, the first N-push multiplier in the multiplier chain can make any high multiplication ratio. However, practically it is limited due to the reference spur around 79 GHz output, which appears closer and stronger as the multiplication ratio increases. Therefore, a seven-push multiplier is chosen considering the tolerable reference spur. Additionally, since the DDS (Analog devices AD9914) used in this study can generate signals up to 1.4 GHz, the total multiplication ratio should be larger than 58 times to generate a 79 GHz signal output. Therefore, the total multiplication ratio is designed as 63 times using two triplers after a seven-push multiplier. Using DDS instead of phase-locked loops (PLLs) ensures good phase noise and high linearity.
The multiplier chain shown in Fig. 2 is composed of a ring oscillator (OSC) based seven-push multiplier and two  mixer-based triplers. Due to the high multiplication ratio amounting to 63 times, the reference input frequency for the final output frequency around 79 GHz is merely about 1.26 GHz. Fig. 3 shows the ×7 multiplier which is composed of a single-to-differential (STD) converter, a seven-phase injection-locked ring OSC with pulse generators, and a seven-push frequency adder. The current starved seven-phase ring OSC is running around 1.26 GHz and locked by an external reference input signal. A single-ended external reference signal is injected through the STD into one of ring OSC cells. Seven differential signals are generated with a phase offset of 2π /7 by these ring cells. If seven-phase signals are ideally combined in the current domain at the adder output, the 7 th harmonic and its odd multiples will survive and lower order harmonics are suppressed [10].
Although the operation of the seven-push multiplier is similar to that of the previous work [11], this work newly adds pulse generators to reduce power consumption. In the previous work, the adder was driven by 50% duty pulse directly buffered from the ring OSC [5]. It consumes a lot of currents because every common source (CS) field-effect transistor (FET) in the adder carries the current during the half period of the reference signal with a little phase offset. If narrow pulses drive CS FETs in the adder without signal overlap, the total current consumption is as small as a single CS FET pair of the 50% duty cycle. The pulse is generated using a delay cell and XOR gate. The pulse width is carefully adjusted to maximize the 7 th harmonic of the reference frequency. A simple Fourier analysis shows that the optimum delay is half period of the 7 th harmonic frequency. The adder output drives the injection-locked OSC to enhance the output signal swing. The negative resistance strength of the OSC is adjusted for the wideband locking range. Simulation results show that current consumption is reduced by 70% compared to the previous work by adopting narrow pulses. Total power consumption of the ×7 multiplier is 22.8 mW from a 1.2V supply.
The next two stages after the ×7 multiplier are mixer based triplers. Fig. 4(a) shows a conventional sub-harmonic mixer-based tripler composed of a switching stage and a frequency doubler at the tail. In a conventional structure, the 3 rd order harmonic current at the mixer output gets very small if two input signals V 11 and V 12 in Fig. 4(a) are in phase and maximized if the phase difference between two input voltages is around 90 • [12], [13]. To enhance the 3 rd harmonic output, the conventional mixer based tripler requires a quadrature signal. However, quadrature generation in the mm-wave range requires many resources and becomes more difficult as the frequency gets higher. Therefore, it is not easy to cascade conventional triplers for a high multiplication ratio because both stages require quadrature generation for high output swings. This work separates the frequency doubler as shown in Fig. 4(b) to maximize the 3 rd harmonic component without a quadrature signal. The output signal 2ω 0 of the separate push-push doubler using M N 1 , M N 2 is applied to the transconductance stage M N 3 of the mixer. According to the previous study [12], the required phase shift in I 2B with respect to the phase of the fundamental frequency ω 0 at V 11 is 180 • . In the tripler, due to the transconductance stage M N 3 , the 2ω 0 signal experiences a 180 • phase shift in I 2B . Fig. 5 shows simulation results of the normalized 3 rd order harmonic current of I 2T at the mixer output according to the change of phase difference between two input voltages  V 21 and V 22 of the second tripler operating with 79 GHz output. As expected, the level of the 3 rd harmonic signal is maximized when the phase offset between two input signals is near 0 • or, 180 • instead of 90 • or, 270 • for the conventional tripler. The injection-locked OSC at the mixer output reduces unwanted harmonic signals and enhances signal swing. Fig. 6 shows Tx schematic, including the on-chip monopole feeder, which consists of a ×63 frequency multiplier and a three-stage PA. Each stage of the PA has a differential CS amplifier using cross-coupled neutralization to increase gain and stability [14]. For broadband operation, impedance matching at each stage is performed with frequency staggering. Based on the simulations, the peak gain is 15.8 dB and the saturated output power is 11 dBm. The 3 dB bandwidth is from 74 to 83 GHz. Fig. 7 shows Rx schematic including an on-chip monopole feeder. The Rx is composed of a LNA, a single balanced passive mixer, and a ×63 frequency multiplier. The LNA is designed with sufficient gain using four-stage CS amplifiers to suppress flicker noise of the mixer and baseband circuits. Similar to PA, a cross-coupled neutralization technique is used to increase gain and stability. Impedance matching of the LNA uses a concentric transformer and a balancing capacitor (C 1 , C 2 ) at the input and output to suppress the common mode. A differential common-gate amplifier using pMOS FETs is used to ensure low input impedance for the operation of the current mode mixer. Die micrographs of fabricated Tx and Rx chips are shown in Fig. 8. Chip sizes of Tx and Rx are 0.8 mm × 2.4 mm and 0.9 mm × 2.5 mm, respectively.

C. TX AND RX MEASUREMENT RESULTS
Tx and Rx chips with RF pads were fabricated separately to evaluate chip performance using on-wafer probing. A reference input signal of 0 dBm from the signal generator (Keysight N5173B) is applied to the multiplier input of Tx and Rx chips. Fig. 9 shows simulation and on-wafer measurement results of the Tx output power. The measured maximum output power is 10.93 dBm at 78.75 GHz. The output power above 10 dBm is observed in the frequency-locked range from 77 GHz to 82 GHz. As shown in Fig. 10, phase noise of the 78.75 GHz Tx output is -97.91 dBc/Hz at 1 MHz offset for the reference signal of 1.25 GHz with -135.89 dBc/Hz phase noise at the same offset. The phase noise degradation is 37.98 dB, which is close to the amount of the theoretical degradation of 35.9 dB. Spurs of the output signal were investigated with a PXA signal analyzer (Keysight N9030A) and a W-band harmonic mixer (Keysight 11970W). Spurious tones around the 79 GHz output signal exist with a tone spacing of the reference frequency, but the reference spur suppression is more than 30 dBc. The DC power consumption of the Tx is 217 mW.
The conversion gain of the Rx chip was measured by applying W-band signal available from a vector network analyzer (VNA: Anritsu MS4647A, 7379B). IF signal output was analyzed using a spectrum analyzer. As shown in Fig. 11, the conversion gain has a peak of 30.1 dB at 78.75 GHz and a 3 dB bandwidth of 77.5 to 82 GHz. Rx noise figure (NF) was roughly estimated using the spectrum analyzer as in the previous work [5]. The measured NF is 13 dB at 1 MHz IF signal. The DC power consumption of the single-channel Rx is 154 mW from a 1.2 V supply.

III. SLOT COUPLED SERIES MICROSTRIP ARRAY ANTENNA ON FR-4 SUBSTRATE
In this work, an aperture coupled microstrip array antenna is implemented on FR-4 substrates, where the center patch is fed VOLUME 8, 2020   by an on-chip feeder on a silicon chip as shown in Fig. 12. The on-chip feeder in Fig. 12 was originally developed for vertical interconnect from the silicon chip to the transmission line on RT/Duriod 5880 without using conductive bonding techniques or thru vias. The center patch of the microstrip array is driven through the slot which is formed on the backside ground plane of the microstrip array as shown in Fig. 13. By attaching Tx or Rx chip directly to the center slot of each array, a long feeding network can be eliminated to avoid huge losses of FR-4 substrates.
In Fig. 13, the microstrip antenna array is composed of the center patch fed by slot and the off-center patches fed First, the transmission line section is simulated using ANSYS HFSS to examine attenuation characteristics of transmission lines depending on the thickness of FR-4 substrate. Since the available thickness of the FR-4 substrate from a standard low-cost PCB process is limited to 0.2 mm, three different thicknesses having the multiple of 0.2 mm are evaluated. Simulation results are summarized in Table 1     and the high impedance line on the thinner substrate showed less loss. The overall gain of the center-fed array antenna is determined by combining the gain of the series patch and the  center patch antennas. Table 2 shows gain change of the slot coupled center patch antenna fed by the on-chip feeder and the edge-fed patch antenna with a λ/2 transmission line in the series array according to the thickness of the substrate. It is found in the simulation that the gain and pattern of the single patch antenna show large variations depending on the size of the ground plane and the thickness. In particular, for the edge-fed patch antenna, the elevation pattern is greatly affected by the length of the ground plane due to the surface wave mode. It is known that an FR-4 substrate with a high thickness and dielectric constant is very vulnerable to surface wave mode generation [15]. Therefore, when evaluating single antenna gain for comparison as shown in Table 2, the size of the ground plane is optimized for the best gain. According to simulation results, a thinner substrate is better for high gain patch antenna suppressing the surface wave mode. However, as seen in Table 2 and Fig. 14, the center patch antenna fed by the slot shows better gain with the substrate of 0.4 mm thickness than 0.2 mm thickness. It is very beneficial for overall gain because the series edge-fed patch antennas suffer from severe attenuation along feeding transmission lines. Additionally, since Tx and Rx chips are directly attached to the antenna ground plane, mechanical rigidness is also important. Therefore, the substrate with thickness of 0.4 mm was used to form the antenna array. Fig. 15 shows the gain of the center fed series array with the number of patch array elements on the FR-4 substrate with 0.4 mm thickness and it is found that the antenna gain of the array with more than seven elements does not increase due to feeding line losses.   The benefit of a center-fed patch array is that the degradation of the elevation pattern due to the surface wave mode is marginal because it is gradually and symmetrically attenuated along the axis of the antenna. Therefore, edge diffraction at the antenna boundary is negligible. Additionally, the center-fed array antenna is beneficial for a wideband system because the end feeding of the series array is annoyed by the gradual beam tilting as frequency changes. While the center feeding using transmission lines requires an additional 180 • phase shifting section [16] or coupled line sections [15] for differential mode antenna operation, the aperture coupling beneath the center patch can inherently feed the series array in a differential mode. Fig. 16 shows E-field distribution at radiating edges of the slot coupled center patch antenna. It confirms that E-field distribution is successfully phase-reversed to feed upper and lower series arrays in a differential mode.

IV. PACKAGING AND INTEGRATION OF MULTI-CHANNEL RADAR SYSTEM
This section discusses the implementation of a multi-channel radar system on FR-4 substrates. An exploded view of the radar RF board is shown in Fig. 17. The radar RF board  uses four layers of FR-4 substrates. The patch array antenna designed in Section III is formed on the bottom side of the L1 layer, which is the lowest substrate in Fig. 17. As discussed in [9], Tx and Rx chips are thinned to 50 µm to lower substrate losses. They are mounted on the top surface of the L1 layer aligned with slots, which are formed on the ground plane of the center patch of the series array. Attaching chips to slots, alignment between the ground open stub and the slot should be controlled within 50 µm to keep gain degradation less than 0.2 dB. The second layer L2 is the interfacing layer with two rectangular holes in which 1-Tx and 4-Rx chips are placed. Chip pads are ball-bonded to bonding pads on the top surface of the L2 layer which is closely placed to the sidewall of rectangular holes. Pads on the L2 layer are interconnected to subsequent baseband circuit blocks such as programmable gain amplifiers (PGAs), bias lines, and the reference LO signal.
In addition, the L2 layer forms the back cavity for Tx and Rx chips together with the L3 and L4 layers to suppress backlobes and encapsulate chips for protection. The L3 layer has longer rectangular holes than the L2 layer to secure the space for bonding wires and their landing spots in the L2 layer. When the on-chip feeder feeds the waveguide, the short plane of the back cavity is placed at a quarter-wave distance about 1 mm to reflect the backward wave [9]. However, in the proposed planar integration, the field from the feeder is tightly coupled to the FR-4 substrate underneath the slot due to its high dielectric constant. Therefore, unlike waveguide applications, input matching is not so sensitive to the height of the back cavity. Simulation results for various heights from 0.4 mm to 1.6 mm of the back cavity show little change of input matching. The total thickness of the L2 and L3 layers is determined to be 1.6 mm safely considering the  height of bonding wires, but it can be reduced even less than a quarter-wave length if low profile bonding techniques are available.
Internal sidewalls of these rectangular holes in L2 and L3 layers and both sides of the L4 layer are gold-plated to electrically shield the cavities for Tx and Rx chips. The spacing between 4-Rx's is λ/2. Tx and Rx antennas are separated as far as 9.5λ with guard vias to reduce interference from the Tx to the Rx generated by surface wave modes. Thicknesses of FR-4 substrates are 0.4 mm, 0.8 mm, 0.8 mm, and 0.4 mm for L1, L2, L3, and L4 layers, respectively. These FR-4 substrates are laminated using non-conductive epoxy (STYCAST A312-20). Fig. 18 shows the manufactured 1-Tx in (a) and 4-Rx radar board in (b). Fig. 19 shows simulation results of return losses seen from the feeding point of on-chip feeders of Rx chips in the cavity  of the radar board. It is confirmed that most of the signal from the on-chip feeder around 79 GHz is transferred to the antenna array on the board. Asymmetry of return losses between Rx-1,4 and Rx-2,3 seems to be due to different boundary conditions for surface wave modes. In addition, isolation between 4-Rx channels is better than 30 dB based on simulation results. Fig. 20 shows E-field distribution on the FR-4 radar and the surface wave mode is found along the H-plane in the FR-4 substrate. However, it is effectively suppressed beyond surrounding vias. Mutual coupling between Tx and Rx is negligible. Based on simulation results, the isolation between the Tx and Rx's is better than 100 dB at 79 GHz, which is sufficient to prevent Tx leakage to Rx. Fig. 21 is the antenna gain simulation results of 4-Rx channels. Due to asymmetric boundaries seen from each antenna and surface wave modes, gains and sidelobe levels of four receiving channel are slightly different. However, the main lobe gain shows variations less than 1 dB and the overall performance of the radar system is not severely deteriorated. Fig. 22 shows the backend board that contains a micro-controller unit (MCU: STM 32F303RE), a DDS, a PLL, and a voltage-controlled oscillator (VCO). The DDS generates various modulated waveforms below 1.4 GHz for a system clock of 3.5 GHz. The DDS system clock is made using PLL (Analog devices AD4159) and VCO (Crystek CVCO55CCQ-3500-3500). Since the DDS output has many unwanted spurs, a band-pass filter (Mini circuit VOLUME 8, 2020 ZX75BP-1250+) is used to suppress these spurs. The MCU controls the DDS and PLL and samples IF data using internal 4-channel ADCs. Fig. 23(a) shows a setup for gain measurements. The setup has transmitting and receiving antennas and a rotating positioner. A comparison method is used to determine the gain of the proposed center-fed microstrip array antenna of the Tx on the radar board. The receiving antenna is a standard horn antenna with a 24 dBi gain. Received power is measured using a W-band harmonic mixer and a spectrum analyzer. The aperture plane of the receiving antenna is 75 cm away from the transmitting antenna mounted on the rotating positioner with ±50 • change. At first, another standard horn antenna is placed at the transmitting position. It is driven by the known output power at 79 GHz available from the VNA output. The received power is recorded and verified using the Friis transmission equation. Then, the developed radar board is mounted on the transmitting position and driven by the fixed LO reference frequency for 79 GHz output. The transmitting power from the Tx chip is assumed to have the same value as the measured one shown in Fig. 9. The received power from the radar transmitter is measured and compared to that of the standard horn antenna. Figs. 23(b) and 23(c) show simulated and measured results of E-and H-plane patterns of the proposed FR-4 antennas. The measured maximum gain is 10.8 dBi and the 3 dB beamwidth is ±20 • azimuth and ±5 • elevation. It can be seen that the measured pattern at 79 GHz closely matches the simulated one. The back lobe was also measured after flipping the radar module. The measured front-to-back ratio (FBR) is 34 dB, which is similar to the simulated value of 35 dB. Compared to the previous work without a back cavity [5], the FBR is improved by approximately 23 dB. A performance comparison with published mm-wave radar systems is shown in Table 3.

B. DISTANCE MEASUREMENT RESULTS
FMCW radar operation was measured using a 500 µs triangular waveform from 80.64 to 81.9 GHz by activating the DDS.  Fig. 24(a) shows an outdoor measurement setup for range detection. The proposed radar system was installed at a height of 80 cm from the ground and a trihedral corner reflector (SAGE Millimeter SAJ-043-S1) with a radar cross-section of 10.4 dBsm at 80 GHz was used as a target. Fig. 24(b) shows echo signals from the target and environment clutters. The target was identified by moving its location and observing the corresponding change of the IF frequency. The target at 30 m away from the radar was detected at 1008 kHz IF frequency with an SNR of 16 dB. The maximum gain variation between the channels was observed to be about 3 dB. This received power is reasonably similar to the calculated one taking into account the Rx gain of 28 dB, the Tx power of about 10 dBm, the PGA gain of 20 dB, and the antenna gain of 10.8 dBi using the radar equation [21]. The roll-off of the noise floor spectrum around dc was due to characteristics of the DC block.

C. ANGLE MEASUREMENT RESULTS
The direction of arrival (DOA) can be estimated using four-channel received data. To evaluate the angle detection  capability of the proposed radar system, the conventional delay and sum beamforming algorithm was adopted [22]. Beam steering is effective on the premise that IF signals of the four receiving channels have the same phase of the target located at an angle of 0 • . In the proposed active array system, accurate phase synchronization between Rx channels is not easy at the design time because the FMCW reference signal distribution at the board level cannot be accurately controlled due to tolerances in PCB manufacturing. Therefore, the phase of received signals is not identical, mainly due to different delays in the reference LO distribution network from the DDS. To calibrate the phase offset for each channel, a reference target positioned at the right front of the radar was measured. Fig. 25 shows the measurement setup and DOA measurement results of two targets. These results were obtained by moving the beam steering vector by ±90 • in 1 • step.

VI. CONCLUSION
This work implemented a 1-Tx, 4-Rx 79 GHz FMCW CMOS radar system on a low-cost FR-4 board. The FR-4 board is cost effective with good manufacturability. However, the high loss from the chip to the antenna array and the low efficiency of the antenna make it difficult to implement a W-band system on the FR-4 board. This work overcomes performance degradation of the FR-4 board in the W-band by feeding a separate antenna directly from a chip equipped with an on-chip feeder like an active antenna system. The integrated patch antenna on the FR-4 substrate was found to have a gain more than 10 dBi. The fully integrated 4 channel Rx array was evaluated by range and DOA detection. Since the number of channels can be easily expanded, the proposed low-cost system could be a cost-saving solution for a high-resolution radar.  BYUNG-SUNG KIM (Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electronic engineering from Seoul National University, Seoul, South Korea, in 1989, 1991, and 1997, respectively. In 1997, he joined the College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea, where he is currently a Professor. He was a Visiting Researcher with the University of California at Santa Barbara, in 2013. His research interests include high-frequency device modeling and RF/millimeter-wave CMOS integrated circuit design. VOLUME 8, 2020