Stability Analysis and Efficiency Optimization of an Inductive Power Transfer System With a Constant Power Load

Series-series compensated inductive power transfer (SSIPT) systems have been widely studied and characterized for constant resistance loads (CRLs) and constant voltage loads (CVLs), but much less so for constant power loads (CPLs), although CPLs have numerous applications. In this work, we address some of the fundamental knowledge gaps for SSIPT/CPL systems that we believe have not been fully explored in the literature. First, we apply Middlebrook’s stability criterion to derive a closed-form impedance-based stability condition for SSIPT/CPL systems. The derivation of the equilibrium solution is based on small-signal analysis and we show its consistency with intuitive results from perturbation-based arguments. Second, we show that the power transfer efficiency is minimum at the resonant frequency of the primary resonator. Third, the stability criterion is used to develop a straightforward approach for finding the operating frequency and input voltage that achieves near-maximum power transfer efficiency. This solution is useful as a starting point for a more meticulous parameter sweep to find the optimum input voltage and frequency values. Our analytical results are validated by performing frequency sweep measurements with two SSIPT experimental setups – one tuned to 165 kHz and the other to 6.78 MHz. We also provide an intuitive description and comparison of voltage-driven and current-driven CPLs. This topic is rarely treated in an intuitive manner and largely ignored, but we believe a solid conceptual understanding of voltage-driven and current-driven CPLs is beneficial for designers.


I. INTRODUCTION
Inductive power transfer (IPT) systems have rapidly gained popularity as an efficient and practical means for wirelessly transferring power by magnetic induction over short distances. In the literature, IPT systems are routinely considered with constant resistance loads (CRLs) and constant voltage loads (CVLs), while constant power loads (CPLs) receive much less attention. Nevertheless, CPLs are important as they model the behavior of tightly regulated power converters and motor drives which are deployed in a number of applications like automotive systems [1]- [3], aircraft [4], [5], The associate editor coordinating the review of this manuscript and approving it for publication was Guangdeng Zong .
ships [6], [7], and microgrids [8]- [13]. In the area of DC distributed power systems, CPLs have traditionally been investigated for networks of classic switch-mode converters like buck, boost, and buck-boost converters [4], [8], [14]- [18]. In comparison, there have been significantly fewer detailed studies of IPT systems with CPLs. This work addresses some knowledge gaps for CPL-loaded IPT systems that we believe are fundamentally important but not yet sufficiently addressed. In particular, our study is focused on the stability and power transfer efficiency of series-series compensated IPT (SSIPT) systems. This SSIPT topology was chosen because of its popularity, simplicity, capability for high power transfer efficiency, load-independent output current, and k-independent tuning [19].
A CPL maintains to consume a constant amount of power, i.e., the input and the output power remains always constant. Therefore, a CPL has negative incremental impedance, although the instantaneous impedance is positive. As mentioned above, tightly regulated DC-to-DC converters exhibit CPL behavior. As an example, Fig. 1 shows a block diagram of a DC-to-DC converter that maintains a tightly regulated current through a CVL. This may model, for example, a battery management system during a phase of the charging cycle. For simplicity, if we assume the DC-to-DC converter is lossless then the input power equals the output power delivered to the CVL. Let, V CPL , I CPL , and P CPL represent the input voltage, current, and power, respectively. If the input voltage V CPL is increased then the input current I CPL must decrease in order to maintain the product P CPL = V CPL I CPL for a fixed output power (and vice versa). This means the CPL has a negative incremental resistance. In contrast, for ordinary CRLs if we increase the input voltage then the input current also increases.
From a design standpoint, CPLs are challenging because they have negative incremental resistances which can cause system instability. For analyzing stability of cascaded power electronic systems, it has proven effective to use the minor loop gain, which is the ratio of the source to load impedances at an interface between two converters. Middlebrook showed the minor loop gain plays an equivalent role in the stability analysis of cascaded power converters as the ordinary loop gain for feedback systems [20]. A necessary and sufficient condition for stability is that the minor loop gain satisfies the Nyquist stability criterion. This has been used to derive various impedance-based stability conditions [14], [20]- [24], each offering a unique balance between simplicity and conservatism of stability criteria. Originally, the minor loop gain was developed for voltage-source systems. Later the formation of the minor loop gain was generalized to handle current-source systems [25]- [27], and distributed power systems with arbitrary subsystems [28], [29]. Along with assessing stability, there are a number of techniques to improve stability which are reviewed and summarized in detail in [14].
As the large number of articles and attention on the topic indicates, stability of power systems is a critically important topic. However, the stability of IPT systems with CPLs is not fully explored. Particularly, we have not seen a rigorous derivation of an impedance-based stability criterion for SSIPT/CPL systems. In previous works in this area, the equilibrium solution was reasoned using perturbation arguments applied to the power transfer curve [26], [30]. While intuitive, such arguments lack the rigor of a more formal stability analysis. In other works on IPTs, steady-state analytical solutions have been asserted and verified without a stability analysis (e.g., see [31]). Given the importance of stability and the rising adoption of IPT technology, in this work we firmly establish a closed-form stability criterion for the SSIPT/CPL system based on a rigorous small-signal stability analysis (Middlebrook's approach). Our stability analysis assumes a voltage-driven CPL. We suspect that a number of researchers focused on IPT system design may not be familiar with voltage-driven CPLs and current-driven CPLs. Therefore, in this work we also present an intuitive and simple description of these models.
Along with stability, the power transfer efficiency η is a key figure of merit for IPT systems. It is well-known that for ordinary CRLs, the efficiency η can be maximized at the resonant frequency for a tuned IPT system, provided the optimal choice of load impedance. On the contrary, it has been recently reported that η is poor for a tuned SSIPT/CPL operating on-resonance in stable equilibrium [30], [31]. However, to the best of the authors' knowledge, it has not been proven that the efficiency is minimum at resonance. We therefore prove here that the power transfer efficiency is indeed minimum at the resonant frequency of the primary series LC resonator for a SSIPT/CPL system.
A key question is: how does one increase η of a SSIPT/CPL system if η is minimum at resonance? Zhang et al. showed that η can be increased by operating off-resonance [31], and derived design equations for maximizing η for a given input voltage. While useful if the input voltage is fixed, these design equations do not yield the maximum possible efficiency. This leaves the need to perform a two-dimensional parameter sweep to find the optimal input voltage and optimal operating frequency to fully maximize efficiency. However, parameter searches can be computationally expensive, slow, and unintuitive. To address this, we present here analytical expressions for finding a near-optimal starting point to dramatically speed up the parameter search. Our method uses the impedance-based stability criterion and the known equation for the optimal load impedance.
The summary of the contributions of this article with some remarks regarding our motivation and novelty is presented below: 1) We firmly establish a closed-form stability criterion for the SSIPT/CPL system based on a rigorous small-signal stability analysis (Section II). This stability analysis has not been published before and provides a more formal and rigorous treatment of the subject compared to previous perturbation-based arguments [26], [30]. We were motivated to undertake this stability analysis because it was not clear the validity VOLUME 8, 2020 and assumptions made in the simple perturbation-based treatments. 2) We show that the efficiency of a SSIPT/CPL system is minimum at the resonant frequency of the primary resonator (Section III. A). This result is a defining feature of SSIPT/CPL systems, but it has not been explicitly stated or emphasized before in other works. This result is important because it may conflict with expectations gained from the widespread use of tuned SSIPT systems with ordinary CRLs and CVLs in which the maximum possible efficiency is achieved by operating at resonance with an optimum load impedance. In contrast, for tuned SSIPT/CPL systems, the efficiency is minimum at resonance and the designer must select a different operating frequency to improve efficiency. 3) We present a novel method for finding the optimal combination of operating frequency and input voltage to maximize the power transfer efficiency for a given set of SSIPT/CPL system parameters (Section III. B).
The closest related works are [31] and [38]. In [31] the optimal operating frequency is found that maximizes efficiency for a given input voltage. Conversely, in [38] the optimal input voltage is found that maximizes efficiency for a given operating frequency. The limitation of both approaches is that they do not yield the maximum possible efficiency. In other words, they do not optimize both the input voltage and operating frequency, simultaneously. A two-dimensional parameter sweep over input voltage and operating frequency is therefore needed to find the optimal combination. Our method speeds up the search by providing a simple and intuitive analytical method for finding the near-optimal combination of operating frequency and input voltage.

II. IMPEDANCE STABILITY CRITERION FOR A SSIPT SYSTEM TERMINATED IN A CPL
Our focus is on achieving high efficiency for an IPT system that is stationary (i.e., the coil-to-coil orientation and distance are fixed) with a known, fixed output power in stable equilibrium. An example of a stationary application is an inductive charging system with magnetic alignment and attachment. An example of a fixed-power CPL model is a battery management system that maintains constant current through a battery during a phase of the charging cycle. Fig. 1 shows a schematic diagram of a SSIPT system terminated in a CPL. The system includes a power inverter, coupled resonant network, and rectifier. The primary (secondary) series resonator is composed of capacitor C 1 (C 2 ), inductor L 1 (L 2 ), and series resistor R 1 (R 2 ). The mutual inductance between inductors L 1 and L 2 is M = k √ L 1 L 2 , where k is the coupling coefficient. The output of the rectifier connects to a low pass filter capacitor C f in parallel with the CPL. Unless otherwise stated, this article assumes ideal lossless switches and diodes and ignores inverter switching losses. We assume no feedback or communication between the primary and secondary sides. At steady state the coupled resonator section between the output of the inverter and input of the rectifier can be modeled by the AC equivalent circuit shown in Fig. 4. Here we employ the sinusoidal approximation in which higher-order harmonics of the switching frequency are ignored, and the waveforms are assumed to be purely sinusoidal. Bold capital letters represent phasor quantities of the corresponding first-harmonic sinusoidal waveforms, e.g., I 1 is the phasor representation of i 1 (t). The terminal AC voltages V 1 and V 2 relate to the terminal DC voltages V g and V 0 as follows [32], [33]: where D is the inverter's duty cycle 0 ≤ D ≤ 1; coefficient c 12 = 1 for a half-bridge inverter and 2 for a full-bridge inverter; and coefficient d 12 = 1 for a half-bridge rectifier and 2 for a full-bridge rectifier. The terminal AC current I 2 is related to the terminal DC current Io by: Additionally, V 2 and I 2 are in phase and their ratio is the effective AC CPL input resistance: The output impedance Z th and open-circuit voltage gain G v,AC of the AC Thevenin equivalent circuit shown in Fig. 4 can be obtained using ordinary AC circuit analysis, yielding the following expressions: where ω is the switching frequency of the inverter, and X 1 = ωL 1 − 1/(ωC 1 ) and X 2 = ωL 2 − 1/(ωC 2 ) are the primary and secondary reactances, respectively. Since the rectifier is assumed lossless, the output power P o delivered to R CPL is equal to the real power consumed by the effective AC load R e,CPL . Therefore, the AC Thevenin equivalent circuit shown in Fig. 4 can be used to express output power P 0 consumed by the CPL in terms of R e,CPL , V 1 , G ν,AC , and Z th : According to the maximum power theorem, the AC circuit in Fig. 4 should be terminated in a load impedance that is conjugately matched to Z th to obtain the maximum available power from the source P max . However, in our AC circuit the CPL's effective AC resistance R e,CPL is real (no imaginary component). Under this constraint, maximum power transfer occurs for R e,CPL = |Z th | and P max can be found by substituting R e,CPL = |Z th | into (7), yielding (after some algebraic simplifications):

B. OUTPUT STEADY-STATE POWER CURVE
We do not have direct control of the CPL's input impedance R CPL ; instead, the CPL effectively regulates a constant power sink P o = V o I o by adjusting R CPL . Assuming all other circuit parameters are fixed, the value of R CPL sets the output power.
Recall that the CPL's input resistance R CPL is related to its effective AC input resistance R e,CPL by (4). If the CPL is programmed to sink output power P 0 < P max , then we find that there are two possible values of R e,CPL that yield the same power P 0 at steady state. To find these values we rearrange terms in (7) to yield a quadratic equation in R e,CPL and solve for the roots, which we denote R e,CPL,1 and R e,CPL,2 : VOLUME 8, 2020  5 shows a normalized power transfer characteristic curve generated by loading the AC Thevenin equivalent circuit in Fig. 4 with a variable AC load R e,L , sweeping the load from R e,L = 0 to R e,L = 5|Z th |, and plotting the normalized load power P L /P max . As expected, the peak of the power curve P max occurs for the load R e,CPL = |Z th |. If the system is loaded with a CPL programmed to sink output power P 0 < P max , then Fig. 5 confirms that there two solutions for the effective AC CPL input resistance, which we recognize as R e,CPL,1 and R e,CPL,2 given by (9,10). Our first goal is to prove that the solution with the positive root R e,CPL,2 is the stable equilibrium solution.

C. SMALL-SIGNAL TRANSFER FUNCTION
Here we use small-signal analysis to investigate the stability of the SSIPT system in Fig. 2. This is achieved by driving the system with a time-varying input voltage v g (t) in which the average of v g (t) is equal to a positive DC (quiescent) value V g plus a superimposed small-signal AC variation v g (t): where v g (t) T s denotes the average of v g (t) over the switching frequency T s . In our notation, capital letters X denote DC steady-state values and lower-case terms x(t) represent small-signal AC variations. Fig. 6 presents a simplified block diagram of the SSIPT system showing the terminal signals decomposed into their steady-state DC and small-signal AC components. If we assume the system can be linearized at the quiescent operating point, then the system dynamics are characterized by the small-signal AC Thevenin equivalent circuit shown in   the transfer function of the small-signal AC Thevenin equivalent circuit in Fig. 7, represented as . (12) The reason for expressing the transfer function i o (s)/ ν g (s)G ν (s) in three equivalent forms (12) is to highlight that one form may be more convenient to use over the others for stability analysis and that we are free to choose which form to use. Stability is clearly dependent on the pole and zero locations of Z g (s) and Z CPL (s). In the following sections we examine the properties of Z g (s) and Z CPL (s) individually, and then use this information along with (12) to develop our impedance-based stability criterion.

D. PROPERTIES OF THE SMALL-SIGNAL SOURCE IMPEDANCE
The small-signal source impedance Z g (s) characterizes the impedance of the SSIPT system. In general, the source impedance Z g (s) of a stable source converter has no RHP poles (called ''open-circuit stable'') and no RHP zeros (called ''short-circuit stable'') [34]. Since the SSIPT system shown in Fig. 2 is powered directly by the DC input voltage ν g (t), operates in open loop without feedback, and contains only passive components and switching elements, we assume the SSIPT system is stable under all passive loading conditions (including open and short loads). We conclude Z g (s) has no RHP poles nor RHP zeros. Next, we evaluate the small-signal source impedance Z g (s) at the limits s = 0 and s = ∞. At s = 0 we have the following result (proven in the Appendix): As s → ∞ the large lowpass filter capacitor C f (see Fig.  2) shorts out the circuit elements proceeding it; therefore, In this work we assume that C f is sufficiently large such that the magnitude |Z g (s)| decreases rapidly as s is increased from DC such that max|Z g (s)| = |Z g (0)|.

E. CPL MODEL
At DC steady state, the CPL consumes power P o = V o I o and has an input resistance Fig. 8 presents two ideal CPL models, one implemented with a voltage-controlled current source (VCCS) and the other with a current-controlled voltage source (CCVS), both of which react instantaneously to signal changes. The small-signal impedance of each model can be derived by linearizing about the DC (quiescent) operating point. The result is that both ideal CPLs exhibit the same negative small-signal resistance Z CPL (s) = −R CPL , where R CPL is the large-signal DC resistance. This negative impedance characteristic is a well-known result used in numerous stability studies (e.g., see [4], [8], [15], [35]).
Despite the fact that the ideal VCCS and CCVS CPLs in Fig. 8 have the same small-signal impedance Z CPL (s) = −R CPL , we see that there is a clear difference between the two models. Namely, the VCCS CPL is not compatible with independent current-source inputs, while the CCVS CPL is not compatible with independent voltage-source inputs. This difference is not modeled in their small-signal impedances, which suggests that the ideal models in Fig. 8 are incapable of being realized with physical circuitry. Realistic CPLs, such as tightly regulated DC-to-DC converters, exhibit dynamic behavior and behave as CPLs only within the bandwidths of the converters' feedback loops [7], [36]. Even SPICE is not able to simulate the ideal CPL's instantaneous behavior, since the program's iterative algorithm includes a numerical delay of at least one time-step between input signal variations and output responses produced by the dependent sources. Therefore, to make the CPL models more realistic for our small-signal stability analysis, we shall slow their response times. The modified CPL models are shown in Fig. 9, where the equivalent circuit parameters C and L limit the bandwidth of the respective models to be consistent with a realistic controller design. The modified VCCS CPL in Fig. 9 (a) has small-signal impedance: which has a RHP pole at 1/(C R CPL ). The modified CCVS CPL in Fig. 9 (b) has small-signal impedance: which has a RHP zero at R CPL /L . Because the small-signal impedance expressed in (15) for the VCCS CPL has a RHP pole, the CPL is stable when connected to an independent voltage source and unstable when connected to an independent current source. We refer to this type of CPL as ''voltage-driven'', since voltage changes across the CPL's input terminals drive the load to proportionately adjusts its current draw. Such voltage-driven CPLs are common and well-studied, going back to Middlebrook's original article on the minor loop gain [20]. In contrast, the small-signal impedance expressed in (16) for the CCVS CPL has a RHP zero, which means this ''current-driven'' CPL is stable when connected to an independent current source and is unstable when connected to an independent voltage source. Conceptually, a CPL is a self-adjusting variable resistor that continuously changes its input resistance to maintain a constant power sink.
With this impedance-based viewpoint, the difference between ''voltage-driven'' and ''current-driven'' CPLs relates to the way its input resistance is adjusted in the face of disturbances. Using a discrete-time approximation, we can imagine power transfer change requests are sent to the CPL when mismatches are detected between the target output power and the measured output power. Table 1 presents the reactions of voltage-driven and current-driven CPLs to such requests. A detailed transient analysis depends on the dynamics of the specific CPL implementation which is outside of the scope of this work. As will be shown, the CPL properties that are centrally important to stability include the DC value of the small-signal impedance Z CPL (0) = −R CPL and the existence of RHP poles and RHP zeros of Z CPL (s). While our bandwidth-limited CPL models shown in Fig. 9 are simple, they are sufficiently broad in scope to feature both important properties.

F. IMPEDANCE-BASED STABILITY CRITERION
As previously mentioned, the literature on power converter stability commonly assumes voltage-driven CPLs (note that in many articles this assumption is not explicitly stated but implied). Indeed, voltage-driven converters are much more common than current-driven converters, so most actual applications will be better matched to this model. In this work we follow suit and focus solely on SSIPT systems terminated in voltage-driven CPLs to simplify the scope of the analysis. For the remainder of this article, current-driven CPLs are not considered. We model the voltage-driven CPL using the VCCS CPL in Fig. 9 (a), which has a small signal impedance given by (15) with a RHP pole. The source impedance Z g (s), which characterizes the source impedance of the SSIPT system, has no RHP poles. Both Z g (s) and Z CPL (s) have no RHP zeros. It follows from the pole and zero placements of Z g (s) and Z CPL (s) that the minor loop gain Z g (s)/Z CPL (s) in (12) is stable. We can therefore apply the Bode stability criterion [37] to this minor loop gain to determine the stability of the system as a whole. Note that the minor loop gain Z CPL (s)/Z g (s) in (12) is unstable; therefore, we cannot directly apply the Bode stability criterion to this gain term. Using (13) and (15) we can express the minor loop gain Z g (s)/Z CPL (s) in (12) at DC as: .
Since R CPL > 0, Re[Z th ] > 0, R e,CPL > 0, and |Z th | > 0, the minor loop gain at DC must be negative; therefore, Z g (0)/Z CPL (0) = −|Z g (0)/Z CPL (0)|. Given a sufficiently large output capacitance C f , we assume the amplitude of the minor loop gain decreases rapidly with s such that max{|Z g (s)/Z CPL (s)|} = |Z g (0)/Z CPL (0)|. Hence, to satisfy the Bode stability criterion it is necessary and sufficient that the amplitude of the minor loop gain is less than unity at DC, or Simplifying (18) yields: which is our desired impedance-based stability criterion in terms of the AC equivalent circuit impedance. If the CPL's operating power P 0 is less than the maximum available power from the source (P 0 < P max ), we found that there are two solutions for R e,CPL which are denoted R e,CPL,1 and R e,CPL,2 in (9). We are now in a position to show that R e,CPL,2 is the stable solution. First, it is straightforward to show from (9, 10) that R e,CPL,2 > |Z th | and R e,CPL,1 < |Z th | (this is illustrated graphically in Fig. 5). Hence, R e,CPL,2 satisfies the stability criterion (19) and is therefore the stable equilibrium solution for R e,CPL . It is also straightforward to show from (7) that if (19) is satisfied then the following condition holds true: which is an alternative form of the stability criterion. Substituting (5) into (19) yields another form of the stability criterion that is directly in terms of the CPL's large-signal DC resistance: Substituting (4) into (20) yields: Equations (19)- (22) are four equivalent forms of the impedance stability criterion. They all give the same result that R e,CPL,2 given in (10) is the CPL's stable equilibrium resistance for the SSIPT system, assuming a voltage-driven CPL. The form of the stability criterion in (22) matches that published by Narusue et al. who considered the special case of a perfectly-tuned resonant SSIPT system terminated in a CPL (see Section II in Ref. [30]). The derivation of Narusue et al. is based on reasoning how the rectifier output voltage would react to small disturbances at different operating points for a tuned-system operating at resonance. In contrast, our derivation here is based on classical small-signal analysis and the Bode stability criterion, and valid for both tuned and mistuned systems. We note again that our derivation assumes a voltage-driven CPL. Additional insights into the impedance stability criterion (19) are gained by looking at the system's trajectories of various initial conditions on the normalized power transfer characteristic curve, as shown in Fig. 10. This curve is the same as that shown in Fig. 5 except with the addition of five initial conditions (or states) labeled A, B, C, D and E with arrows that depict the system's trajectories. Each state is quantified by a single independent state variable: the CPL's effective AC input resistance R e,CPL . The value of R e,CPL sets the instantaneous output power consumed by the CPL. The arrow directions are found by considering the CPL's response at each state As discussed previously, a CPL can be effectively modeled as a self-adjusting variable resistor that continuously changes its effective AC input resistance R e,CPL in pursuit of sinking a constant target output power P 0 . A basic voltage-driven CPL achieves this through a simple algorithm: it decreases R e,CPL if the measured output power P L is less than the target output power P 0 (i.e., P L < P 0 ), and increases R e,CPL if the measured output power P L is greater than the target output power P 0 (i.e., P L > P 0 ). In sketching the trajectories shown in Fig. 10, we assume the system slowly moves toward equilibrium without overshoot due to the large output capacitor C f . Note that all arrows in  On the other hand, R e,CPL,2 is an attractor (or sink). Specifically, R e,CPL,2 is a locally stable state for initial values of R e,CPL greater than R e,CPL,1 . Note that R e,CPL approaches zero if the initial value of R e,CPL is less than R e,CPL,1 .
For a stationary IPT system with a fixed output power, both the CPL's resistance and the system's power transfer efficiency remain fixed and stationary over time after the system reaches stable equilibrium.

III. POWER TRANSFER EFFICIENCY OF A SSIPT SYSTEM TERMINATED IN A CPL AT EQUILIBRIUM A. EFFICIENCY LIMIT OF A TUNED RESONANT SYSTEM IN STABLE EQUILIBRIUM
An important figure of merit is the power transfer efficiency η = P o /P s at the DC stable equilibrium state, where P o is the power delivered to the CPL and P s is the power produced by the source. In this section we consider the efficiency of a synchronously tuned SSIPT system (ω 0 = 1/ √ L 1 C 1 = 1/ √ L 2 C 2 ) operated at resonance in which the primary and secondary reactances are both zero (X 1 = 0 and X 2 = 0). This is a common assumption and operating condition for SSIPT systems in the literature. Unfortunately, a tuned SSIPT system terminated in a voltage-driven CPL has an efficiency less than the maximum in stable equilibrium. In fact, Narusue et al. showed that for a lossy system in stable equilibrium the efficiency is less than 50% (η < 0.5) [30]. We shall verify this result using the impedance stability criterion (19).
The efficiency η of a SSIPT system terminated in a general AC load resistance R e,L is [38]: .
At resonance X 2 = 0, and (23) can be rewritten in terms of three terms R e,L ,|Z th |, and R 2 : Inspecting (24) reveals that if R e,L > |Z th | then η < 0.5. Since, the voltage-driven CPL's input resistance R e,CPL > |Z th | in stable equilibrium according to the impedance stability criterion (19), we conclude the maximum efficiency for a resonant tuned SSIPT system terminated in a voltage-driven CPL is less than 50% in stable equilibrium. Furthermore, for practical cases with output power levels much less than the maximum available power of the source, the corresponding efficiency is much less than 50%. To graphically illustrate the efficiency limit concept, Fig. 10 presents a plot of the normalized power transfer characteristic and efficiency. These curves are generated by analyzing the AC equivalent circuit in Fig. 3 with a variable load R e,L in which the load resistance is swept from R e,L = 0 to R e,L = 9|Z Th |. The primary and secondary effective series resistances are R 1 = R 2 = 0.039|Z Th |. The shaded area in Fig. 10 corresponds to the region R e,L < |Z th |, which is unstable for a voltage-driven CPL termination according to the stability criterion (19). Note that the efficiency η reaches values greater than 50% in the unstable (shaded) region; however, η < 50% in the stable (unshaded) region. The above analysis shows that, without modification, the tuned SSIPT system at resonance will converge to the operating point with reduced efficiency. Indeed, it can be shown from (23) that ∂η/∂X 1 | X 1 =0 for R e,L = R e,CPL,2 given by (10), which means the efficiency is minimum at stable equilibrium at the primary circuit's resonant frequency. This is an important result for SSIPT/CPL systems, which, to the best of the authors' knowledge, has not been stated explicitly in the literature before.

B. OPERATING OFF-RESONANCE TO STABILIZE THE SYSTEM AT A HIGH EFFICIENCY OPERATING POINT
In the previous section we showed that the efficiency of a resonant-tuned SSIPT system is minimum at resonance in stable equilibrium. To increase efficiency, Narusue et al. proposed adding a K-impedance inverter to the primary side which increases the optimum input resistance [30]. While effective, a K-impedance inverter introduces more components into the system, which adds complexity and increases loss. A simpler solution is to operate off-resonance. Zhang et al. showed how to find the optimal frequency to maximize efficiency for a given input voltage [31]. This is useful if the input voltage is fixed, but the method does not yield the maximum possible efficiency. A parameter sweep is required to find the optimal input voltage and operating frequency to maximize efficiency. To speed up search, it would be useful to select a starting point near the optimum point. In this section we show how to find such a starting point. The optimum AC load impedance R e,L required to maximize efficiency η is [38]: Substituting R e,L = R e,opt into (23) yields the maximum efficiency at any given frequency. The maximum achievable VOLUME 8, 2020 FIGURE 11. Power transfer characteristic and efficiency curve for a tuned SSIPT system operated at resonance. efficiency over all frequencies occurs at resonance X 2 = 0 [38] and decreases as the operating frequency is adjusted offresonance.
Consider a synchronously tuned SSIPT/CPL system, in which the primary and secondary resonate at the same frequency ω o . Due to the stability criterion (19), the optimal solution closest to ω o is available at frequencies which satisfy the equality: R e,opt = |Z th |. There will in general be two solutions to this equation (one frequency above ω o , and the other below ω o ). It is common practice to operate above resonance to force the primary current to lag the input voltage, which is necessary for zero voltage switching (ZVS). After the frequency is determined, the corresponding input voltage can be found by solving V 1 using the AC Thevenin equivalent circuit in Fig. 4 and applying (1): The operating frequency and input voltage found using the method described above will yield a near-optimal solution for maximizing efficiency that is useful for initiating a parameter sweep. The selection of the off-resonance frequency will be further addressed in the section IV(B).

IV. EXPERIMENTAL VALIDATION
Two different SSIPT systems -one tuned to 6.78 MHz and another tuned to 165 kHz-were constructed to validate results. Each SSIPT system was terminated with an electronic load, and the steady-state system responses were measured over frequency for different load conditions. This section presents the results.

A. 6.78 MHz SYSTEM
A photograph of the 6.78 MHz system is shown in Fig. 12 and its system parameters are presented in Table 2. We are interested in 6.78 MHz because this is the operating frequency used in the A4WP standard. Our system was driven with an Amplifier Research 75A250A RF power amplifier and terminated in a BK Precision 8601 DC electronic load programmed in CW mode to sink 2 W. The full-bridge rectifier was constructed with PDS3100-13 diodes from Diodes   Incorporated. The transmit coil used was a single-layer multiturn inductor (210 mm -by-210 mm) constructed with AWG 15 wire, and the receive coil was a smaller flat single-layer spiral coil on a PCB. No shielding or ferrites were used, and the coil-to-coil distance was approximately 1 cm.
Figs. 13 and 14 present plots of the DC load resistance and efficiency as functions of frequency. We see that as the operating frequency approaches the resonant frequency (6.78 MHz), the stable equilibrium resistance rises significantly (Fig. 13) and efficiency decreases (Fig. 14). Calculated and measured results in Fig. 13 show fair agreement. The largest disagreement between measured and calculated results are the efficiency curves shown in Fig. 14. This disagreement is likely due to measurement tolerance as well as rectifier diode conduction losses and parasitic capacitances that are not included in the analytical model. As we shall demonstrate, we achieve much better agreement at lower frequencies in which these non-ideal effects are less significant.   Fig. 15 presents a photograph of the experimental 165 kHz wireless charging system. We chose 165 kHz because this frequency is within the typical 87 to 205 kHz operating range used by the popular WPC Qi wireless power standard for inductively charging portable consumer electronics [39]. A possible application involving a CPL at this frequency is inductively charging an off-the-shelf device by connecting the wireless power receiver to the device's charging port. In such a case, the load would constitute the device's integrated battery management system, which typically behaves as a CPL over the majority of the charging cycle. The principal parts of the system are the half-bridge inverter, coupled-inductor resonant circuit, passive half-wave rectifier, and electronic load. For a set of system components and parameters, our goal is to select an inverter switching frequency f and DC input voltage V g that maximizes efficiency of the SSIPT/CPL system for a given output power. No communication is assumed between the primary and secondary.

B. 165 kHz SYSTEM
System components include an EPC9201 half-bridge inverter, WE-WPCC coils (part number 760308110) with a 2.3 cm air gap, SR340 Schottky rectifier diodes, and a XL4015 buck converter. The inverter's FET on-resistance  Table 3, the values of parameters have been summarized.    16 is a plot of |Z th | versus the optimal rectifier input resistance (R e,opt ). This plot is generated using analytical equations with measured variables (k, L 1 , L 2 , C 1 , C 2 , Q 1 , Q 2 , etc.) for a 5 W system with a half bridge rectifier and half bridge inverter. For simplicity, the rectifier loss is not included in this plot. The purpose of generating such a figure is to give the designer a direction for finding an appropriate operating point (i.e,. input voltage and operating frequency). The designer looks for the intersection of |Z th | with the optimum rectifier input resistance. In Fig. 16, this occurs for a frequency of 175.84 kHz. We also see that at 175.84 kHz the optimal rectifier input resistance is 6.22 . Next we can plug these into (26) to find the optimal input voltage at 175.84 kHz, which we find to be 11.1 V. Assuming the rectifier is not too lossy, this tells us that the optimal solution is near f =175.84 kHz and V g =11.1 V, which informs the region for the parameter sweep. Fig. 17 represents the efficiency contour, where the frequency and DC input voltage are swept for the same 5 W system. In addition, this plot (Fig. 17) includes the rectifier loss for completeness. In Fig. 17, the red X marks the absolute maximum possible efficiency point and the red circle marks a good practical operating point. The white region in the contour plot is the invalid region, in which the output power P o is less than the maximum available power P max from the SSIPT system. The practical operating point is chosen (corresponding to the red circle in Fig. 17) because this operating point yields near optimal efficiency while significantly decreasing the sensitivity to variations in input voltage and frequency. The maximum possible efficiency (red X) efficiency is 0.873, while the efficiency of the point (red  circle) is 0.871. This point (red circle) corresponds to an input voltage and frequency operating point of: V g =12 V and f =175.5 kHz. Fig. 18 compares the measured and calculated (analytical) frequency responses, which shows good agreement. At the design frequency f = 175.5 kHz the measured and calculated efficiencies (η) are above 0.87. The red circles are measured data and the black line is the analytical. This plot includes the losses due to the rectifier. So the efficiency is the full DC-to-DC efficiency of the system including the inverter, resonant circuit, and rectifier.
The power loss in the rectifier is a significant portion of the overall system loss and is mainly due to the forward voltage drop V F across each diode. Fig. 19 shows a plot of the measured output DC voltage V o over frequency. In highpower IPT systems V F is typically negligible compared to the output DC voltage V o ; however, in our case V F = 0.45 V, which is non-negligible compared to V o = 15 V at 175.5 kHz. The efficiency η rec of the half-wave rectifier alone can be calculated as [40]: Substituting V F = 0.45 V and V o = 15 V into (27) yields η rec = 0.943 at 175.5 kHz, which compares well with the measured rectifier efficiency of η rec = 0.940. With this, the measured wireless link efficiency without the rectifier is 0.871/0.94 = 0.93. This is only slightly less than the theoretical possible maximum efficiency η max = 0.94, which we calculate using R e,opt given by (25) at resonance (X 2 = 0 and ω = ω 2 ). The wireless link efficiency can be improved by increasing the coupling coefficient k; however, out of interest we have chosen to consider a system with looser coupling (k = 0.206) compared to a typical Qi-compliant system in which k is around 0.65-0.8 [41].

V. CONCLUSION
In this work, we address some fundamental knowledge gaps for SSIPT/CPL systems that we believe have not been fully explored in the literature. In particular, we analyzed the small-signal stability of a SSIPT/CPL system and developed an impedance-based stability criterion that is simple, agrees with intuition, and based on reasonable assumptions. We also showed that the power transfer efficiency is minimum at the resonant frequency of the primary resonator. This behavior is contrary to that of a SSIPT system terminated in a CRL (e.g., a resistor) which can achieve maximum efficiency at the resonant frequency. Finally, we used the stability criterion is to develop a straightforward approach for finding the operating frequency and input voltage that achieves near-maximum power transfer efficiency. This solution is useful as a starting point to speed up a parameter sweep over input voltage and operating frequency for maximizing efficiency. We believe our results are beneficial improving the design process of SSIPTs with loads that behave as CPLs, such as tightly regulated power converters.
We found that the measurements for the 165 kHz system agreed very well with the analytical models. On the other hand, efficiency measurements for the 6.78 MHz system showed more disagreement but did still exhibit the basic features predicted at resonance (i.e., high equilibrium load impedance and minimum efficiency). We believe that at the high operating frequencies, the simple diode model we assumed is not adequate and needs improvement for better agreement. Other challenges at MHz frequencies include higher sensitivity to measurement error and parasitic capacitances.
For future work, it would be useful to study how SSIPT/CPL systems perform against disturbances (e.g., changes in coupling coefficient). It would also be useful to compare how various IPT topologies (e.g., series-series, series-parallel, LCC-series, etc.) perform with CPLs in terms of efficiency, bandwidth, sensitivity to coupling coefficient changes, etc. The performance and features of these topologies are better understood for ordinary loads than for CPLs.

APPENDIX
To prove (13) consider the SSIPT system shown in Fig. 20, which is driven by a DC input voltage v g (t) = V g and terminated in a DC current sink i out (t) = I o . Note that the quiescent output voltage is v out (t) = V o . If the output current i out (t) is suddenly increased from I o to I o +δI 0 then the system will undergo a transient step response and the output voltage v out (t) will change over time from V o to its new quiescent value V o + δV 0 . For a small disturbance, such that I o δI 0 and V o δV 0 , the DC small-signal input impedance can be approximated as Z g (0) ≈ −(δV 0 )/(δI 0 ). In the differential limit we obtain Z g (0) = −(dV 0 )/(dI 0 ).
To find Z g (0) = −(dV 0 )/(dI 0 ), we first solve for the AC output voltage magnitude |V 2 | by analyzing the AC Thevenin equivalent circuit in Fig. 4 terminated in a general AC effective load resistance R e,L : Next we use (1) -(4) to re-express (28) in terms of the DC terminal variables V g , V o , and I o : Squaring both sides of (29), simplifying, and rearranging terms yields the following expression: Taking the derivative of both sides of (30) with respect to I o , and substituting Z g (0) = −(dV 0 )/(dI 0 ) and R L = V 0 /I 0 .
PETER PHAM (Member, IEEE) received the B.Sc. degree from The University of Tennessee, Knoxville, in 2018, where he is currently pursuing the M.Sc. degree in electrical engineering. He was with the research center early in his undergraduate years and played important roles in many student organizations, such as the student leadership council. His major research interest is in the field of power electronics. He is currently working on the wireless power transfer project sponsored by PowerAmerica. He received several outstanding awards and won different mathematical and robotic competitions during his undergraduate years. He has been working in the area of distributed power systems and renewable energy integration for last ten years. He has authored or coauthored a number of research articles and posters in these fields. He is currently an Associate Professor with the Department of Electrical Engineering and Renewable Energy, Oregon Institute of Technology, where he is involved in several research projects on renewable energy and grid-tied microgrid systems. He is an Associate Researcher with the Oregon Renewable Energy Center. His research interests include modeling, analysis, design, and control of power electronic devices, energy storage systems, renewable energy sources, integration of distributed generation systems, microgrid and smart grid applications, robotics, and advanced control system. He was a recipient of the Rising Faculty Scholar Award in 2019 from the Oregon Institute of Technology for his outstanding contribution in teaching. He, along with his dedicated research team, is looking forward to explore methods to make the electric power systems more sustainable, cost effective, and secure through extensive research and analysis on energy storage, microgrid system, and renewable energy sources. He is the Senior Member of the Association of Energy Engineers. He is currently serving as an Associate Editor for IEEE ACCESS. He is a registered Professional Engineer in the state of Oregon, USA. He is also a Certified Energy Manager and a Renewable Energy Professional. VOLUME 8, 2020