A Compact Short-Channel Analytical Drain Current Model of Asymmetric Dual-Gate TMD FET in Subthreshold Region Including Fringing Field Effects

A compact drain current model is developed for an asymmetric, dual gate, monolayer <inline-formula> <tex-math notation="LaTeX">$2-D$ </tex-math></inline-formula> Transition metal dichalcogenide (TMD) field effect transistor (FET) in the subthreshold region. The work includes the effect of source to drain tunneling and gate dielectric fringing effects. The model is systematically derived for an asymmetric, dual gate structure. The model developed is also extended into a dual-gate symmetric structure. The characteristic length expression has only physical and dimensional parameters including the contribution of fringing field effects from both front and back gate dielectric. The model is validated with simulation results obtained using NEGF based nanodevice simulators and experimental data of <inline-formula> <tex-math notation="LaTeX">$WSe_{2}$ </tex-math></inline-formula> p-channel FET. Also, transfer characteristics, output characteristics, subthreshold swing and output resistance are compared with reported data in literatures. A close agreement is observed with some disparity arising because of the non-inclusion of back gate fringing effects and source to drain tunneling in their models. The proposed model captures the effects of different high-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> gate dielectric materials and its thicknesses. Impact of temperature is also studied on transfer characteristics. The model is also scalable from ultrashort channel regime to long channel regime. Finally, the model can be applicable not only for TMD materials but other <inline-formula> <tex-math notation="LaTeX">$2-D$ </tex-math></inline-formula> materials also.


I. INTRODUCTION
2-D Transition metal dichalcogenides (TMDs) have attracted a lot of attention to the scientific community because of its interesting properties like natural bandgap, impurity charge free surfaces and atomic scale thicknesses [1], [2].Their properties make it suitable channel materials for ultrascaled technology nodes below 10 nm. Transition metal dichalcogenides are compounds formed by transition metals and chalcogen atoms. There are various TMDs garnering attention recently like MoS 2 , WSe 2 , MoSe 2 , WTe 2 etc. Monolayer TMDs achieve a bandgap of around 1.6-2.0 eV which is suitable for The associate editor coordinating the review of this manuscript and approving it for publication was Anisul Haque. ultra low power applications, thus could potentially solve a major bottleneck for the current Silicon technology.
For circuit exploration purpose, it is essential to develop compact I-V models for TMD based Field effect transistors. There have been several efforts in this direction ever since the inception of these materials. In [3], authors have developed long channel models for TMD FET utilizing drift-diffusion transport based model. In [4], some non-ideal effects like interface traps, mobility degradation and inefficient doping effect are included in the drift-diffusion model. In [5], authors have proposed compact I-V models for 2D material FETs using semiclassical transport based approach including several nonideal effects. However the model is applicable for long channel transistors having channel length around 100 nm. In [6], Taur et. al. have developed short channel models for 2 − D material channel FETs. But the authors did'nt discuss development of compact, closed form expressions for current related to geometric and physical parameters of 2 − D FET. However, in [10], [11], authors have developed the framework for analyzing short channel effects in 2 − D material FETs using generalized scale length approach. Subthreshold I-V model for short-channel TMDFETs is proposed in [7]. In their work, authors have verified the results using a drift-diffusion based simulator. However, in TMD FETs for channel length below 10 nm, transport mechanism is not drift-diffusion based thus their model fails to model short-channel TMDFETs. Also the model developed does'nt include back gate fringing field effects. In [8], author has proposed a short channel model for symmetric TMD FET in the subthreshold region. The model is developed from the short channel model in [6], [10]. The characteristic length expression contains empirical parameters which lacks physical meaning and author has mentioned the inclusion of those parameters solely to fit the numerical simulation results. The derivation of the characteristic length expression is not clearly described and also it underestimates the impact of back gate thickness which will be described later in this paper.
Author has claimed to model down to channel length of 3 nm, however they report characteristic length (λ) varying from (4.05-4.85) nm. Now as mentioned in [10], lowest order scale length can be termed as characteristic length only for channel length preferably above 2λ. So, characteristic length expression mentioned in the paper should have taken higher order expressions for modelling down to 3 nm. Also, such complex expression of characteristic length is highly undesirable as it would limit the development of a compact model. Modeling technique described by [8] does'nt take care of this limitation even though authors report results for channel length down to 3 nm. Also the approach is applicable for selected ranges of dielectric constants of dielectric and channel materials and its thicknesses severely limiting our purpose to develop the compact model for any arbitrary 2 − D TMD FET. Further, at such nanometric dimensions, source to drain tunneling can't be ignored. However this is not taken care of in prior literatures to the best of authors' knowledge.
Principal contributions of our work are as follows: • This work for the first time derives the compact subthreshold model for an asymmetric TMD FET structure including the source to drain tunneling effect and front and back gate dielectric fringing effects. The approach can be smoothly extended to develop the model for a symmetric structure described in [8]. Further the model can be utilized for any arbitrary 2 − D material FET structure.
• Back gate fringing field effect is included in the developed model. Work in [8] does'nt include the impact of back gate fringing field effects, and is only applicable for symmetric TMD FET. In [7], although it claims it includes the fringing field effect but it includes the effect using fitting parameter which underestimates the impact and is only validated with drift diffusion based simulator.
• The developed model is validated using NEGF based simulator, NanoTCAD ViDES [13] and Experimental data [14]. It is compared with the results in [7] and [8] in terms of transfer characteristics, output characteristics, output resistance and subthreshold swing. A close conformity is observed with disparity at shorter channel lengths because of non-inclusion of source to drain tunneling and back gate fringing effects in their models.
• The study has been carried out for different front and back gate dielectric materials i.e. SiO 2 , Y 2 O 3 , HfO 2 , BaO and TiO 2 and thicknesses (i.e. from 2 nm to 6 nm).
• The study has been performed for different channel lengths from 120 nm to 5 nm to verify the applicability of our model in ultra short channel length regime. The work also proves the scalability of our model from long channel to ultrashort channel regime.
• Impact of temperature on transfer characteristics is studied.
• Impact of channel length and dielectric thickness on transfer characteristics and subthreshold swing is also studied.
The paper is organized as follows. In section II, the compact subthreshold current model including source to drain tunneling model and gate dielectric fringing field effects has been methodically derived for both asymmetric and symmetric TMD FET structure. Section III discusses the results in detail. Finally, the conclusions are drawn in Section IV.

II. DERIVATION OF COMPACT SUBTHRESHOLD MODEL
A. ASYMMETRIC DUAL GATE STRUCTURE Fig. 1(a) shows the schematic of the asymmetric Dual-gate monolayer TMD FET device, where, x is the channel direction and, y is perpendicular to the channel. Parameters considered in the model are shown in Table 1. Nourbakhsh et. al. has reported, that tunneling from source to drain of MoS 2 MOSFET does not significantly contribute to transport in sub 10 nm regime due to its high effective mass and large bandgap [12]. Whereas, materials with low bandgap and effective mass will suffer from source to drain tunneling in subthreshold region. So, source to drain tunneling has been included in the proposed model to utilized it for any arbitrary 2−D materials as described in subsection C. Considering an infinitesimal Gaussian enclosure in the 2 − D material channel as depicted in Fig. 1(b), we arrive at the below mentioned expression, Here, field moving into the surface is taken to be positive and coming out of the surface is considered to be nagative. Now, the Gaussian enclosure in front gate dielectric results in, Here, k ch , k fox and k box are the dielectric constants of the TMD channel, front and back gate oxide respectively. Similarly, the Gaussian enclosure in back gate dielectric results in, Here, ξ C,x and ξ C,y are the Electric fields in the channel in lateral and vertical direction respectively. Now, Equation (1) can be simplified to, Here, ξ C,y (y) and ξ C,y (y + y) are the vertical Electric field components on the front and back surface of the 2 − D TMD channel arising because of the Front and back gate bias, the fringe field due to high k dielectric is included in the model by taking the gaussian enclosure in both the dielectrics [7] as shown in Fig. 1(b).
Equation (2) can be simplified to obtain expression of ξ C,y (y) as, Now, as lateral electric field in the channel and the front gate dielectric can be related as, so Equation (5) can be represented as, Here, η F is a model parameter for the front gate dielectric.
Using the same procedure from Equation (3) can be simplified to obtain expression of ξ C,y (y + y) as, As, lateral electric field in the channel and the back gate dielectric can be related as, so Equation (7) can be represented as, Here, η B denotes the model parameter for the back gate dielectric. Now, ξ fox and ξ box are the electric fields on the top of front and back gate dielectric respectively. They can be expressed as, and, Here, ψ c (x) denotes the surface potential of the TMD channel and V gs , V bs , V fb and V fbb are the front gate bias, back gate bias, flat band voltage of front gate oxide and flat band voltage of back gate oxide respectively. Firstly, expression in Equation (9) and Equation (10) are substituted in Equations (6) and (8) respectively. Finally these expressions in Equation (6) and (8) are substituted in Equation (4) to obtain a simplified expression represented as, where, λ is called the characteristic length expressed as, The expression of λ in Equation (12) includes fringing field from both front and back gate unlike the expression obtained in [7] where, fringing field arising out of back gate is neglected. However for a high-κ dielectric in the back side of TMDFET necessitates the inclusion of back gate fringing effect. Parameters η F and η B essentially models the impact of front and back gate on the TMD channel respectively. Also, ψ c,long is the long channel surface potential expressed as, Equation (11) can be solved with the boundary conditions at source and drain side as, ψ c (0) = V bi and ψ c (L ch ) = V bi + V ds as, In this case, surface potential along the channel, ψ c varies only along x-direction because a monolayer TMD channel is considered having channel thickness ∼ 0.65 nm. So it is assumed that potential variation along the perpendicular to channel direction (y-direction) is insignificant compared to the variation along the channel. Here, V bi is the built in potential the source-channel junction and V ds is the applied drain to source bias. V bi can be expressed as, Here, N src is the doping concentration in the source side and N int is the intrinsic carrier concentration in the channel. Both are generally expressed in the unit of cm −2 . Thus the model developed can be utilized for any arbitrary TMD FET having asymmetric gate oxide material and thickness.

B. SYMMETRIC DUAL GATE STRUCTURE
The model developed in the previous subsection can be extended to a symmetric structure having identical front and back gate dielectric material and thickness. The expression of characteristic length, λ can be derived from Equation (12) as, Also, long channel surface potential simplifies to, Here, for symmetrical structure, T fox = T box , k fox = k box , EOTF = EOTB and η F = η B .

C. SOURCE TO DRAIN TUNNELING MODEL
Source to drain tunneling is inevitable for ultra short channel 2-D FETs. The model can be developed from the energy band profile. The conduction band profile of MoS 2 FET has been plotted in Fig. 2. From the figure, following expression can be written as, Now, E b (barrier height) can be written as, The surface potential minima or the conduction band maxima occurs where electric field is zero. So, by using − dψ c (x) dx = 0, at x = l b it is found that, For any arbitrary energy, E, the expressions for intersection points, x s (near source-channel junction) and x d (near VOLUME 8, 2020 drain-channel junction) have been derived as [15], Now, the source to drain tunneling probability (T WKB ) can be evaluated using WKB approximation [16] as in Equation (22), Here, m * , E c (x), E are effective mass of the carrier, conduction band energy and the carrier energy respectively.
The drain to source current due to tunneling is evaluated using Landauer's formula as given in Equation (23), Here, M (E) is the number of the conduction modes for 2 − D materials and can be written as [17], Here, W ch , g s , g v andh are width of the channel, spin degeneracy factor, valley degeneracy factor and reduced planck's constant respectively.

D. DRAIN CURRENT CALCULATION
The subthreshold drain current can be evaluated according to the expression obtained from [9], [10] as, Total drain to source current, I ds can be obtained by using Equations (25) and (23).
Here, W ch is the channel width, k is Boltzmann's constant, T is temperature and µ is the carrier mobility and I d,tun is tunneling current due to the carriers tunneling from source to drain.

III. RESULTS AND DISCUSSION
Our developed model is verified with numerical simulation data obtained using NEGF based nanodevice simulator, Nan-oTCAD ViDES [13] as well as with experimental data of WSe 2 p-channel FET [14]. The parameters considered in this work are mentioned in Table 2. The flatband voltage (V FB ) in this work is taken to be 0.19 V . For the asymmetric structure, we have varied the dielectric constant of the front gate dielectric by selecting various oxides. However, the back gate oxide is considered to be Silicon dioxide (SiO 2 ) and   back gate bias is 0 V . For the symmetric structure, both front and back gate oxides are of the same material and tied to a common bias voltage. The validation of our model against NEGF based simulator is shown in Fig. 3. The model is also validated with the experimental result is shown in Fig. 4   data (as WSe 2 p-FET is chosen), this is because of I ds − V gs characteristics obtained from NEGF simulation and Experimental data enter to region other than subthreshold after V gs = 0.17 V for NEGF simulation and V gs = −0.35 V for experimental data respectively. Fig. 5 (a) and (b) depict the channel potential variation with V gs at V ds = 0.5 V and with V ds at V gs = 0.2 V respectively. The tunneling current, I d,tun with respect to V gs for different materials MoS 2 (E g = 1.8 eV , me = 0.45) [8], GeSe (E g = 1.3 eV , me = 0.2) [18] and WSe 2 (E g = 1.6 eV , me = 0.33) [19] is shown in Fig. 6 (a). Fig. 6 (b) depicts the transfer characteristics of MoS 2 FET at different temperatures. By observing Fig. 6 (b), it can be inferred that Zero temperature coefficient (ZTC) occurs at V gs = 0.14 V . Fig. 7 depicts the comparison of our model against the model available in [7]. It can be observed that our model shows a close proximity with the model of [7] for different channel lengths from 5.9 nm (short channel) to 120 nm (long channel) in the subthreshold region. As the model is developed for the subthreshold region, so V gs is kept below 0.25 V . An insignificant difference in OFF current is  noted for channel length of 5.9 nm. This is observed because back gate fringe field effect has been considered in our model. Fig. 8 confirms that our model can accommodate different dielectric materials. Here, the dielectric materials considered are, SiO 2 (k fox = 3.9ε 0 ), Y 2 O 3 (k fox = 15ε 0 ), HfO 2 (k fox = 25ε 0 ), BaO (k fox = 33ε 0 ) and TiO 2 (k fox = 50ε 0 ). The output resistance (R out ) is a significant parameter for analog applications. Fig. 9 shows the variation of R out with drain to source bias (V ds ). It can be observed that our model and model in [7] are matched till V ds = 0.2 V . This is because our model is valid in subthreshold region with V gs < 0.2 V . Model in [7] overestimates the value of R out for V ds ≥ 0.2 V .
From Fig. 10 it is evident that Model in [7] does not track the variation in back gate dielectric thickness whereas the effect of back gate is included in our model. This is the limitation of the model in [7]. In our proposed model, the characteristics length is increasing with back gate oxide thickness and that will further impact the electrostatics of the device under consideration. The comparison of Characteristic length with [7], [8] is shown in Fig. 11. It is observed that   characteristic length obtained in our model, model of [7] are all below 1.5 nm for different high-κ front gate dielectric cases. Model in [8] clearly is less scalable than others because the characteristic length reported is higher than other cases. Higher-k dielectric reduces the characteristics length for our model and in [8]. This points out the requirement of high-κ dielectric for oxides in ultra short channel regime. Further, an inverse trend is observed for the data reported in [7] pointing the usage of low-k dielectric materials which is not supported by existing literatures. Fig. 12 shows the comparison of transfer characteristics with model reported in [8]. Some deviation is observed for the proposed model in comparison to the data obtained by model in [8] for channel length of 5 nm above a V gs of 0.15 V . However, nice agreement is observed for channel length greater than 5 nm. This deviation happens for short channel length because of the characteristic length expression in our model includes both front and back gate fringing effects which is inaccurately modeled in [8]. Fig. 13 shows a good matching of transfer characteristics for lower V gs (≤ 0.2 V ) and starts deviating for higher V gs and gate oxide thicknesses. As thickness is increasing, our model and model in [8] starts deviating FIGURE 13. I ds versus V gs plot for different front and back gate oxide thicknesses and comparison with model in [8] with HfO 2 as gate oxide having an EOT of 0.31 nm, V ds = 0.4 V and L ch =7 nm.  after certain V gs . It is also observed that the trend in [8] leaves subthreshold region (saturation behaviour is observed) at V gs ≥ 0.15 V and V gs ≥ 0.10 V for T ox = 3 nm and 4 nm respectively.This behaviour is not expected at such a low V gs . In our case, the trend does not show any saturation behaviour, which depicts that TMD FET remains in subthreshold region below V gs = 0.2 V .
A comparison of subthreshold swing (SS) for different channel lengths and oxide thicknesses with Model in [8] is shown in Fig. 14((a),(b)). It shows a good conformity with the model in [8]. The comparison of output characteristics is shown in Fig. 15. A critical observation depicts that our model shows lower output resistance at higher V gs which is because of proper consideration of fringing effect in the model. So the developed model is scalable and we have shown good matching from ultrashort channel length of 5 nm to long channel of 120 nm channel length. However theoretically our model is applicable till 2λ = 3 nm. The model developed is universal as it can be applied for both asymmetric and symmetric gate structure. The model is not only confined to TMD materials like MoS 2 , WSe 2 , MoSe 2 , WTe 2 etc., but also applicable for other 2 − D materials like Graphene, Silicene etc.

IV. CONCLUSIONS
A compact analytical I-V model is presented for an asymmetric, dual gate, monolayer 2 − D Transition metal dichalcogenide field effect transistor in the subthreshold region. The model includes the effect of source to drain tunneling and gate dielectric fringing effects. The model is methodically derived for an asymmetric, dual gate structure. The model developed is well extended into a symmetric dual gate structure also. The characteristic length expression has dependence only on physical and dimensional parameters and includes the contribution of fringing effects from both front and back gate dielectric materials. The model is validated with simulation results obtained using NEGF based nanodevice simulator [13] and experimental data in [14]. Also, transfer characteristics, output characteristics, subthreshold swing and output resistance are compared with reported literatures of both asymmetric [7] and symmetric structures [8]. A close conformity is observed with some disparity arising because of the non-inclusion of back gate dielectric fringing field effects and source to drain tunneling [7], [8]. The model can well adapt to the effects of different high-κ dielectric materials and its thicknesses. The model is shown to be scalable from ultrashort channel regime to long channel regime. Finally, the model is not confined to only 2 − D TMD materials but applicable for any arbitrary 2 − D materials also.