Analysis and Design of Outphasing Transmitter Using Class-E Power Amplifiers With Shunt Capacitances and Shunt Filters

In this paper, a novel outphasing power amplifier (PA) based on class-E amplifiers with shunt capacitances and shunt filters is proposed. The new design provides high drain efficiency for both peak and back-off power levels. A mathematical model for the class-E power amplifier with shunt capacitance and shunt filter is presented. The proposed model enables derivation of load circuit parameters that provide optimum drain efficiency for the peak and back-off power levels using closed form mathematical expressions. Based on this model, an outphasing power amplifier is designed and subsequently implemented using microstrip transmission lines and a GaN HEMT devices. The fabricated power amplifier prototype is optimized for 2.14 GHz and provides drain efficiency of over 60% for back-off power levels up to 8.5 dB. The amplifier demonstrates a 44.3% drain efficiency for 64QAM OFDM modulated signal with 20 MHz bandwidth. Adjacent channel leakage ratio (ACLR) of −39.5 dB and error vector magnitude (EVM) of 0.9 % were achieved after the application of a memory polynomial linearization algorithm.


I. INTRODUCTION
Providing high data throughput and maintaining high energy efficiency are two of the main requirements for modern wireless communication systems. In order to increase channel capacity, signals with high peak-to-average power ratio (PAPR) are being used. However, it is challenging to transmit these signals without nonlinear distortion and low power consumption at the same time. Several advanced power amplifier (PA) structures have been proposed in order to fulfil both the linearity and efficiency requirements: Doherty PA [1], outphasing PA [2], [3] and an envelope tracking transmitter [4]. The first two PA architectures realize the load modulation principle in order to improve transmitter efficiency. Due to the possibility of achieving wide operational bandwidth, the Doherty PAs have gained in popularity over the last decades [5]- [7]. Besides, Doherty PAs have a simple single input single output interface, which makes them an attractive approach to replace single-ended PAs, such as The associate editor coordinating the review of this manuscript and approving it for publication was Rocco Giofrè . class-AB. The main advantage of the outphasing PA is the possibility of driving both the active devices in saturation regardless of the magnitude of the input signal. Therefore, the high efficiency at back-off power level can be easily achieved by appropriate output combiner design, as will be discussed further in this paper. Combined with non-constant envelope input signal techniques and drain supply modulation, the outphasing PA can demonstrate high drain efficiency and power added efficiency (PAE) for wide range of output power levels [8]- [11]. Several techniques have been proposed in order to achieve broadband operation of outphasing PA [12]- [14]. All these features make the outphasing PA an attractive solution for efficient RF transmitters for the 5G communication systems.
The outphasing PA was initially introduced in [2] as a way of improving efficiency of amplitude modulated transmitters. The general structure of the outphasing PA is shown in Fig. 1. It consists of a signal components separator (SCS), two branch amplifiers and an output power combiner. The input signal with amplitude and phase modulation is separated by the SCS into two phase modulated components S 1 and S 2 VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ according to the following equations: where θ is referred to as the outphasing angle and conveys information about the signal magnitude. These two components have a constant magnitude and can be amplified with high efficiency without nonlinear distortion. The two amplified phase modulated signals S 1a and S 2a are added together with the output combiner in order to achieve an amplified replica of the input amplitude and phase modulated signal. Throughout this paper, the branches of the outphasing PA will be referred to as +θ branch (PA1 in Fig. 1) and −θ branch (PA2 in Fig. 1). The same concept is also referred to as linear amplification with nonlinear components (LINC) [3]. Different types of output combiners have been used in outphasing transmitters. All types can be categorized into three general classes: isolated combiners [15], [16], non-isolated combiners [17]- [23], and partially isolated combiners [24]. Isolated combiners contain resistive elements that isolate branch PA outputs from each other. Therefore, each branch PA sees a constant load impedance and very high linearity can be provided. However, as it was shown in [25], isolated combiners demonstrate low average efficiency for signals with high PAPR. The input impedance of nonisolated combiners depends on the outphasing angle and therefore on the level of input signal. This load modulation can significantly improve the average efficiency of the transmitter. However, since these combiners introduce significant nonlinear distortion, digital predistortion techniques (DPD) are often required for these transmitters [26]- [28]. Partially isolated combiners provide a trade-off between nonlinear distortion and linearity and are capable of improving the bandwidth performance of an outphasing transmitter [24].
Among all of the aforementioned classes of PAs, the class-E PA has a compact load circuit and provides high efficiency under a wide range of back-off power levels. Compared to other switch-mode PA classes, such as class-F, the class-E PA has a simple and compact load network which provides the necessary drain load impedance at the fundamental frequency [36]. Consequently, for class-E it is easy to provide wideband operation. Due to these advantages, the class-E PA has drawn the attention of researchers for 5G communication systems [37], [38]. The concept of the class-E amplifier was described in [39]. It was shown that if zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) conditions are satisfied, the power dissipation during the transistor switching is minimized, and drain efficiency is improved. The operation of class-E PA with RF choke was analyzed in [40]. Based on this analysis, in [36] expressions for optimum load values were derived. These expressions were used in [17] in order to analyze the load modulation properties of the class-E PA. However, this analysis is based on one harmonic approximation and is valid for the class-E PA with RF choke.
Mathematical analysis of a class-E PA with finite DC inductance was demonstrated in [41]. It was shown that in order to maintain high efficiency of class-E PA under back-off output power, it is necessary to violate the ZVDS condition while fulfilling the ZVS condition. This analysis was used in order to design an outphasing PA in [21]. A similar approach was demonstrated in [42]. However, voltage waveform slope at the end of the period is used as an input parameter for design, which makes the algorithm difficult to apply when a back-off power level is specified.
Achieving class-E operation with a load network containing shunt capacitance and shunt filter was demonstrated in [43], [44], and the ideal operation was analyzed in [45]. This type of class-E PA enables the incorporation of the device's parasitic capacitance and inductance into the load network. Besides, a class-E PA with shunt capacitance and shunt filter has higher maximum operating frequency, therefore, it has the potential for broadband operation [45]. Building a load modulation transmitter based on a class-E PA with shunt capacitance and shunt filter was demonstrated in [46], where it was used in Doherty PAs. However, no analysis of the load modulation properties of the class-E PA with shunt capacitance and shunt filter has been presented previously in the literature.
In this paper we present detailed analysis of load modulation properties of the class-E PA with shunt capacitance and shunt filter. Firstly, the behavior of the PA for the ideal conditions (when both ZVS and ZVDS conditions are fulfilled) is described. In load modulation PAs, such as outphasing, this operation corresponds to the peak output power. It should be noted, that the peak power solution is very similar to the analysis presented in [44], [45], however, the solution is modified in order to enable extension of the analysis for the back-off power case. Secondly, the waveforms of the PA under back-off power are analyzed. The derived mathematical expressions can be used to identify the optimum load impedance values for the given load circuit parameters and 208880 VOLUME 8, 2020 back-off power level. Finally, the presented analysis is used for designing an outphasing PA.
The remainder of the paper is organized as follows. Section II presents the waveform analysis of class-E PA with shunt capacitance and shunt filter for both ideal operation and back-off power operation. In Section III the proposed mathematical solution is proven by simulation using the circuit simulator Keysight ADS. Section IV presents the application of the proposed technique for the design of outphasing class-E PA. The performance of the manufactured outphasing PA was experimentally measured and the results are presented in Section V.

II. CIRCUIT ANALYSIS
As mentioned in [44], [45], class-E operation can be achieved using the load network configuration shown in Fig. 2(a) and Fig. 2(b). This load network consists of shunt capacitance C p , series inductance L s , shunt resonator L 0 C 0 , DC-block capacitance C b , resistive load R and load reactance jX that can be inductive or capacitive depending on the PA parameters. The DC voltage V cc is supplied to the drain of the transistor either through an RF choke RFC (see Fig. 2(a)) or through the inductance of the shunt resonator L 0 (see Fig. 2(b)). The latter case is preferable since it avoids the need for bulky inductive elements. The operation of the PA can be considered separately in two states: when the switch is on (0 ≤ ωt < π) and when the switch is off (π ≤ ωt < 2π). As in [40], [41], [44], [45] we consider the idealized operation of the PA, which means that: 1) The transistor operates as an ideal switch with zero on-resistance and infinite off-resistance. 2) All the lumped components in the circuit are linear.
3) All the components except the load resistance R are lossless. Throughout this paper we denote: • v(ωt) is voltage across switch in time domain; • v R (ωt) is voltage across resistive load in time domain; • v X (ωt) is voltage across reactive load in time domain; • i C (ωt) is current through the parallel capacitance C p in the time domain; • i L is current through the series inductance L s in time domain; • V R is amplitude of the voltage across the resistive load at the fundamental frequency; • V X is amplitude of the voltage across the reactive load at the fundamental frequency; • ω ≡ 2πf is the fundamental angular frequency. In order to simplify the equations, the following parameters are used: In the normalized form, the conditions for ideal class-E operation ZVS and ZVDS can be written as: As it was shown in [44], the voltage across the switch can be described in the time domain by a second order differential equation. In the normalized form, this equation can be written as: The general solution of (11) can be written as where C 1 and C 2 are constants that do not depend on x, and ϕ is the phase of the voltage across the output load. It should be noted, that in the case r X = 0, the solution (12) coincides with the solution derived in [44]. The constants C 1 and C 2 can be defined from the initial conditions for the moment when x = π. The first condition comes from the assumption that the voltage drop across the switch is zero while the switch is on: At the same time the current through the inductance L s can be expressed as: The expressions for the constants can be written as: where the variables p 1 and p 2 are defined as follows: In order to find the circuit parameters it is necessary to use conditions for ideal class-E operation (9) and (10). Substituting expression (12) along with the expressions for constants (15) and (16), one can achieve a system of two independent linear equations with two unknown parameters p 1 and p 2 . The solution for the system is: In order to derive explicit expressions for load circuit components, it is necessary to consider the drain current when the switch is on. Assuming that the drain efficiency is 100%, one can derive: In order to find values r R , r X and ϕ it is necessary to consider the operation of the PA in the frequency domain at the fundamental frequency as shown in Fig. 3. The normalized voltage magnitude across L s and X can be found as: whereas normalized voltage magnitude across the resistive load R will be: From the first Kirchoff's law for the circuit it follows that However, from the output power definition From (25) and (26) it follows that By performing integration on expression (24) and substituting it into equation (27), one can derive an equation that, along with the equations (19) and (20), form a system of three independent equations with three unknown variables. The solution of this system can be written as: where The values r R and r X in turn define the load impedance: The presented solution uniquely defines load network parameters from the given input parameters: output power P out , drain supply voltage V cc , operating frequency f c and the parameter q. It also can be shown that this solution coincides with the solution presented in [45]. However, as it will be shown in the following subsection, this analytical solution enables extension for back-off power analysis.

B. BACK-OFF OPERATION
Although the ideal load network parameters can be found for the specified output power, in energy-efficient transmitters, such as Doherty or Outphasing, output power changes due to the load modulation. This in turn causes non-ideal class-E operation. In these systems the load presented to the PA changes with time, whereas the values of C p and L s do not alter.
As it was shown in [41], a class-E PA can have very high drain efficiency even when the condition (10) for drain voltage is not satisfied. This means that at the moment when the switch turns on, the initial drain current i L (0) (the last term in (14)) is non-zero. Therefore, the initial condition for normalized drain voltage u at the moment x = π will be dv n (x) dx x=π = q 2 π + 2(r X sin ϕ − r R cos ϕ) Applying the condition (40) along with the zero voltage condition at the moment when the switch turns on, expressions for the constants C 1 and C 2 can be expressed as follows: where the coefficients c ij can be calculated as follows, using the given value of q: 2q sin qπ cos qπ − 1 c 10 = qπ sin qπ + cos qπ − cos 2qπ cos qπ − 1 The DC component of the drain current will be: The first derivative of the normalized voltage dv n dx x=2π in (44) can be found by differentiating the expression (12) with constants defined by (41) and (42). By assuming that the drain efficiency is 100%, P out becomes Therefore, one can derive the first equation for variables p 1 and p 2 : where The second equation can be derived from the condition (9). Therefore, the parameters p 1 and p 2 can be calculated from these two equations as: Once the values p 1 and p 2 have been found, one can define the parameters ϕ, r R and r X from the expressions (28), (37) and (36) respectively. These parameters define the optimal load impedance according to the expressions (38) and (39).
The class-E PA design procedure, operating under a given back-off power, can be outlined in the following steps: 1) From the chosen value q calculate the values p 1 and p 2 for ideal class-E operation using the expressions (19) and (20). 2) Using the calculated values p 1 and p 2 obtain values for constants C 1 and C 2 using (15) and (16). 3) From the calculated values C 1 , C 2 , p 1 , p 2 along with the given drain supply voltage V cc , output power P out and operating frequency f c calculate circuit parameters using (21), (22), (38), (39). 4) For the given back-off power level calculate p 1 and p 2 using (50) and (51). 5) Once the values p 1 and p 2 have been found for the back-off power, the optimum load can be calculated using the same expressions (38) and (39).

III. WAVEFORM ANALYSIS
In order to demonstrate the proposed technique 3 different class-E PA load networks are analyzed in this paper: q = 1.4, q = 1.61 [44] and q = 1.85 [45]. The load networks are designed for the following parameters: f c = 2.14 GHz, V cc = 20 V, P out = 12 W. The load contours are shown in Fig. 4. From the presented curves it can be seen that the resistive part of the load decreases with decreasing output power, which makes the class-E PA with shunt capacitance and shunt filter similar to a current source. The reactive part VOLUME 8, 2020 of the load becomes more inductive for lower output power levels for all values q. The impedance seen by the drain at the fundamental is shown in Fig. 5. Since the shunt filter provides a short circuit for the harmonics, the drain impedance for the second harmonic is purely reactive and does not depend on the output power level, as shown in Fig. 6.  The drain current and voltage waveforms for ideal class-E operation along with waveforms for different back-off power levels are shown in Fig. 7 and Fig. 8. From these waveforms  it can be observed that for lower output power level the first derivative of the voltage at the end of the period is negative, in contrast to the peak power case, where it reaches zero value. This, in turn, causes non-zero drain current at the moment the switch is turned on (see Fig. 7). The performance of the PAs was tested using Keysight ADS simulation tool. As in [44], [45], for the simulation of an ideal PA, the transistor is represented as an ideal switch with on-resistance 10 −3 and off-resistance 10 6 as shown in Fig. 9. The load network consists of lumped elements only. The fundamental load impedance values at the resonator plane are calculated for the peak power and for back-off power levels −3 dB, −6 dB, −9 dB, −12 dB. The output power and drain efficiency simulated in ADS are presented in Table 1. The drain efficiency is defined as the ratio of the power dissipated in the output load to the power generated by the DC voltage source (see Fig. 9). From the presented results one can see that even for the ideal case, the efficiency of the PA decreases for back-off power level. The reason for that is harmonics, that are generated due to the very quick change of the drain current at the moment x = 0.
It should be noted, that since real transistors do not operate as ideal switches, the obtained values cannot be used directly in the final PA design. However, impedance values calculated using the presented technique can be used as an initial    approximation for further optimization using real transistor models. For example, a simulation of a class-E PA based on a GaN HEMT CGH40010F transistor model is shown in Fig. 10. Using a GaN HEMT transistor model enables accurate simulation of PA parameters without load-pull measurements of the device. In order to drive the transistor in a switch mode, a matching circuit has been added to the input of the device. This circuit provides input device impedance transformation (Z in ≈ 3.2 − j4.8 Ohm) to the standard 50 Ohm line impedance. The gate bias voltage is supplied through a 10 Ohm resistor, which provides better stability. The shunt capacitance C p is replaced with the packaged device output capacitance, which is approximately C ds ≈ 1.3 pF. The optimum series inductance value L s is provided by proper choice of microstrip line segment at the device drain taking into account the device bondwire inductance. The lumped component resonator L 0 C 0 is replaced with two microstrip line sections with electrical length of 45 • . The value q = 1.57 is chosen in order to match this value with the optimum parallel capacitance value. The load values that correspond to the maximum output power 12 W as well as back-off power levels are presented in Table 2.

IV. OUTPHASING PA DESIGN
As it was shown in the previous sections, the class-E PA with shunt capacitance and shunt filter can provide high drain efficiency across a wide range of output power levels. This property can be used in load modulation transmitters, such as the outphasing PA. In this section the application of the proposed approach to outphasing PA design is demonstrated. The operating frequency of the PA is 2.14 GHz, the peak power P out = 15 W, PAPR = 8.5 dB. Both class-E PAs are built using a GaN HEMT transistor CGH40010F. The output capacitance of this device, C out ≈ 1.3 pF, can be used as the shunt capacitance for the PAs, and the output inductance, L out ≈ 0.65 nH, should be incorporated into the series inductance of the output circuit. It should be pointed out, that the output capacitance of a GaN HEMT device decreases with the rise of drain-source voltage. If this dependence significantly affects the performance, a transistor model that takes into account output capacitance variation can be used [47], [48]. However, if the tracking of the optimum load impedance is provided, the drain-source voltage variation is not significant for the peak and back-off power levels, as shown in Fig. 8. Therefore, in this work the output capacitance is assumed to be constant.
Using the algorithm presented in Section I, the following circuit parameters were derived: L s = 1.625 nH, C p = 1.3 pF. The load impedance for peak output power Z L,ideal,peak = 15 + j0.5 Ohm, and for -8.5 dB back-off level Z L,ideal,BO = 4.65 + j16.53 Ohm. These impedance values were used as an initial approximation for the circuit shown in Fig. 10. After optimization of drain efficiency the following load impedance values were found: Z L,peak = 16 − j1.5 Ohm and Z L,BO = 3.12 + j11.7 which provide drain efficiency of 85% and 68% respectively.
As shown in Section I, the outphasing PA separately amplifies two phase modulated signals (see Fig. 1). In order to restore the original signal, these two amplified signals must be recombined using one of the combiner types. The Chireix combiner for outphasing power amplifiers consists of two quarter wavelength transmission lines with characteristic impedance Z c and two reactance compensation elements C comp and L comp (see Fig. 11). In the case when the magnitude of the input signals are equal, the input impedance of the Chireix combiner branches at the operating frequency f c can be found from the expressions: where θ is outphasing angle defined by equation (3). The reactance compensation elements C comp and L comp are adjusted in order to provide zero input reactance at the outphasing angle that corresponds to a specific back-off power level. The input impedance of a quarterwave Chireix combiner shown in Fig. 11 for outphasing angles between 0 • and 90 • is shown in Fig. 12. From these plots it can be  seen that Chireix combiner provides complex conjugated impedance for +θ branch and −θ branch. For this reason, for symmetrical outphasing PA it is impossible to provide ideal tracking of load modulation contour for both branch PAs. Therefore, the task of Chireix combiner synthesis is to provide the optimum value of input impedance at peak power and back-off power level for the both +θ and −θ branches. The outphasing angle for the peak and back-off power levels can be defined from the following expressions: θ BO = arccos 10 P BO 20 (54) In order to provide the required impedance values a transmission line topology was used as shown in Fig. 13. The two class-E PAs were simulated based on the Cree GaN HEMT device model with microstrip line input and output circuits (see Fig. 10). The input circuit provides matching of the device input impedance (Z in ≈ 3.2 − j4.8 Ohm) with 50 Ohm power source. The output device capacitance is used as shunt capacitance, whereas series inductance and resonator are implemented using microstrip transmission lines. The lines of the resonator have 45 • electrical length providing short circuit condition for the second harmonic. The drain voltage is supplied to the device through the inductive line of the resonator.
The outputs of two class-E PAs are connected to the inputs of the Chireix combiner through a T-shaped impedance transformer, as shown in Fig. 13. The right box demonstrates a Chireix combiner based on quarterwave transmission lines. The reactance compensation at the back-off power level 8.5 dB is provided by the open and short transmission line sections. From the expressions (52) and (53) it follows, that the quarterwave line combiner provides the following impedance for both branches: Z CH,peak = 58.22 Ohm for the peak power (θ = 22.1 • ) and Z CH,BO = 354 Ohm for the back-off power (θ = 67.9 • ). In order to transform the values Z CH,peak and Z CH,BO to the previously found required values Z L,peak and Z L,BO , two T-shaped transformers have been added, as shown in the left box in Fig. 13. Along with the impedance transformation, the open stubs of the transformers provide the third harmonic suppression improving the overall efficiency. It should be pointed out, that based on the required impedance values other combiner synthesis techniques can be used, such as the one proposed in [17].
The calculated structure was optimized using Keysight ADS simulation software. The transmission lines were simulated as microstrip lines on Rogers RO4350B substrate with thickness 0.762 mm. For drain efficiency simulation, the inputs of the outphasing PA were excited with two single tone signals with phase difference defined from back-off power level using expression (3). The simulated drain efficiency and PAE are presented in Fig. 14 and 15 respectively along with measured results. The simulated fundamental load impedance at the resonator plane is shown in Fig. 16. From these plots one can see a slight deviation of the simulated load impedances from the calculated load impedances for a single-ended PA. The reason for this deviation is significant influence of the microstrip line width change at the resonator plane. Therefore, the final tuning of the outphasing PA is always required.

V. IMPLEMENTATION AND MEASUREMENT RESULTS
The optimized outphasing PA was implemented using Cree GaN HEMT CGH40010F transistors and Rogers RO4350B substrate. The input and output load circuits were constructed on 0.762 mm thick Rogers RO4350B substrate with dielectric constant 3.48 and dissipation factor 0.0037 (see Fig. 17). The setup for output power and efficiency measurement consists of a dual-path transmitter board TSW30SH84EVM, linear driver amplifiers and a Rohde&Schwarz NRP output power meter.
Two single-tone signals were generated at the frequency 2.14 GHz from the transmitter board. The phase difference between the transmitted signals was defined by the back-off power level according to (3). The two signals were preamplified by the linear amplifiers to the level +30 dBm in order to drive both branch PAs in class-E mode. The power of the output signal was measured at the operating frequency using the power meter. For the measurement the both transistors VOLUME 8, 2020   were biased in order to achieve a quiescent current of 30 mA. For the transistors used in this work the achieved bias voltages were −2.71 V and −2.61 V.
The dependence of the PA drain efficiency and PAE on the output power level is presented in Fig. 14 and Fig. 15 respectively. From these plots it can be seen that the fabricated PA provides more than 60% drain efficiency for back-off power levels of 8.5 dB. It also can be seen, that close to the peak power the ADS simulated drain efficiency is higher because the simulated model does not take into account losses in the substrate dielectric as well as metal loss. However, at back-off power level the ADS harmonic balance simulator experiences convergence issues. For this reason,  the simulated results at deep back-off may deviate from the measured results. The frequency dependence of drain efficiency at peak and back-off power levels is presented in Fig. 18. It can be seen, that the back-off efficiency decreases quickly with frequency offset. The reason for that is the significant difference between the input impedance of the quarterwave combiner and the required back-off load impedance for the class-E PA. It should be pointed out, that since two constant envelope signals are used for active devices excitation, the PA provides low gain at back-off. Consequently, the PAE is much lower at back-off compared to drain efficiency. This issue can be overcome by using non-constant envelope signals, as has been demonstrated in [8].
A signal with 64QAM OFDM modulation scheme, 20 MHz bandwidth and 8.8 dB PAPR was used in order to test the linear performance of the fabricated PA. The test setup is shown in Fig. 19. The signal separation component was implemented in the digital domain, and two outphasing signal components were generated using TSW30SH84EVM transmitter board. Both signals were preamplified with EMPOWER driver PAs and supplied to the inputs of the fabricated outphasing PA. The output signal was attenuated and captured with a Rohde&Schwarz signal analyzer and processed in the digital domain. The spectrum of the output signal is presented in Fig. 21. Because the two input signals have constant envelope, the nonlinearity is mainly caused by phase distortion. A memory polynomial digital predistortion technique was applied in order to linearize the output signal at the frequency 2.14 GHz. It is worth mentioning, that the nonlinear behaviour and the DPD algorithm can be tested using Keysight ADS-Ptolemy cosimulation tool, if a  simplified model of the active device is used [49]. However, if an outphasing PA is modelled using real GaN HEMT model, simulation with a complex modulated signal may require considerable computational resources. The dependence of the normalized output signal magnitude upon normalized input signal magnitude is shown in Fig. 20. From these plots one can see, that significant distortion occurs for low signal level. The main reason of the PA nonlinearity is the outphasing angle distortion caused by the two class-E amplifiers. Since the outphasing angle is related to the signal magnitude, as defined by (3), the magnitudes of the output signal are different from the input signal magnitudes before DPD is applied. Power spectrum and constellation of the output signal after linearization are shown in Fig. 21 and 22. The achieved drain efficiency with modulated signals is 44.3% and PAE is 26% whereas the measured ACLR of the output signal is -39.5 dB. It should be noted, that the drain efficiency can be improved by using crest-factor reduction techniques, and the PAE can be increased by using input signals with non-constant envelope. The comparison of the demonstrated outphasing PA with some of the state-of-the-art outphasing PAs is presented in Table 3.

VI. CONCLUSION
A theoretical analysis of load modulation properties of the class-E PA with shunt capacitance and shunt filter is presented. The proposed analysis was used to find the optimum values of the class-E PA load in order to maintain high drain efficiency. The ideal simulation demonstrated drain efficiency over 99% for back-off power levels from 0 to 12 dB. It has been shown that for back-off power operation the zero voltage derivative switch condition is violated while the zero voltage switch condition is still fulfilled. The proposed analysis has been used in order to design an outphasing class-E PA. The designed PA was fabricated using a GaN HEMT transistor and microstrip transmission line topology on Rogers RO4350B substrate. At center frequency 2.14 GHz the fabricated PA demonstrated over 60% drain efficiency across back-off power range 0 to 8.5 dB. The back-off efficiency remains over 40% across over 100 MHz bandwidth. For a 64QAM OFDM modulated signal with 20 MHz bandwidth and PAPR of 8.8 dB the fabricated PA demonstrated 44.3% drain efficiency. Applying a memory polynomial algorithm EVM of 0.9% and ACLR of −39.5 dBc were achieved.
RONAN FARRELL (Member, IEEE) received the B.E. and Ph.D. degrees from University College Dublin, in 1993 and 1998, respectively. He worked with ICI/Zeneca Chemicals, from 1993 to 1995, and with Parthus Technologies, from 1998 to 2001, as a Mixed Signal ASIC Designer. In 2001, he joined Maynooth University, as a Lecturer, and was subsequently promoted to a Professor, in 2016. He has served as the Director for the Callan Institute for Applied ICT, from 2008 to 2015, where he has been serving as the Head of the Department of Electronic Engineering, since 2012. In 2004, he became the SFI Theme Leader for radio frequency electronics research within the Centre for Telecommunications Value-Chain Driven Research (CTVR) and the SFI CONNECT Centre for Telecommunications. He has published more than 100 peer-reviewed articles. He holds three patents and licensed technology that has led to the spin-out three companies. His personal research interests include wireless system design, electronics and radio systems, and technology transfer and innovation.
JOHN DOOLEY (Member, IEEE) received the Ph.D. degree in electronic engineering from University College Dublin, Ireland, in 2008. He is currently an Assistant Professor with the Department of Electronic Engineering, National University of Ireland, Maynooth. He is also a Funded Investigator of Science Foundation of Ireland (SFI) CONNECT Centre for Telecommunications. His research interests include cluster around signal processing and applications to high frequency circuits with a current focus on power efficiency optimization for wireless communications devices, and digital compensation techniques for terrestrial and satellite communication systems. VOLUME 8, 2020