Voltage Source Converters Connected to Very Weak Grids: Accurate Dynamic Modeling, Small-Signal Analysis, and Stability Improvement

The interfacing of the vector-controlled voltage-source converters (VSCs) into weak grid (WG) systems can induce severe instabilities. This is attributed to interactions between the vector control of the VSCs and the high impedance of the WG. The weak connection limits the amount of active power that can be injected by the VSC to the WG. In this work, the small-signal analysis is used to derive; first, a transfer function that helps to design the controller of the VSC output voltage based on the VSC-WG accurate dynamics; second, the full-order state-space model of the VSC-WG system. A modal analysis is then conducted to develop the participation factors to characterize the influencing states on the dominant modes of the system, followed by a sensitivity analysis to evaluate the influence of the vector control gains and other parameters on the dominant modes. The results of the modal analysis confirm that instabilities at the nominal power are inevitable for VSCs connected to very weak grids (VWGs). Inspired by this shortcoming, a novel compensation method is proposed to mitigate the dynamic instability of VSCs connected to VWGs. Finally, several offline time-domain simulations and hardware-in-the-loop (HIL) real-time experiments are conducted to verify the validity of small-signal analysis, validate the effectiveness of the proposed compensation method; and investigate the performance of the system under challenging scenarios such as sudden variations in the phase angle of the grid.


I. INTRODUCTION
The growth of energy demand, environmental and economic problems related to fossil fuels, power grid limitations, and economic incentives rising from electricity market are among the reasons behind the adoption of the distributed generation (DG) systems to support and eventually replace the conventional power plants [1]- [3]. DG units often utilize clean energy sources such as fuel-cells and renewable energy resources (RESs) such as hydro, wind, and solar energy.
The associate editor coordinating the review of this manuscript and approving it for publication was Sze Sing Lee . Therefore, they can provide clean energy for remote or dispersed areas and locations [1], [3].
The two-level three-phase voltage source converters (VSCs) are the state-of-the-art technology to interface DGs into the power grid due to the high switching frequency capability and the ability to regulate bidirectional active and reactive powers independently [1]- [4]. In the context of grid-connected VSCs, the conventional control method which is widely accepted in the industry is the vector control (VC) [1]- [4]. Conventionally, the VC scheme is implemented in the direct-quadrature reference frame (dq-RF) which is synchronous with the phase angle of the point of common coupling (PCC) voltage, and hence a phased-locked loop (PLL) is employed to generate the synchronization angle [1], [4]. If the equivalent impedance between the power grid and the PCC is negligible, the PCC voltage magnitude and frequency can be assumed to be constant, and hence the control of the VSC can be designed independent of the grid parameters. In this situation, the grid is known as a stiff grid (SG). However, if the equivalent impedance is not small enough, the previous assumption is not valid anymore as the PCC voltage exhibits fluctuations, especially during transient conditions. Moreover, the VSC and the grid dynamics become undesirably coupled [5]. In this case, the grid is known as a weak grid (WG). The grid impedance is mainly dictated by the long transmission lines and low power transformers [7]. Since wind farms and photovoltaic units are installed in locations far from the load centers [8], [9], the integration of DGs usually occurs in a WG infrastructure. Moreover, the WG impedance might have a wide range of variations due to faults, loading conditions, and grid reconfigurations by the operator [7], [9]- [11]. To quantify the grid strength or stiffness, the short circuit ratio (SCR) is utilized which is defined as the ratio of the grid short circuit level at the PCC to the rated dc power of the VSC [11]. A grid is considered a very weak grid (VWG) when SCR = 1.
In the technical literature, several issues are reported due to the interaction dynamics between the VSC and the WG [5]- [32]; (1) Low-frequency resonances that interact with the VC of the VSC which might induce instability under the VWG conditions; (2) Instabilities due to the PLL dynamics especially in the VWG conditions; and (3) Limited active power transfer under the weak conditions. In the literature, many control methods discussed in the following have been proposed to enhance the integration of VSCs to WGs.
The first method is to modify (shape) the PLL control loop used for the VC method by reducing its bandwidth [12]- [16]. The reason is that a high PLL bandwidth increases the negative real-part of the converter output impedance which decreases the overall system damping [15], [17], [18]. Therefore, decreasing the PLL bandwidth improves the stability of the interaction dynamics between the VSC and the WG, which in turn, increases the maximum power capacity of the VSC. However, this method often limits the transient response of the system [19]. Moreover, SCR = 1.25 is the maximum stable condition which is obtained for the VSC-WG system in previous works. However, the instability problem of the VSC-WG systems at SCR = 1, which is the worst-case scenario [24], does still exist.
The second method, as addressed in [7], [19]- [22], is to change the magnitude or phase angle of the VSC output impedance by adding auxiliary feedforward loop(s) to the current control path of the VC. However, the minimum SCR level studied in all these cases equals two. Another common feature in most of these methods is that they change the steady-state response of the VSC by modifying the VSC output impedance as an attempt to enhance the stability of the VSC-WG system.
The third method, as discussed in [8], [9], [23], is to eliminate the conventional PLL instead of dealing with its negative effect on the system stability by replacing the VC method by the power synchronization control (PSC). The PSC is a new concept in controlling the VSC output power in grid-connected applications, where the VSC is controlled to imitate the characteristics of a synchronous machine. The paramount advantage of the PSC method is that the VSC does not face any limitation to inject the active power into the VWGs. However, as the ac current is not controlled directly in the PSC, the performance under fault conditions is compromised. Therefore, there is still a great interest to improve the conventional VC method to adapt to the VWGs and maintain the direct current regulation.
Another variant of the VC method is introduced in [5] where the inner current control (CC) of the VSC is replaced by a voltage controller while the PLL is preserved in the control structure. In this case, the active and reactive power controls are the outer loops of the overall control system. However, similar to the PSC, there is no direct control on the VSC current. Moreover, the stability of the system under study has been verified at SCR = 3 which is not close enough to the worst-case scenario. An improved version of the VC strategy is proposed in [24], where the classic outer loop is modified by additional four decoupling gains based on the gain-scheduling technique. The VSC shows a stable performance at SCR = 1. However, the control design requires lookup tables to schedule eight control parameters following the operating point variation. Therefore, there is still a need for a simpler VC-based method to improve the VSC-WG system stability in the VWG conditions [25].
Inspired by the shortcoming of the previous works to present a simple method to mitigate the instability problem of the VC-based VSC in the VWG conditions, a simple active compensation method is proposed in this work that can be easily integrated with the existing VC scheme. The proposed method does not require any change in the VSC control parameters. Also, upon using the compensation method, the steady-state measures of the VSC remain unchanged. Moreover, it is shown that the stability region of the VSC-WG system is increased to SCR = 1 which is the worst-case scenario. The contributions out of this work are summarized as follows.
• Implementation of the compensated VSC-WG system to achieve a stable performance at SCR = 1, i.e., the VWG condition.
• Derivation of an accurate analytical transfer function of the PCC dynamics, which can be used for designing the PCC control system using single-input-single-output (SISO) control tools.
• Derivation of the small-signal state-space full-order model of the vector controlled VSC-WG system augmented with the compensation method where the influence of the ac voltage control (AVC), the PLL, the CC, and the dc-link voltage control (DVC) is considered. VOLUME 8, 2020 • Performance comparison of the VSC-WG systems with and without the proposed active compensation method in terms of the dynamic response, the steady-state response, and the small-signal stability. The rest of the paper is organized as follows. In Section II, the mathematical model of the VSC-WG system and the controllers are introduced; followed by a discussion of the tuning of the controllers parameters. Section III presents the small-signal model of the VSC-WG system followed by extensive modal analysis under the VWG conditions. In Section IV, the modeling and design of the proposed active compensation method are discussed. Section V provides the large-signal simulation results. The experimental verification of the proposed method is presented in Section VI. Conclusions are presented in Section VII. Fig. 1(a) shows the VSC-WG system which includes a VSC with the nominal dc power P n and an LC filter at the ac-side with a series resistance r d as a passive damping [33]. The VSC is connected to an ideal voltage source, which emulates the power grid, at the PCC via a step-up power transformer and the grid impedance, modeled by a lumped RL impedance. A generic dc source, modeled as a dc current source, in parallel with a dc capacitor is interfaced by the VSC at the dc-link. The grid is assumed strong enough so that it can be modeled by a voltage source with a constant magnitude V g and a constant frequency ω g . It follows from the definition of SCR that

II. DYNAMIC MODELING OF THE VSC-WG SYSTEM
where r g and L g are respectively the grid resistance and inductance. The complete system parameters are depicted in Appendix A. The VSC is controlled by the VC scheme. The VSC control system is developed in the dq reference frame (dq-RF) which rotates synchronously with the converter angle θ vsc . As shown in Fig. 1(b), the PLL provides the required angle θ vsc for the VSC control system by synchronizing the VSC to the PCC voltage. The equations describing the VSC-WG system in the following parts are written in the dq-RF. All equations are expressed in the frequency domain, wherein s represents the Laplace operator. The dynamics of the VSC, CC, PLL, DVC, and AVC are modeled in the following subsections.

A. MATHEMATICAL MODEL OF THE POWER CIRCUIT
Based on Fig. 1(a), the mathematical models of the grid impedance and the LC filter are given as where Z f (s) = r f + sω g L f and Z g (s) = r g + sω g L g are the impedances of the filter inductor and grid impedance, respectively.

B. CURRENT CONTROL
The block diagram of the CC loops, which is the innermost control loop, is shown in Fig. 2 where u d and u q are the control inputs. As shown in Fig. 2 where the second and third terms are added to decouple the d-and q-axis closed-loop dynamics and reject the disturbances, i.e., v od and v oq [4]. If the PWM dynamics are neglected and the fundamental components of the terminal voltage is considered, the following holds [4].
Applying (6)-(8) into (2) results in the following transfer function for the CC loops.
Neglecting the power losses in the VSC switches, the dc power P dc is equal to the instantaneous active power at the VSC terminals in Fig 1(a), which in turn, is the sum of the instantaneous power corresponding to the LC filter and the active power of the VSC injected into the grid, P ac . Therefore, the following can be written [4].
shows the block diagram of the DVC loop based on (10). Due to the PLL, discussed in the sequel, v oq is zero in the steady state. Therefore, (10) can be linearized into where is the transfer function from i fd to v dc and 1 (s) is a linear function showing the effect of the disturbances, i.e., i dc , i fq , v od , and v oq . As Fig. 3

D. PHASE-LOCKED LOOP MODEL
The PLL, shown in Fig. 4(a), is based on tracking the angle of the PCC voltage by regulating v oq to zero as given by where ω vsc and θ vsc = ω pll t + θ vsc0 are, the VSC frequency and phase angle generated by the PLL, respectively; ω g and θ g = ω g t + θ g0 are the frequency and the phase angle of the grid voltage, respectively; δ is the phase angle difference; and G pll (s) = K pω + K iω s −1 is the PI compensator. The grid voltage v g can then be decomposed into dq components on the dq-RF as where v g is the magnitude of the grid voltage. Substituting for v oq in (15) from (3) and then substituting for v gq from (18) in the result gives the nonlinear dynamics of the PLL as where the second term in the right-hand side shows the effect of the grid impedance on the PLL dynamics. If the grid impedance is small, i.e., Z g (s) ≈ 0, then v od ≈ v gd ≈ θ and δ ≈ 0 in the steady state. If the grid frequency is constant, then (19) can be linearized as where 2 (s) is a linear function showing the effect of the disturbances ω vsc , i od , and i oq , which are yielded from the nonzero grid impedance. Ignoring the disturbances in (20), the small-signal dynamics of the PLL control can be obtained as shown in Fig. 4(b). However, the overall dynamics of the θ vsc is significantly affected by the grid disturbances under the WG condition. VOLUME 8, 2020

E. INFLUENCE OF THE CONVERTER MODELING ON THE AC VOLTAGE CONTROL 1) ACCURATE MODELING
In grid-connected applications, in addition to injecting the active power to the grid, the VSC is usually responsible for either injecting the reactive power or regulating the PCC voltage magnitude. When connected to the WG, the latter application is more common [9], [24]. Since v oq is regulated to zero by the PLL, the regulation of the PCC voltage is limited to v od . Similar to the CC loop in Part B, an AVC loop is shown in [3] where the feedforward terms are introduced to reject the output current disturbances, i.e., i od and i oq in (4), and derive the decoupled SISO outer control loops in the dq-RF. However, this method cannot be applied to the VSC-WG system since the DVC block regulates the value of i ref fd . Also, v oq is set to zero by the PLL. Therefore, a different method is adopted here for the AVC, which is originally used to control the PCC voltage in the STATCOM applications [4], as follows. Linearizing (3) where v gd and v gq are obtained by replacing δ in (17) and (18) from (16) and linearizing the results; and ω vsc and θ vsc are given in terms of v oq by perturbing (15). Moreover, considering the current of the ac filter capacitor i c as a negligible portion of the inductor current i f [34], then i fd ≈ i od and i fd ≈ i od . After some mathematical manipulations, v od and v oq are obtained as functions of i fd and i fq from (21) in the following. where In [4], i fd is neglected because the VSC injects zero active power to the grid in the STATCOM applications. Therefore, further treatment is needed to include the effect of i fd in this work. Perturbing (14) and rewriting the equation in terms of i The AVC is designed to have a much smaller bandwidth compared with the CC loop. Therefore, i fd ≈ i ref fd in the time scale of the voltage dynamics. Thus, v dc in (11) can be replaced by its equivalent in (26) as a function of i fd . Ignoring i dc as a disturbance, the result can be rearranged to express i fd as (27) where Using the equivalent expression for v od and v oq , given by (22) and (23), respectively, in (27) then i fd can be expressed in terms of i fq after a long manipulation as (29) where Finally, replacing i fd in (22) by its equivalent in (29), the current-to-voltage transfer function T ac iv (s) is deduced as 5 shows the control block diagram of the PCC voltage, where, G v (s) = K pv +K iv s −1 is the PI compensator employed to regulate v od ; and u cp is a compensating signal that is discussed in Section IV. As shown, a negative gain is added to the forward path to preserve the closed-loop stability. According to 2) APPROXIMATED MODELING According to (20), θ vsc and ω vsc are functions of i od and i oq . Therefore, their transient excursion can be ignored if i od and i oq change with a sufficiently slow rate [4]. This means that ω vsc ≈ θ vsc ≈ 0 and, since the grid frequency is assumed fixed, δ ≈ 0. Consequently, v gd ≈ v gq ≈ 0 according to (17) and (18). This condition holds assuming the AVC and DVC dynamics are considerably slower than the CC dynamics. With these assumptions in place, (21) simplifies into: Repeating the same procedure in (22)-(32) results in the following. where It is shown in Section V that using the accurate modeling of the PCC voltage dynamics results in small-signal voltage responses that closely match the large-signal transient responses of PCC voltage at different values of the PLL bandwidth. On the contrary, the small-signal responses yielded from the approximate model, which is widely used in the literature for the AVC design [4], [24], [29], shows a discernable discrepancy between the small-and large-signal transient responses and this difference increases by increasing the PLL bandwidth. Therefore, it is important to obtain an accurate SISO transfer function for the PCC voltage dynamics if the control design optimization is the objective.

F. DESIGN OF THE VSC CONTROLLERS
As suggested by [4], the bandwidth of the CC loop T c (s) is 10% to 20% of the converter switching frequency. The AVC and DVC loops are also considerably slower than the current loop. To this end, the corresponding control gains are selected to assign a bandwidth equal to 17% of the switching frequency to the CC loop and bandwidths equal to 14 % and 12% of the CC bandwidth to the DVC and AVC loops, respectively. In the latter, the stability of the closed-loop system imposes the maximum permittable degree. The closed-loop bandwidth of the PLL is a trade-off between the filtering characteristics and fast responses [35]. In order to meet a fast tracking and filtering characteristics, the bandwidth of PLL is usually in the range of few tens of Hz [36]. Further, the PLL bandwidth in the grid-connected applications should be smaller than the grid nominal frequency to reject the second and sixth order harmonics [4]. However, it should not be too small so that the PLL tracks fast changes in the PCC voltage following the output power or the grid impedance variations [4].

III. SMALL-SIGNAL STABILITY ASSESSMENT OF THE VSC-WG SYSTEM WITHOUT ACTIVE COMPENSATION
A small-signal model of the VSC-WG system without active compensation (i.e., u cp = 0 in Fig. 5) is developed in the form of the state-space equations by linearizing (2)  is given by where ''∼'' denotes a small deviation in variables and X uc is the state vector as given by and A uc is the state matrix as given in Appendix B.

A. PARTICIPATION ANALYSIS
The relative participation of different states in the dominant eigenvalues (modes) of the A uc matrix in (39) is evaluated using the participation factor (PF) measure [37]. The relative PFs of the states are calculated for two cases of connection to a SG at SCR = 10, and a connection to a VWG at SCR = 1.
The PF results are summarized in Table 1. As shown, in the case of the SG, there are two real stable eigenvalues, λ 1 and λ 2 , which mainly corresponds to the PLL and control states of the PCC voltage, respectively. However, in the case of the WG, there are two real stable eigenvalues, λ 1 and λ 4 , which are mainly affected by the states of the PLL and the DVC, respectively. Also, there is a pair of unstable complex eigenvalues, λ 3−4 , which corresponds to the states of the grid impedance, PLL, DVC, and AVC. This shows that the cross-coupling between the states of the VSC control system and the WG impedance is the primary source of instability in the VSC-WG system. In addition, there is a pair of stable complex eigenvalues, λ 5−6 , which correspond to the states of the PLL, dc-link, and the grid impedance similar to λ 3−4 . As will be shown, this pair can induce significant progress toward the imaginary axis following variations in the control VOLUME 8, 2020 gains. Therefore, they can be responsible for introducing oscillatory unstable modes to the system dynamics. Fig. 6 shows the location of the dominant eigenvalues of A uc under different values of P ac . As shown, by changing P ac from 0.35 to 1 pu, λ 3−4 have considerable progress toward the imaginary axis while λ 1 does not show any noticeable change and λ 2 departs slightly from the imaginary axis. Therefore, the stability of the VSC-WG system decreases as the value of P ac increases. Moreover, the VSC-WG system is not stable for P ac > 0.84 per-unit (pu.), which corresponds to SCR < 1.2. Fig. 7 shows the trajectory of the dominant eigenvalues when the LC filter damping resistance r d changes from 0 to 0.6 under the nominal power condition, i.e., SCR = 1. By increasing the passive damping, it is possible to shift λ 5−6 to the stable region. However, λ 3−4 is almost unaffected by the passive damping resistance and hence it is not possible to stabilize the system at the nominal power level. Clearly, the origin of the instability is not the ac filter resonance.

3) INFLUENCE OF THE PLL CONTROLLER
The effect of changing the PLL control gains on the dominant eigenvalues is shown in Fig. 8. As shown, by multiplying (K pω , K iω ) by a gain of 1 to 10, the modes λ 3−4 progress extensively toward the imaginary axis. Initially, the modes are located in the stable region where the PLL bandwidth  (ω pll ) is equal to 2.3 Hz. By increasing the PLL gains, λ 3−4 progress towards the imaginary axis and enter the unstable region at ω pll = 2.8 Hz which is noticeably smaller than the grid nominal frequency, i.e., 60 Hz. Therefore, for a PLL with extremely limited bandwidth, the VSC-WG system can be stable. However, limited bandwidth of PLL hinders the excursion of the frequency during transients [4] which, in turn, slows down the response time of the VSC to the variations in the DG power that are typically fast. This effect is also in an agreement with the PF values given in Table 1 for λ 3−4 where,δ andṽ c oq are the states related to PLL. Therefore, there is a trade-off between the VSC-WG system stability and the fast dynamic response.

4) INFLUENCE OF THE DC-LINK VOLTAGE CONTROLLER
The effect of changing the DVC gains on the dominant eigenvalues is depicted in Fig. 9. As shown, λ 3 and λ 4 are initially real with positive values. Then, by multiplying (K pdc , K idc ) by a gain of 0.28 to 1.23, the eigenvalues relocate until they merge and turn into the complex pair λ 3−4 , yet, still in the unstable region. This observation is also in an agreement with the PF values given in Table 1 where the states related to the DVC show a considerable participation in λ 3−4 . Further, the bandwidth of the DVC (ω dc ) increases from 29.3 to 86.9 Hz which is equal 6% to 17% of the CC bandwidth. Further increases of the control gains do not show a considerable influence on the system stability.

5) INFLUENCE OF THE AC VOLTAGE CONTROLLER
The effect of changing the AVC gains on the dominant eigenvalues is depicted in Fig. 10. According to Fig. 10(a), similar to changing DVC gains, λ 3 and λ 4 are initially real values and, by multiplying (K pv , K iv ) by a gain of 0.08 to 1.05, a relatively large relocation occurs before merging and turning into a complex pair λ 3−4 , yet, still in the unstable region. This observation is also in an agreement with the PF values given in Table 1. Further, the bandwidth of the PCC closed-loop system (ω pcc ) increases from 0.6 to 6.6 Hz and so λ 5−6 progress extensively toward the unstable region as shown in Fig. 10(b).

IV. PROPOSED ACTIVE COMPENSATION OF VSC-WG
From Section III, it is concluded that without compromising the PLL closed-loop bandwidth, i.e., having the PLL with slow response time, it is not possible to preserve the stability of the VSC-WG system under the worst-case scenario at SCR = 1. Therefore, a novel method is proposed in this work to stabilize the VSC-WG system under the same conditions and increase the damping of the system responses under lower levels of SCR. Fig. 5 shows a new feedforward compensation loop (in red) where a compensation signal u cp is added to the forward path of the PCC closed-loop control system with a negative sign. Based on this augmentation, the equation for the q-axis component of the current reference can be rewritten as where u cp (s) = K cp ω cp s + ω cp v oq (42) in which, K cp and ω cp are the dc gain and the cut-off frequency of the low-pass filter. In (42), v oq is used for the active compensation because; first, according to Table 1, v oq is the input of the PLL which corresponds to the instability of the dominant modes λ 3−4 , second, v oq is zero in the steady-state where the state vector X cp is given by where, x cp is the new state variable corresponding to the low-pass filter in (42); and the state matrix A cp is given in Appendix B.

B. STABILITY ASSESSMENT AND DESIGN
According to (42), there are two degrees of freedom to design the active compensator. Fig. 11 shows the eigenvalue spectrum of A cp under the nominal conditions when K cp increases at three different values of the cut-off frequency, ω cp = (15,20,25) rad/s. As shown, with the different values of ω cp , the dominant eigenvalues λ 3−4 migrate from the unstable to the stable region as K cp increases. Note that λ 3−4 move back toward the imaginary axis at higher values of K cp . Fig. 11 also shows that with a smaller value of ω cp , more improvement in the dynamic stability is obtained. As shown in Appendix A, the parameters of the active compensation are designed to provide the maximum enhancement in the stability of the VSC-WG system at SCR = 1. Fig. 12 shows the location of the dominant eigenvalues of A cp when P ac increases from 0.35 to 1 pu. As shown, λ 3−4 progress toward the imaginary axis while λ 1 does not show a visible change whereas λ 2 departs slightly away from the imaginary axis. Unlike the uncompensated system in Fig. 6, it is clear that the dominant eigenvalues are in the stable region for 0.84 < P ac <1 pu. The proposed active compensation loop successfully achieves the full integration of the VSC at SCR = 1. Fig. 12 also shows the progress of a pair of complex eigenvalues, denoted by λ cp1−2 , which corresponds to the active compensation state. As shown, by increasing P ac , VOLUME 8, 2020 λ cp1−2 depart slightly from the imaginary axis which does not compromise the system stability.

V. SIMULATION RESULTS
To validate the developed dynamic models, the small-signal analysis, and the effectiveness of the proposed compensation method, nonlinear time-domain simulations are conducted in MATLAB/Simulink for the system shown in Fig. 1 and the parameters given in Appendix A. The average model of the VSC is used for the purpose of dynamic simulation [4].

A. INFLUENCE OF THE AC VOLTAGE CONTROL
The dynamic response of the PCC voltage corresponding to the VSC-WG system is presented in this section. The small-signal model is based on the closed-loop system in Fig. 5 whereas T ac iv (s) is evaluated using (32) and (36) as given in Appendix C for the accurate and approximate small-signal models, respectively. Fig. 13 shows the step response of v od following a 1% step in v ref od at t = 0.5 s when P ac = 0.84 pu with and without the proposed active compensation. As shown in Fig. 13(a), where the PLL is slow with a bandwidth of 3.2 Hz, the approximate model is close to a first-order exponential signal whereas the accurate model shows a second-order underdamped behavior with a noticeable overshoot before reaching the steady state. Moreover, the response of the nonlinear large-signal model is shown which closely matches the response of the accurate small-signal model. Fig. 13(b) shows the dynamic responses of the models under the same scenario when a faster PLL with a bandwidth of 25 Hz is implemented. As shown, the response of the approximate model is the same as the case of the slow PLL since the effect of PLL is ignored. However, the responses of the accurate and the large-signal models show a poorly damped oscillatory behavior. Further, the responses of the accurate and large-signal models are closely matched which verifies the development of the small-signal model in (21)−(33). It is clear that the approximate model fails to reflect the entire dynamics of the system. On the other hand, the accurate model derived in this work closely follows the large-signal dynamics of the PCC voltage. This allows designing an optimized PCC controller for the VSC-WG systems according to the SISO model in Fig. 5. It is also worth noting that the slow PLL bandwidth of 3.2 Hz is implemented for the sake of evaluation only whereas a fast PLL is adopted in this work.
The capability of the accurate model in reflecting the PCC voltage dynamics is tested for the VSC-WG system with active compensation under the same scenario as the uncompensated model. Fig. 14 shows the response of the accurate small-signal model as compared to the response of the nonlinear large-signal model. As shown, both responses coincide closely. Moreover, the responses exhibit much less oscillatory behavior as compared to the response of the uncompensated model in Fig. 13 because the feedforward compensation is included in the control loop of the PCC voltage.

B. INFLUENCE OF THE ACTIVE POWER LEVEL
The performance of the VSC-WG system under different active power levels is investigated in Fig. 15. A small step change in the active power at t = 0.5 s under different levels of power is applied. As shown in Figs. 15(a)−(c), for P ac ≤ 0.6 pu, the responses are similar. However, as shown in Fig. 15(d), the uncompensated system is oscillatory as the active power increases. These oscillations are related to the relocation of λ 3−4 with the change in the power according to Fig. 6. The unstable oscillatory behavior of the uncompensated system is clear at P ac = 0.86 pu as shown in Fig. 15(e).

C. INFLUENCE OF THE GRID ANGLE VARIATION
In this part, another advantage of using the proposed active compensation method is demonstrated. The capability of the compensated VSC-WG system to preserve the stability following a sudden change in the phase angle of the grid voltage θ g is investigated. As an extremely challenging condition, Figs. 16(a)−(b) show the responses of P ac and v o following a step change of 70 • in θ g at P ac = 0.85 pu. Fig. 16(a) shows that the active power of the compensated system undergoes an overshoot and undershoot of around 0.15 pu, yet, the VSC controller manages to regulate the injected power at the initial value. Therefore, the stability of the system is preserved. As shown in Fig. 16(b), the VSC angle relative to the synchronous frame θ vsc -ω g t increases by 70 • while its value relative to the grid angle θ g (not shown here) is not changed. The same condition is applied to the uncompensated system. As shown in Figs. 16(a)−(b), the uncompensated system fails to follow the deviations in the voltage angle and therefore does not reach a stable operating point. Figs. 17(a)−(b) show the active power and angle responses to a 20 • increase in θ g between t = 1 s and t = 1.5 s at P ac = 1 pu. As shown, the compensated system stability is preserved under the nominal power condition.

D. INFLUENCE OF THE GRID IMPEDANCE VARIATION
Depending on the flow of power, especially in WGs where DGs are integrated, the grid impedance is not constant and might be subject to uncertainties [21], [39]. Online identification methods are suggested to find the real-time values of impedance for the stability assessment [40]. The stability  analysis that is conducted in Part IV-B considers the nominal power which corresponds to the worst-case scenario at SCR = 1, where the suggested active compensation in (41) guarantees the system stability. However, according to (1), the SCR level is a function of the VSC nominal dc power and the grid impedance. Therefore, in this part, the operation of the VSC-WG system is tested under the nominal power condition and a wide variation range in the grid impedance Z g .
Figs. 18(a)−(b) show the response of the VSC reactive power Q ac and the magnitude of the phase difference, i.e., |δ|, to the increase in the grid impedance (while the angle of Z g is fixed). Since the rate of the change in the grid impedance is not a priori knowledge, the simulation is repeated for two periods of 0.3 s and 1 s during which, the grid impedance is changed to assess the effect of the impedance variation on the VSC-WG performance with fast and slow rates, respectively. As shown, the system is initially in the steady-state stable condition at SCR = 3, i.e., the WG condition, where the grid impedance Z g is one-third of the nominal value given in Appendix A. Then, at t = 0.25 s, Z g increases linearly until it reaches the nominal value at SCR = 1, i.e., the VWG condition. In the meantime, according to Fig. 18(a), Q ac increases to partially compensate for the reactive power absorbed by the grid reactance. Since the injected active power is fixed at 1 pu, |δ| increases as the grid reactance increases according to Fig. 18(b). This agrees with the steady-state real power flow equation in inductive lines [37]. Fig. 18 also shows that there are overshoots and undershoots in the responses corresponding to the fast rate of changes in the grid impedance while VOLUME 8, 2020  they are considerably lessened in the responses of the slow rate of changes. However, the stable operation of the system is maintained during both impedance changes. Therefore, the VSC-WG system with the suggested active compensation method is immune to a wide range of changes in the grid impedance with slow and fast rates.

E. INTERACTIONS WITH VSC PRIMARY CONTROLLERS
In this part, the dynamic interactions of the proposed compensation method with the primary controllers of the VSC-WG system are investigated at P ac = 0.75 pu by comparing the compensated and uncompensated responses. Fig. 19(a) shows the frequency tracking responses of the PLL subsequent to a 1 Hz step change in the frequency of the grid. It is clear that the active compensation loop has an insignificant effect on the PLL bandwidth. Fig. 19(b) shows the responses of i fd following a 5% step in the active power at t = 0.5 s. The proposed active compensation method manages to significantly decrease the overshoots and suppress the oscillations before reaching the steady-state operating point.  Fig 19(c) shows the variations of the PCC voltage magnitude |v o | following a 5% step change in the voltage reference at t = 0.5 s. As shown, the proposed active compensation does not have any noticeable influence on the dynamics of the PCC voltage as compared to the uncompensated system. Generally, the design of the VSC controllers is not compromised by the proposed active compensation method.

VI. HIL EXPERIMENTAL VERIFICATION
The feasibility of the proposed compensation method is verified by an FPGA-based HIL platform, as shown in Fig. 20, where the VSC-WG model is emulated with the same specifications as in Appendix A. The circuit model of VSC-WG is developed in the single-FPGA NI-PXIe-7846R real-time simulator with 1 µs time step which is interfaced to the host computer by StarSim HIL software. Also, the control model is implemented in the double-FPGA NI-PXIe-7868R simulator which is interfaced to the host computer by StarSim RCP software. The connections between NI-PXIe chassis are realized through three I/O interface boxes.
A series of experiments is performed during which the VSC dc power P dc increases according to the profile given by P dc = [0.4, 0.6, 0.8, 0.9, 0.95, 1] pu at t = [0, 1, 2, 3, 4, 5] s, respectively. Fig. 21(a) shows the VSC responses v o , i o , and the dc-link voltage difference from the nominal value v dc . As shown, both v o and i o are well-damped and regulated under all conditions. Moreover, since v dc is regulated by the DVC, v dc is zero in the steady state as shown in the figure.
There are small overshoots in the waveform at the beginning of each step that are less than 0.15 pu at the start-up and less than 0.1 pu for the next steps. Fig. 21(b) shows a closer view of v o and i o in the steady state. It should be noted that v o has a total harmonic distortion of 5% which is in compliance with the IEEE standard 519 [38]. Fig. 22(a) shows the increases in the active power injected by the VSC P ac subjected to the steps in P dc . There are small overshoots during each step. This regime continues until P ac reaches the nominal value at t > 5 s. According to Fig. 22(b), the magnitude of the phase angle difference |δ| between the PCC and grid phase voltages increases after each step in P dc . Fig. 22(c) shows the variations of the proposed compensation signal u cp . As shown, the compensation signal is only activated during the transient conditions to mitigate the potential instabilities and has no impact at the steady-state conditions.

VII. CONCLUSION
In this work, the integration of VSCs into the VWG systems has been investigated, and the associated instabilities have been mitigated effectively under the worst-case scenario at SCR = 1. The proposed compensator injects a modified version of v oq into the q-axis reference of the CC. It is shown that the proposed method contributes successfully to the relocation of the unstable modes into more damped locations on the complex plane. In addition to the stabilization of the compensated system under the VWG conditions, the stability of the system under the grid angle deviations has been improved significantly with the proposed compensator. The effectiveness of the proposed compensator has been verified analytically using the small-signal analysis followed by large-signal simulations in MATLAB/SIMULINK and real-time HIL experiments. The proposed compensator has the following features; (1) it is simple and can be easily designed using the linear analysis tools; (2) it does not interact with the steady-state performance of the VSC; and (3) it has a minimal influence on the existing vector control structure and so it can be designed independently. Time-domain simulations and experiments of the VSC-WG system are carried out to verify; (1) the superiority of the accurate small-signal modeling derived in this work over the conventional approximate modeling in reflecting the PCC voltage dynamics; (2) the stability of the VSC-WG system with the proposed compensation method under VWG condition at SCR = 1 and its improved damping property at SCR > 1; and (3) the enhanced capability of the VSC-WG system to withstand sudden grid angle deviations and wide range of variations in the grid impedance.

APPENDIX A
Parameters of VSC-WG system are provided in Table 2.

APPENDIX B
The state matrices introduced in the main body of the paper are provided in detail. A up = A cp (i, j) for 1 ≤ i, j ≤ 13 and A cp is shown at the bottom of the next page. The corresponding parameters are: 1