Non-Isolated Fourth-Order Boost DC-DC Converter for Power Management in Low Voltage Low Power DC Grids: Design and Interaction Analysis

In this paper, a minimum-phase response fourth-order boost dc-dc converter (FBDC) exhibiting continuous input and output current is proposed. A voltage-mode controller is adopted to this converter to perform bus voltage regulation in a low voltage low power dc distribution system (LVPDS). FBDC supports additional load demand by interconnecting a second power source/battery. A systematic steady-state analysis for FBDC is established and the ripple content and other L-C design expressions are derived. The LVPDS is an integration of solar photovoltaic (PV) source using a conventional dc-dc boost converter (CBDC), and constant power load using a conventional dc-dc buck converter (CBuC). In this LVPDS, the FBDC primarily ensures dc bus voltage regulation, CBDC ensures the maximum power point tracking (MPPT) while CBuC regulates the load voltage. Various transfer function models, formulated through small-signal analysis, are used to address the controller design aspects and interconnected LVPDS stability issues. A generalized small-signal model of LVPDS is also developed to analyze the sub-system interactions arising during the coherent operation of BRC in this multi-converter system. The impact of connecting FBDC, as BRC, with other converters in the LVPDS is also analyzed. The laboratory prototype of a 48 V LVPDS is developed for experimental validation of bus voltage regulation and sub-system interactions. The theoretical and experimental results are found to be in close correlation with each other.


I. INTRODUCTION
Standalone single/multi-source low voltage low power dc distribution systems (LVPDS) involving small scale renewable energy generators (REGs) (such as solar photovoltaic (SPV), wind, fuel cell, and biomass, etc.), energy storage devices (batteries / ultra-capacitors) and loads have evolved as a viable solution not only to meet the power requirements of the secluded areas, still deprived of grid connectivity, but also of urban residential buildings to reduce their dependency on conventional energy sources [1]- [6]. LVPDS is formed by interconnecting several stages of dc-dc converters which process the power and carry out the power management task [3], [4]. The performance of LVPDS depends upon the performance of individual converters and hence selection of converter topologies, for various purposes, is very significant. For safe and reliable operation, standardization agencies have recommended 48 V and 24 V as safe operating voltages for residential consumers [5]. The generalized architecture of a multi-source LVPDS is shown in Fig. 1, wherein a source converter connects the SPV with the bus and also implements MPPT. The constant power loads are supplied via dc-dc buck converters while the energy storage device(s) are interfaced through bi-directional dc-dc converters [3], [4]. A second power source is interfaced, with the dc bus, using an additional dc-dc converter termed as 'bus regulating converter' (BRC). The role of BRC is to meet the additional load demand and also to regulate the bus voltage (v bus ) in the presence of fluctuations in the source and load. CBDC is widely used for this purpose but it exhibits (i) nonminimum phase (NMP) behavior due to the presence of right half plane (RHP) zero and (ii) discontinuous bus-side current (i bus ). The NMP behavior restricts the dynamic response of the converter by limiting its bandwidth to the frequency of RHP zero. Further, the existence of extra phase lag leads to control difficulties. Its effect is also observed in the start-up response and step change in duty ratio [7]. On the other hand, high current ripples result in more ac losses, thereby reduced efficiency, and induces harmonics and electromagnetic interference (EMI) [7]. The high peak-peak ripples have a larger impact when the working voltages are low. Therefore, the dcdc converters with enhanced performance are a viable option for interconnecting power sources within the LVPDS. The desired performance includes continuous input and output current exhibiting lower ripple content, low component count, high power density, faster dynamic response, etc.
Different dc-dc converters, exhibiting improved steady-state performance have been evolved by increasing the number of passive energy storage elements (ESE) and switching devices (SD) [6]- [24]. The performance and voltage gain of these converters depend upon the type of topology, the number of components, and their structural arrangement. Most of the boost topologies have continuous input current, due to the presence of an inductor at the input side, but the nature of load side current (whether continuous/discontinuous) depends on the placement of other circuit components in the converter [8], [9].
A tri-state boost converter having high voltage gain together with low source current ripple was proposed in [10] but its load current is discontinuous and it has six SDs. Boost converters proposed in [11]- [14] had two, four, five, and six switching devices, respectively. Converters having five and six ESEs were analyzed in [15]- [17]. A quasi Y-source dc-dc converter having high voltage gain together with continuous input current is proposed in [18] but its load side current is discontinuous. Although, the above-discussed higher-order dc-dc boost converters [6]- [18] have a high voltage gain either their input/output current or both input and output currents are discontinuous.
Higher-order dc-dc converters having high voltage gain together with continuous input and output (CICO) current have been reported in [8], [19]- [24]. A group of dc-dc converters exhibiting continuous currents was presented in [8] while a high-gain boost converter exhibiting continuous input and output current is reported in [19] but it has seven energy storage elements and five switching devices.
A KY-Boost converter exhibiting continuous input and output current was proposed in [20] but it has five energy storage elements and three switching devices. A high gain boost converter in [21] exhibits CICO currents but its seven ESEs and five SDs. High gain boost converters proposed in [22], [23] has three SDs and five ESEs.
It is inferred from the above discussion that although increasing the number of ESEs and SD improves the converter performance but it also increases the converter order thereby leading to control complexity. Thus, there is a need to evolve topologies exhibiting improved steady-state and dynamic performance aspects. Particularly, the boost topologies with a minimum-phase response which finds wide utility in the low power dc-distribution systems.
Referring to Fig. 1, when the FBDC is coherently operated with other source and load converters sub-system interactions take place which may have a deteriorating effect on the performance and stability of other converters. However, the severity of the performance deterioration depends upon the converter topology and its design. The instabilities imposed due to load and source converters on LVPDS were discussed in [25], [26], respectively. A systematic approach to design the load subsystem for stabilizing an unstable source converter was proposed in [27]. A local impedancebased stability criterion, depending upon the power imbalance conditions, was proposed in [28], [29] for a distributed system. The stability of the bi-directional dc-dc converter was analyzed using local impedance stability criterion in [30], [31].
However, the effect of interactions arising due to the interconnection of bus regulating converter on other coherently operating converters needs detailed investigations. Therefore, a generalized small-signal model of the LVPDS is developed and used for analyzing the effect of subsystem interactions arising due to the interfacing of FBDC, as BRC, with other dc-dc converters in the LVPDS.
The main contributions of this paper are summarized as follows: (i) a low component count FBDC converter exhibiting continuous source and load current is proposed and analyzed as BRC in a LVPDS, (ii) a generalized small-signal model of the LVPDS is developed and used for analyzing the effect of subsystem interactions arising due to the interfacing of FBDC with other dc-dc converters in the LVPDS, and (iii) an optimized power stage design methodology is followed for designing FBDC, with the aim, to obtain minimum phase behavior and minimize sub-system interactions.
The rest of the paper is organized as follows: Section-II presents a detailed analysis of the power stage of the twoswitch fourth-order boost converter. The controller design of FBDC is given in section-III. The architecture of low voltage low power dc distribution system (LVPDS) is discussed in section-IV. The derivation of the generalized smallsignal model, considering the source and bus regulating dc-dc converter, is given in section-V. Experimental results are discussed in section-VI while conclusions are given in section-VII.

II. FOURTH-ORDER DC-DC BOOST CONVERTER
The circuit diagram of the proposed fourth-order boost dcdc BRC is shown in Fig. 2. The salient features of this converter (FBDC) are: (a) exhibits minimum-phase behavior with reference to the control-to-output voltage transfer   Table-11.
To characterize the proposed converter performance aspects, the continuous-conduction mode (CCM) of operation is analyzed in the following paragraphs. The proposed converter exhibits two modes of operation in one switching cycle. Switch SW 1 modulates with active duty ratio 'D 1 ' (D 2 = 1−D 1 ) while the switch SW 2 operates complementary to it. The equivalent circuit of the converter during each mode is shown in Fig. 3(a)-(b), respectively. For uniformity in analysis, the direction of current in the inductors and capacitors marked for mode-I operation, in the equivalent circuit of Fig. 3(a), are retained for mode-II operation also. The key waveforms showing the nature of the steady-state currents and voltages in various converter components are given in Fig. 4 while the experimental results are given and discussed in section-VI. It is seen from Fig. 4 that both the inductors charges during Mode-I and discharges during Mode-II. On the other hand, the capacitor C 1 discharges during Mode-I and charges during Mode-II operation. The continuous nature of input current (I B ) and output current (I bus ) is also evident from Fig.4.

A. STEADY-STATE AND TIME-DOMAIN ANALYSIS
The voltage gain of FBDC is obtained by applying inductor volt-sec balance to inductors L 1 and L 2 , respectively. The corresponding equations are given by (1), where, T S is the switching time-period. The voltage gains of the converter, given by (2), is obtained by solving (1).
The generalized expressions for the steady-state quantities of ESE and peak-peak ripple in inductor currents and capacitor voltages, given by Table-1 are derived from the instantaneous voltage applied across the inductors and the current flowing through the capacitors, respectively, during different modes of operation. The expressions for the voltage and current stresses across the switches are derived and given in Table 2 for ready reference.

B. SMALL-SIGNAL MODELING
The small-signal models of FBDC are formulated by assuming the dc bus as a current sink. The state-space representation of the converters, exhibiting linear time-invariant response (LTI), during each mode is given by (3).    (4) and (5), are obtained as discussed in [15]. Here, the quantities with a 'hat' represent small-signal perturbations in the respective quantity. d represents perturbation in duty ratio D 1 . The key equations to derive these models are given by (A3) and (A4) in Appendix-A.

C. CONTROLLABILITY AND OBSERVABILITY OF FBDC
Controllability and observability are important aspects of the closed-loop operation of the dc-dc converters. A converter is controllable if and only if rank 'N' of controllability matrix 'C' is equal to the order of the converter TF. The controllability matrix 'C' for FBDC calculated using the procedure given in [32]- [33] is given by (A5). Here, it is observed that the rank of 'C' is 4 which indicates that FBDC is controllable.
A geometric hybrid approach [33], [34] is used to analyze the observability of FBDC. Here, the unobservable subspace, O m 1 of the system is obtained. The converter is completely observable if and only if, O m 1 = {0}, i.e. all elements of unobservable subspace are zero. The numerical values of unobservable subspaces for FBDC are given in (A6), in Appendix, where it is seen that all elements of O m 1 are zero. Therefore, the converter is completely observable.

D. POWER STAGE DESIGN AND ANALYSIS
The generalized expression of the control-to-bus voltage TF 'G vd (s) B−o ' of FBDC is given by (6) while the coefficients of its numerator and denominator are given in Table 3.
It is observed from (6) and its pole-zero plot, given in Fig. 5, that 'G vd (s) B−o ' has two pairs of complex conjugate poles P 1 and P 2 placed at frequencies f P1 and f P2 , respectively. It also has a pair of complex-conjugate zeros Z 1 , placed at f Z1 , which exists in RHP, and a real zero Z 2 which exists inside the left-hand side plane (LHP). A deeper analysis of the control-to-bus voltage transfer function reveals that the complex-conjugate zero is placed between the poles P 1 and P 2 which may lead to the formation of an up-down glitch in its frequency response (FR) as shown in Fig. 6. The shape of the up-down glitch (i.e. its peak and width) depends on the damping of poles and zeros and the difference between the frequencies at which the P 2 and Z 1 are placed [11]. This up-down glitch not only has a deteriorating effect on the dynamic response and stability of FBDC but also leads to  increased sub-system interactions when interconnected with other converters in LVPDS. The effect of interactions is more dominating in the frequency region where the up-down glitch is formed. Moreover, the presence of RHP zero restricts the control loop bandwidth thereby limiting its dynamic response. It is observed from Table 3 that the location of poles and zeros (magnitude and frequency), in the s-plane, depends upon the converter parameters, their parasitic resistances, and the operating point (i.e. duty ratio). Therefore, an appropriate selection of converter parameters may shift RHP zeros to LHP and also minimize the severity of up-down glitch. However, the manual selection of these parameters is very difficult due to the highly non-linear relation between the contradicting design requirements like placing zeros in LHP, minimizing up-down glitch, simultaneously meeting the steady-state requirements. Therefore, a Particle Swarm Optimization (PSO) based optimized power stage parameter selection procedure described in [11], [35] is followed, in this paper.
A multi-variable constrained optimization problem with the objective function given by (7) is formulated to minimize  the peak and width of up-down glitch subject to the following constraints: (i) peak-to-peak ripples in inductor currents and capacitor voltages are within specified limits, (ii) the poles of G vd (s) B−o are inside LHP, (iii) the zeros of G vd (s) B−o are inside LHP, and (iv) the damping of poles and zeros must be more than the threshold limits. Eq. (7) denotes the objective function of this optimization problem.
To minimize the above objective function, subject to the constraints, the following parameters are used in the PSO optimization process: (i) number of variables: 4, (ii) particle size: 20, and (iii) number of iterations: 35. The variations in the position of each particle in the parameter space with the number of iterations are shown in Fig. 7.
The values of the power stage design parameters obtained from the PSO design are given in Table 4 while the pole-zero plot for PSO design is shown in Fig. 5. The FR of G vd (s) B−o for PSO designed parameters is shown in Fig. 6 where it is seen that the up-down glitch is not formed in the characterizing transfer-functions. It is also observed from Fig. 5 and the phase plot of Fig. 6 that the optimal selection of converter parameters has led to the shift of complex-conjugate zero of G vd (s) B−o inside LHP which would have otherwise required an additional damping network or magnetic coupling.
The power stage of FBDC is also designed using conventional ripple-based design (RBD) for peak-to-peak ripple in inductor currents ( i L1 , i L2 ) < 20% and capacitor voltages ( v C1 , v C2 ) < 10%. The converter design parameters, obtained by substituting these requirements in the design equations of Table 2, are given in Table 4. The pole-zero map, for these parameters, is plotted in Fig. 5 wherein it is seen that the complex zero 'Z 1 ' is placed in RHP. The FR of G vd (s) B−o , for RBD parameters, is shown in Fig. 6, wherein the formation of a dominant up-down glitch is seen.

III. DIGITAL CONTROLLER DESIGN
The block diagram representing the dynamics of source current 'î B ' and dc bus voltage 'v bus ', in terms of small-signal TFs, derived in (4)-(5), is shown in Fig. 8. A single loop voltage-mode control scheme with controller transfer function C B is also shown in the figure. The closed-loop smallsignal TFs, obtained by using the block diagram reduction technique, are given by (8) Here, R(s) B is the open-loop gain of FBDC which defines its closed-loop stability.
In this section, the digital controller is designed to regulate the dc bus voltage (v bus ) using the digital redesign approach wherein the converter model in s-domain is first converted into z-domain and then the digital controller is directly designed using discretized models. To design the controller, the discretized small-signal control-to-bus voltage TF G vd (z) B−o is exported to the single input single output GUI environment of MATLAB. Here, the poles and zeros of the controllers are first placed to achieve absolute stability and then tuned to achieve relative stability as well [11]. The discretized control-to-bus voltage transfer functions, of FBDC, obtained by substituting the RBD and PSO design parameters from Table-4 are given in Table-5. The secondorder digital controllers, for RBD and PSO design parameters, along with the obtained relative stability margins are given in Table-6 and Table-7, respectively. Here, it is observed that higher bandwidth is achieved with PSO design (836 Hz as against 382 Hz with RBD) as the up-down glitch is eliminated in this case.

IV. ARCHITECTURE OF LOW VOLTAGE LOW POWER DC DISTRIBUTION SYSTEM (LVPDS)
A detailed scaled-down architecture of LVPDS with distributed control is shown in Fig. 9. The frequency-dependent impedances, admittances, and the notations of voltages and currents of all the converters along with their polarities VOLUME 8, 2020   are also marked. Subscript 'B' is used to indicate the TFs of BRC converter while suffix 'S' and 'L' are used to indicate the TFs of source and load converters in subsequent sections. Description of each converter is described below:

A. SOURCE CONVERTER
The SPV source is connected to the dc bus using the conventional dc-dc boost converter. The main role of the boost converter is to implement MPPT which is implemented using a two-stage controller. Here, Perturb-and-Observe MPPT algorithm is implemented which provides reference voltage (v S,ref ) for the control loop having a two-pole two-zero digital controller {C} S . {C} S regulates the output voltage of SPV at v MPP which is also the input voltage of source converter (v S ). Therefore, the closed-loop dynamics of its source voltage 'v S ' and bus-side current 'î bS ', given by (10), are significant for its interaction and stability analysis.
here, Z(s) s and Y(s) s are the input impedance and output admittance of the source converter, respectively.

B. BUS VOLTAGE REGULATING CONVERTER (BRC)
The FBDC, analyzed in the previous section, is proposed for voltage regulation of the dc bus. BRC connects a second source for supplying additional load demand. The power supplied by the source-2 varies depending upon the maximum power generated by the SPV, state-of-charge (SoC) of the battery, and the load demand. Bus voltage, v bus is regulated by the controller, {C} B of BRC.

C. LOAD CONVERTER
The load connected to the dc bus is a constant power load fed through a conventional buck converter. The main role of this converter is to regulate the load voltage (v 0L ). A simple voltage mode control is used wherein a two-pole two-zero digital controller {C} L regulates the load voltage. The smallsignal closed-loop model of the load side converter is given by (11).

D. PASSIVE DC LOADS
The passive dc loads are sometimes directly connected to the dc bus. The power drawn by such loads depends on the bus voltage, v bus . For analysis, all such loads are combined and represented by an equivalent load 'R' as shown in functional block diagram Fig. 9. The design parameters for the source and load side converter are given in Table 8. The second-order controllers used for regulating the output voltage of SPV and load voltage of the load side converter are given in Table 9.

V. FORMULATION OF GENERALIZED SMALL-SIGNAL MODEL FOR SUB-SYSTEM INTERACTION ANALYSIS
In this section, a generalized small-signal model of the LVPDS is developed and used for analyzing the effect of sub-system interactions arising due to the interconnection of BRC with other converters. Although, the model here is derived for LVPDS comprising of two sources and one load converter it can be scaled up for multiple interconnected converters. The small-signal model for LVPDS is formulated from the individual closed-loop small-signal models of the BRC, source converter, and load converter given by (8), (10), and (11), respectively. The generalized expression of the bus-side current of FBDC, obtained, from Fig. 9, is given by (12).
Substituting the expressions of 'î bS ' and 'î bL ', obtained from (10) and (11), respectively, gives (13) which represents the dynamics of 'î bus '. Eq. (13) is then substituted in (8) to obtain the expression for 'v bus ' in terms of input quantities (î bus ,v batt andv rbus ) and is given by (14) which in simplified form is given (15). 'v bus ', obtained in (15) is then substituted in (10) to obtain the expression forv S , given by (16), in terms of input quantities (î S andv batt ) and control quantities (v rS andv rbus ). Eq. (15) and (16) together form the small-signal model of LVPDS and is given by (17). (19) where, This model is derived, for the case, when the source converter is a current-fed converter and bus is regulated by BRC. Here, the quantities to be regulated are source voltagev S of source converter and bus voltagev bus .
The generalized expression of the minor loop gain (MLG), which defines the stability of the interconnected converters is obtained from the characteristic equation 'CE'. CE is given in (18) while the MLG is given by (19). Here, it is observed that the minor loop gains depend on the bus-side impedance/admittance of FBDC, source and load converter Z (s) B , Y (s) S, and Y (s) L , respectively.

A. INTERACTION ANALYSIS OF FBDC WITH OTHER CONVERTERS IN LVPDS
In this section, the sub-system interactions arising due to the interconnection of FBDC with the LVPDS are analyzed using the small-signal model developed in the previous section. The effect of these interactions on other converters operating in LVPDS is also analyzed. From the well-established impedance stability criterion [27], [28], the interactions are minimum and the stability is ensured when (20) is satisfied. (20) MLG and loop gains of the interconnected converters, required for interaction analysis, are obtained using (17)- (19) and plotted in Fig. 10. The FR of the closed-loop bus-side VOLUME 8, 2020 impedance Z (s) B−RBD and Z (s) B−PSO of FBDC, for RBD and PSO design, respectively are plotted in Fig. 10 (a). These impedances are superimposed with the equivalent bus-side impedance of the source and load converter Z(s) SL in the same figures. Here, it is observed that the FR Z (s) B−RBD intersect with that of Z (s) SL but the FR of Z (s) B−PSO does not intersect with it. This is because the loop gain bandwidth for RBD is 382 Hz which is less than f ZSL , the frequency of first resonance in Z(s) SL while the loop gain bandwidth for PSO design is 836 Hz which is greater than f ZSL . It is therefore inferred that the sub-system interactions take place when the converter is designed using RBD. This is due to the formation of a dominant up-down glitch. However, interactions are mitigated when designed using PSO. A similar inference is also obtained from the FR of MLG, plotted in Fig. 10 (a-ii), where it is observed that the MLG crosses the 0 dB line for RBD but it does not cross for PSO design. The FR of loop gain of source converter R(s) S , the interfaced loop gain of source converter for RBD, and PSO design R(s) LV S−RBD and R(s) LV S−PSO , respectively, are superimposed in Fig. 10 b (iii)-(iv), for RBD and PSO design, respectively. It is observed from Fig. 10 (b-iii) that the FR of R(s) LV S−RBD gets distorted in the frequency range where MLG RBD is greater than 0 dB leading to the formation of an up-down glitch in the magnitude plot. This up-down glitch may induce conditional instability in the source converter. However, it is observed that the FR of R(s) LV S−PSO is identical to R(s) S indicating that when FBDC is designed using PSO it does not alter the dynamic characteristics of the source converter.
To analyze the effect of sub-system interactions on load converter, the FR of loop gain of load converter R(s) L , the interfaced loop gain of load converter incase of RBD and PSO design R(s) LV L−RBD and R(s) LV L−PSO , respectively, are superimposed in Fig. 10 b (v)-(vi). It is observed from Fig. 10 (b-v) that the FR of R(s) LV L−RBD gets distorted in the frequency range where MLG RBD is greater than 0 dB. Not only an up-down glitch is formed in R(s) LV L−RBD but the converter behavior also changes from minimum phase to non-minimum phase, as can be seen from its phase plot in Fig. 10 (b-vi). This will not only deteriorate the dynamic performance of the LVPDS but may also destabilize it. However, the FR of R(s) LV L−PSO is identical to R(s) L which depicts that the interfacing of FBDC with PSO designed parameters do not affect the performance of the load converter.

VI. RESULTS AND DISCUSSIONS
The analytical concepts developed in the previous sections are experimentally verified on the laboratory prototype of the 48V LVPDS. The image of the experimental testbed is shown in Fig. 11. Here, a battery is interfaced via FBDC as a secondary source in an LVPDS to regulate the bus voltage. The zoomed image of a laboratory prototype FBDC, designed using converter parameters given in Table-3 is also shown. The digital control laws are implemented using the Texas Instruments' F28379-D controller. The TerraSAS ETS80 solar array emulator is used to emulate the characteristics of SPV. Initially, the steady-state and dynamic results of FBDC for standalone operation is presented thereafter results for its coherent operation with other converters interfaced in LVPDS, is presented.

A. FBDC AS STANDALONE CONVERTE
The experimentally measured steady-state waveforms of inductor currents (I L1 and I L2 ), input current (I B ), and output voltage of FBDC, (V C2 = V bus ), under nominal operating conditions, are shown in Fig. 12. Here, it is seen that the input current and the output (bus-side) current are continuous and have lower peak-to-peak ripples. The lower ripples reduce the ac losses, which increases the converter efficiency and life of the power source. The variation in the voltage gain of the converter against variation in the duty ratio is plotted in Fig. 13 (a). The variation in the voltage gain of FBDC  is almost identical to that of CBDC. The experimentally obtained plot of efficiency vs power is plotted and compared with CBDC in Fig. 13 (b) which shows that even though FBDC has four energy storage elements its efficiency is almost comparable with CBDC.
The dynamic response of the converter for step-change in the load current I bus from 1.5 A to 2.5 A, i.e. 66.67% change, is shown in Fig. 14. Here, it is observed that the second source supplies the additional current which increases from 3.1 A to 5.2 A. It is also seen that the bus voltage is regulated at 48 V. The experimental results to demonstrate that FBDC exhibits improved dynamic performance, for parameters designed using PSO, are given in Fig. 15. Here, the dynamic response of FBDC designed using RBD and PSO design is compared. For comparison purposes, the experimentally obtained data points, for both cases, are exported to Matlab for data handling. It can be seen in Fig. 15 (a) that although the bus voltage is regulated for both the design parameters, regulation time is quite less for PSO design as compared to RBD. Moreover, higher undershoot is observed for RBD design. This is because the loop gain bandwidth and phase margin for RBD design is less than that of PSO design. The dynamic response for the step decreases in bus current is shown in Fig. 15(b). Here, it is seen that although the converter, with RBD parameters, tries to regulate the bus voltage the response is not stable.    [21], CICO-2 [23], and CICO [24] are compared with the proposed converter. The dynamic response is plotted for step-change in load current I bus from 2 A to 3.2 A. Here, it is observed that the proposed converter exhibits a better response with minimum undershoot as compared to other converters.

B. FBDC FOR DC BUS VOLTAGE REGULATION IN LVPDS
As described in previous sections, FBDC regulates the bus voltage, the load side converter regulates the load voltage, and the source converter ensures MPPT.  Depending upon the local weather conditions when the solar PV power is less than the load power; the source converter and FBDC get connected in parallel to supply the load. The 180 Wp solar panel is connected to provide power to an active load rated at 24 V, 30 W and variable passive load that varies between 30 to 190 W. As the power supplied by SPV and loads are intermittent, the FBDC regulates the dc bus voltage simultaneously supplying additional load demand. The solar panel power generation data at different insolation levels are given in Table-   irradiance levels are shown in Fig. 17. The corresponding voltage, current, and power are also shown in the figures. In case, the battery is fully charged and the power generated by SPV and second power source is greater than the load demand then the source converter is controlled to operate at OFF MPPT point in-order to ensure power balance within the LVPDS. Figure 18 shows the performance of LVPDS, when FBDC designed using RBD is connected as BRC. As the impedance Z(s) B of the FBDC overlaps with the impedance Z(s) SL of source and load converter sub-system interactions take place and affect the performance of the other interconnected converters, as shown in Fig. 10. The sub-system interaction causes low-frequency but high magnitude oscillations in the  SPV voltage, bus voltage, and input current of FBDC. These as shown in regions (i) and (ii) of Fig. 18. It is therefore inferred that the formation of up-down glitch with RBD parameters results in sub-system interactions which deteriorates the performance of LVPDS.
The experimental results for the coherent operation of converters in LVPDS are shown in Fig. 19 to 21. While carrying out the experiments, FBDC with parameters designed using PSO is used. The experimental results for variation in solar irradiation (S) from S = 1000 W/m 2 to 800 W/m 2 are shown in Fig. 19 (a) where it is observed that even though the SPV power is reduced the power balance is maintained in the LVPDS. FBDC regulates the bus voltage while the load converter regulates the load voltage at 48 V and 24 V, respectively. In this case, a 190 W passive load is introduced for validating the operation of FBDC at higher irradiation levels. It is observed from Fig. 19 (b) that when the SPV generation is decreased from 180 W to 120 W, the input current drawn by FBDC is increased from 2.1 A to 4.5 A  to compensate for the decrease in power and to maintain the power balance in the LVPDS. The experimental results for the coherent operation of the converters during low irradiations are shown in Fig. 20.
A 40 W passive load is connected to the bus. Fig. 20 (a) shows the effect of gradual variation in solar irradiation from S = 600 W/m 2 to S = 200 W/m 2 . The source converter tracks the maximum power as it changes from P S = 76 W to P S = 30 W with SPV current (I S ) changed from 2.7 A to 1.1 A and SPV voltage regulated at V S = 28 V. The load converter regulates load voltage at V Load = 24 V and FBDC regulates the bus voltage at V bus = 48 V. Although, the slight steady-state error is observed in V bus but it is well within acceptable limits of low voltage dc grids.
The experimental results for change in irradiation from S = 400 W/m 2 to S = 200 W/m 2 are shown in Fig. 20(b). During a decrease in solar irradiance, it is observed that the BRC converter regulates the bus voltage and compensates for additional load demand by an increase in its input current from 0.5 A to 2 A. Meanwhile, the load voltage is regulated at 24 V with a constant load current. The experimental results for the increase in load current from 0.5 A to 1 A at constant solar power are shown in Fig. 21. It is observed here that the FBDC input current increases from 1.2 A to 1.8 A. Here, it is seen that the bus voltage and the load voltage are regulated to their respective reference values while the battery current increases to meet the increased load demand.

VII. CONCLUSION
In this paper, a low component count fourth-order boost converter, which exhibits continuous input and output current, was proposed for bus voltage regulation of LVPDS. The small-signal analysis of the converter revealed the formation of an up-down glitch in the converter models. The impact of glitch was minimized by optimal selection of the values of energy storage elements. Also, it was demonstrated that the optimal parameter selection shifted the RHP zero to LHP simultaneously mitigating the impact of up-down glitch in the converter models. This not only improved the dynamic performance and stability of the FBDC but also minimized the sub-system interactions within the LVPDS. A generalized small-signal model of LVPDS was derived and used to analyze the effect of sub-system interactions arising due to interconnection of FBDC with other coherently operating converters in the LVPDS. It was shown, through frequency response analysis, that RBD design parameters resulted in sub-system interactions which was reflected in the form of sustained oscillations in the experimentally obtained time-domain results for standalone and coherent operation. The power management feature of the LVPDS was demonstrated experimentally wherein it was shown that FBDC regulates the dc bus voltage simultaneously supplying the extra load demand when the SPV generation decreases. The analytical predictions were found to be in close agreement with the experimental results.
)U X ss and U are the steady-state values of state variables and input, respectively while R P = r L1 + r L2 + r C1 + r C2 .
The unobservable subspace of the system is defined as given by (16).