A Quasi-Multilevel Gate Driver for Fast Switching and Crosstalk Suppression of SiC Devices

The crosstalk phenomenon in a phase-leg configuration forbids the operation of SiC devices at high switching speed. A multilevel gate driver (MGD) is well-known for crosstalk mitigation, however, it requires two driver ICs and two voltage supplies to generate four different levels in the gate-source waveform. This paper presents a low-cost quasi-multilevel gate driver (QMGD) for crosstalk suppression which can be implemented on a single driver IC using only positive supply voltage. With a simple auxiliary circuit of the parallel-connected transistor, zener diode, and a capacitor, the proposed driver can generate multilevel output. The auxiliary transistor governs the charging and discharging of the capacitor, controlling voltage at the source terminal of SiC MOSFET and thus generating different voltage levels essential for crosstalk suppression. Performance of the proposed gate driver is validated through Spice based simulation as well as experimental tests conducted with Cree C2M0025120D. It is concluded that the proposed QMGD can replace a complicated MGD without any loss of performance.


I. INTRODUCTION
Wide bandgap devices have revolutionized the power electronics technology and gained rapid acceptance due to improved characteristics like fast-switching, high-voltage, high-temperature, and high-efficiency. However, these devices have relatively restricted gate voltage range, which introduces gate driver design challenges [1]. Particularly, due to low gate threshold voltage of SiC MOSFET, a phaseleg configuration encounters the crow-bar current which increases switching losses and thus degrades the converter efficiency. Therefore, to fully utilize SiC MOSFET to its potential, the spurious voltage spikes should be restricted.
Phase-leg configuration with low-side MOSFET S L and a high-side MOSFET S H is shown in Figure 1(a) with related list of symbols given in Table 1. The crosstalk occurs due to fast-rising or falling of drain-source voltage, which induces a current in the parasitic capacitance and introduces spurious spike in the gate-source voltage [2]. When v GSH climbs above V TH , it initiates the turn-on transient of S H and the steep slope of the drain-source voltage of S L induces a positive The associate editor coordinating the review of this manuscript and approving it for publication was Yuh-Shyan Hwang. spike in v GSL as illustrated in Figure 1(b). Spurious turn-on of S L occurs if the peak of the gate voltage spike is more than the threshold voltage, causing shoot-through and increasing switching losses. Figure 1(b) also shows a negative spike in v GSL which occurs during S H turn-off transient, when v GSH drops below the miller voltage. The negative voltage spike in v GSL can damage the oxide layer, leading to failure of the device. Therefore, it is equally important to protect a SiC MOSFET against the negative excursion of gate-source voltage. To justify the cost of SiC MOSFET by fully capitalizing its advantages, several techniques have been proposed [3], [4]. The conventional technique uses an external gate-source capacitance to suppress spurious spikes, however, it prolongs the rise time of the gate voltage and thus degrades the converter efficiency.
An MGD proposed in [5], has been proven to be the most suitable choice for driving a SiC MOSFET to ensure crosstalk suppression. Moreover, it accelerates the switching transition from blocking to conduction state by applying a maximum allowed gate-source voltage which reduces the switching losses. On the other hand, it relaxes the gate oxide stress by setting gate-source voltage to zero before the transition to the turn-on level. In [6], the authors proposed an active  MGD by connecting driver ICs in series. Similarly, a 3-level turn-off waveform is generated in [7] by driving the negative pole of one driver IC with the output of another. It means that a combination of driver ICs powered by two voltage supplies is required for the generation of multilevel output, raising cost, and layout design complexity. Other techniques listed in Table 2 are developed employing auxiliary circuits to generate multilevel gate-source voltage waveform.
This paper presents a low-cost four-level QMGD for SiC MOSFET by adding an active switch to the auxiliary circuit of [10] and the capacitor which acts as a local source is charged from driver output instead of driver supply, reducing driver losses. Applying maximum allowable drive voltage accelerates switching transition and clamping the gate voltage to zero reduces the risk of gate breakdown due to negative gate voltage spike. The proposed driver offers several advantages over reported work in literature. First, and the most important feature is its ability to generate a multilevel gate voltage using only a positive supply voltage. This feature eases the layout design of a power converter, leading to low parasitic inductances and reduction in electromagnetic interference (EMI). Second, the proposed circuit enables a four-level output using only one active switch which reduces complexity in implementation because the active switches also need gate signals for their driving to perform the desired operation.
The rest of the paper is organized as follows. Section II presents the operating principle of the QMGD. Also, mathematical relations are derived. The parameters design is given in Section III. Simulation and experimental results verify the performance of the proposed driver in section IV, followed by the conclusion in section V.

II. OPERATING PRINCIPLE OF QMGD
In order to overcome the aforementioned shortcomings, a simple gate driver for SiC MOSFET is proposed in Figure 2(a), with auxiliary circuit comprising a transistor M , a zener diode D Z , current limiting resistors R M and R C , and a capacitor C Z . Due to charging and discharging operation of C Z , the transition between gate voltage levels for a given switching state is smooth, therefore, the effect of parasitic inductance in the driver loop is minimized. Since the proposed QMGD enables four-level output using one additional active switch M driven by signal u M which is a delayed version of u DL , thus the auxiliary circuit doesn't add much complexity. In addition, the source terminal of M is connected to driver ground, which eases its driving as compared to the floating source case.
Since C Z is connected between the source terminal of SiC MOSFET and driver ground, levels in v GSL can be introduced by controlling the voltage v N . Due to parallel connection of C Z with active switch M and zener diode D Z , v N has steadystate values of V Z and α M V G . Thus, voltage v N raises when u DL = 1 and u M = 0 and saturates at V Z due to parallel connection with D Z . When u DL changes to 0, the driver circuit applies −V Z to the gate of SiC MOSFET, generating negative turn-off voltage. Therefore, the QMGD enables four-levels, that are α C V G , (V G − V Z ), −V Z , and 0 in the v GSL waveform as shown in Figure 2(b), where V G is the driver supply voltage and α C is the scaling factor determined by R M and R C . The switching signal u M is a time-shifted version of u DL having same time-period, therefore, perform the desired operation without any significant power losses.
The equations for v GSL and v N are derived by applying KVL to the equivalent circuits during each interval, which are essential to determine the optimized parameters of QMGD. The equivalent circuits for each interval are given in Figure 3. To ease the analysis, the conduction resistance of M and parasitic inductances of SiC MOSFET are neglected.
Turn-on transient of SiC MOSFET occurs in this interval. Since u DL = u M = 1, the driver supply voltage enforces a charging current i GS through C GS , which in addition to gate resistances R ON and R G(in) , also flows through R M . Applying KVL to the driver loop in the equivalent circuit, the dynamic equation is given in (1).
. Since, the time-constant of equivalent circuit depends on R M , it should be relatively smaller to ensure minimal effect on slope of v GS , meaning that α C should be close to 1. Also, the voltage v N increases to attain a steady-state value determined by By the end of interval I, i GS decays to 0 and v GS and v N achieve the steady-state values of α C V G and α M V G , respectively. Meaning that only current i RC = V G (1−α M )/R C flows in M , regulating v GS and v N . Since i RC contributes to power dissipation, optimal value of R C needs to be chosen.
At time t 2 , u DL is still high while u M toggles to the low logic level, turning-off M . C Z begin to charge by currents i GS and i RC , raising v N . This reduces v GS as indicated in equation (3), where R C C GS determine the transition time. To ensure that v GS attain next voltage level before the transition of u DL to 0 logic level, time-constant R C C GS D m T S , where D m is the minimum duty ratio of SiC MOSFET. Interval III ends when v N and v GS get to voltage level V Z and (V G − V Z ), respectively.
At time t 3 , C Z is pre-charged to voltage V Z . Due to parallel connection, zener current I Z flows in D Z , regulating v GS and v N at (V G − V Z ) and V Z , respectively. Therefore, i GS = 0 and Turn-off transient of SiC MOSFET occurs in this interval. The logic level of u DL toggles to 0, internally connecting the out of driver IC to the ground. Therefore, current i RC is 0 and C GS and C Z discharges in R OFF . Since, C Z acts as a local source to generate negative turn-off voltage, negligible change in v N should be ensured which requires C Z C GS . If we assume v N = V Z in interval V, transition time of v GS from (V G − V Z ) to −V Z is determined by R OFF as indicated by equation (4). v GS and v N saturates at −V Z and V Z , respectively, when i GS reduces to 0. The QMGD generates a negative turn-off voltage, that is −V Z without using an additional voltage supply. To eliminate switching crosstalk, the other SiC MOSFET in the phase-leg must be turned-on in The signal u M toggles to its high logic level at t 5 , turning-on auxiliary switch M and thus discharging C Z . Equation (5) indicates that v GS raises from −V Z to 0. Since the fast

III. SELECTION OF QMGD PARAMETERS
In this section, design rules for C Z , R C , and R M are presented. Auxiliary circuit waveforms in Figure 4 indicates four important constraints on QMGD parameters. First, the turnon voltage is v GS = α C V G , which is less than V G as the drop across resistor R M is α M V G . Second, during turn-off transient, C Z releases some of its energy, which can be reduced if C Z C GS . Third, the time required for charging of C Z to voltage V Z is determined by i RC , thereby R C cannot be selected freely to reduce the power losses, otherwise, the capacitor will charge to a level lower than V Z which can compromise crosstalk suppression. Fourth, V Z comes out to be the negative turn-off gate voltage, thus it is important to select diode with zener voltage less than the allowable negative voltage.
Resistor R M should be of smaller value in order to ensure fast turn-on, however, the C Z discharging current during interval V will be significantly high. Thus, the power ratings of resistor R M and transistor M are considered based on the operation in interval I and V. To find R M for a given value of t 1 , required for the transition of i GS from V G /R th to 0.1V G /R th , using (1) gives Design relation for C Z and R C can be derived in interval III, where v N raises due to charging of C Z . Since Solving (7) and simplifying for time-constant C Z R C gives required relation in (8) Effect of parameters C Z , R C , and R M on the response of QMGD can be observed from v GS verses v N phase plot in Figure 5(a) and corresponding time plot of v GSL in Figure 5(b).

IV. RESULTS AND DISCUSSION
The performance of the proposed QMGD is validated using Spice based simulation as well as with experimental setup. SiC MOSFET employed for the performance verification of driver is C2M0025120D from Cree. Considering the gatesource voltage limits (25 V/−10 V), a 25 V gate driver supply is used to generate drive waveform with levels +24.67 V, +19.57 V, −5.1 V and 0 V. A double pulse test (DPT) with parameters listed in Table 3 are used to evaluate the performance of gate driver. Parameters of the QMGD circuit, optimized using mathematical relations are given in Table 4.

1) SIMULATION RESULTS
The Spice model of SiC MOSFET provided by Cree Inc. is tailored to match the simulation response with that in the actual circuit. Parameters of the Spice model are listed  in Table 5, simulated with step size and dead-time of 1 ns and 600 ns, respectively. u M is delayed by 24 µs relative to u DL , meaning that v GSL stays at 24.67 V for nearly 4 µs as shown in the simulation result of Figure 6(a). It can be observed from  the simulation results that positive spurious spike is below the gate threshold voltage and thus doesn't cause crosstalk. Figure 6(b) shows that for higher values of R OFF it takes v GSL longer time to reach −V Z . Figure 6(c) and 6(d) show that higher values of R C result in lower charging current and longer falling time. Therefore, longer dead-time is required, which increases power losses as body diode of SiC MOSFET is not best in characteristics compared to Si counterpart.

2) EXPERIMENTAL RESULTS
To conduct the experimental tests, a DPT platform is constructed using Cree C2M0025120D SiC MOSFET. Prototype of the proposed gate driver is given in Figure 7. The QMGD is implemented using ADuM4135, which is an isolated gate driver IC having 4 A drive capability. For short circuit protection of power MOSFET, the driver IC embodies the desaturation detection circuit. Also, it features an Under Voltage Lock Out (UVLO) which protects the power circuit when the driver supply voltage drops below the specified threshold. The logic signals u DL and u M are generated from a digital signal processor. Two tests are conducted on the prototype: first, the effect of parameters C Z , R C , and R OFF on the waveform of v N and v GSL is captured and second, the waveforms of v N , v DSL , v GSL , and i L are recorded to verify the crosstalk suppression. Figure 8 shows the operation of proposed driver at noload comparing v N and v GSL for different circuit parameters. Waveforms for 50 nF, 100 nF and 200 nF values of C Z are compared in Figure 8(a) and two regions are highlighted where the effect is evident. First the v GSL transition time from 24.67 V to 19.57 V increases with C Z , minimum of 3 µs for 50 nF (shown in red) and 8.3 µs for 200 nF (shown in green). Second is the turn-off voltage which gets more negative with C Z , that are −3.3 V and −5.01 V for 50 nF and 200 nF case, respectively. Since R C sets the C Z charging current, its effect on the waveform is quite similar as shown in the comparison of Figure 8(b), for R C of 150 , 499 and 1 k . The zoomed view of Figure 8(b) is presented in Figure 8(c), which indicates that bigger R C cannot charge C Z to the voltage level V Z before turn-off transient. For R C = 1 k , v N has reduced to 2.5 V, which may not be enough to suppress crosstalk because the positive spike can violate the MOSFET threshold voltage. Another parameter that affects the operating waveforms is R OFF , which controls the turn-off transient as shown in Figure 8(d). The time required for v GSL transition from 19.57 V to 0 V is 65 ns and 113 ns for R OFF of 150 and 1 k , respectively. Please note that reducing R OFF suppresses the peak of positive gate voltage spike, accelerates the turnoff transient and lowers the switching losses.
The second set of results are given in Figure 9(a), measured at operating condition 400 V/20 A, with R OFF = 10 . The negative spike in v GSL during turn-off transient of the high-side SiC MOSFET is observed to be −8.1 V that is well above the allowable negative gate voltage (−10 V for C2M0025120D) as shown in Figure 9(b). Similarly, it is observed from turn-on transient of high-side device shown in Figure 9(c) that v GSL can go as high as 2.2 V which is less than the threshold voltage (2.6 V for C2M0025120D), suppressing crosstalk.

V. CONCLUSION
A QMGD has been proposed in this paper for crosstalk suppression. The simulation and experimental results using Cree C2M0025120D indicate that QMGD can successfully generate a multilevel gate-source waveform using only positive driver supply. Spurious turn-on of SiC MOSFET is avoided as the gate voltage spike is level shifted and is kept below 2.2 V at full load condition, that is lower than the threshold voltage of 2.6 V. Similarly, using zero-voltage clamping, SiC MOSFET is protected against the negative gate voltage spike, measured as −8 V at full load condition. Being a simple, low-cost and implementable with one driver IC, the QMGD is an excellent alternative to the conventional MGD. It is worth mentioning that the proposed QMGD is also applicable to GaN cascode transistors.
HAIDER ZAMAN received the B.Sc. and M.Sc. degree in electrical engineering from Abbottabad, Pakistan, in 2008 and 2013, respectively, and the Ph.D. degree from the School of Automation, Northwestern Polytechnical University, Xian, China. Since March 2019, he has been working as a Lecturer with the Electronics Engineering Department, UET Peshawar, also working with NPU as a Research Assistant. His current research interests include resonant converters, characterization of Silicon Carbide devices, gate driver design, and application wide bandgap devices in high-power density converters. He was awarded as outstanding graduate for his Ph.D. degree from Northwestern Polytechnical University.
PANPAN WU was born in Anhui, China, in 1995. He received the B.S. and M.S. degrees in Northwestern Polytechnical University, Xian, China, in 2010 and 2013, respectively, where he is currently pursuing the Ph.D. degree. His research interests include high-frequency planar magnetics design and integration, resonant converter design, analysis, and control. VOLUME 8, 2020 RONGYOU JIA received the B.S. degree in electrical engineering from Northwestern Polytechnical University, Xian, China, in 2019, where he is currently pursuing the master's degree in power electronics. His research interests include highfrequency power conversion and planar magnetics design.
XIN ZHAO (Member, IEEE) received the B.S. and M.S. degrees in power electronics and electrical drives from Northwestern Polytechnical University, Xian, China, in 2010 and 2013, respectively, and the Ph.D. degree in electrical engineering from Aalborg University, Aalborg, Denmark, in 2017. Since 2017, he has been with Northwestern Polytechnical University, as an Associate Professor. His research interests include power quality, distributed generation systems, power electronic converter design, analysis, and control.
XIAOHUA WU (Member, IEEE) received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from Northwestern Polytechnical University (NPU), Xian, China, in 1991, 1994, and 2004, respectively. In 1994, she joined NPU, where she is currently working as a Professor with the School of Automation. Her current research interests include modern control in power electronics, the modeling and simulation of power electronic devices, and the application of power electronics.