A New Configurable Topology for Multilevel Inverter With Reduced Switching Components

Multilevel inverters (MLI) are now becoming an important element for medium-voltage high-power applications. A low switch count MLIs are more popular due to their high efficiency, low cost, and easy control for the output having a higher number of levels. A new MLI topology for single-phase applications based on switched dc voltage source with reduced switch count is proposed in the paper. The presented topology is developed with the constraints of lesser blocking voltage of the switches with a higher number of levels at the output using a lower number of components. The proposed topology can also work in the symmetrical and asymmetrical configuration. Selective harmonic elimination (SHE) technique is applied to synthesize the staircase output voltages with eliminations of lower order harmonics by optimized computation of angles for switching operation. The comparative studies with the MLIs recommended in recent times show the importance of the proposed MLI structure in terms of reduced switch count and lower voltage stresses across switches in both asymmetrical and symmetrical configurations. The experimental results are presented to confirm the performance of the proposed topology.


I. INTRODUCTION
Multilevel inverters (MLIs) are the smart arrangements of dc voltage sources with or without using capacitors and power semiconductor devices to achieve high-quality output voltage. MLIs have been widely studied and are gaining importance in the medium and high voltage power applications. This is due to several important features of MLI such as good output voltage waveforms with a lesser amount of total harmonic distortion (THD), enhanced efficiency, reduced voltage stresses across power devices and better electromagnetic compatibility [1]- [5]. Cascaded H-Bridge (CHB), flying capacitor (FC) and neutral point clamped (NPC) are the three basic structures of MLIs. NPC and FC require a higher number of components and issues of capacitor voltage balancing as the number of levels increases. Therefore, many The associate editor coordinating the review of this manuscript and approving it for publication was Sanjeevikumar Padmanaban . researchers are focusing on the reduction of component count while maintaining a higher number of levels [4], [6].
The design of MLIs depends mainly on the number of voltage levels to be generated. The number of dc voltage sources/links in a topology determines the number of output levels. The magnitude of these dc voltage sources can be obtained in two configurations i.e. symmetrical and asymmetrical. In symmetrical configurations, all dc voltages have the same magnitude whereas, in the asymmetrical configurations, the magnitude of dc voltages is of different values. Therefore, a higher number of levels can be generated with the same number of dc voltage sources and power devices in an asymmetrical configuration compared to the symmetrical mode of operation [7], [8]. In recent years, topologies in both symmetrical and asymmetrical configurations have been reported in several papers. A new symmetrical cascaded MLI has been presented in [9]. It uses 10 switches for 7 levels and 16 switches for 13 levels. With more number of switches, the topology suffers from higher blocking voltages across the switches. A cascaded MLI using novel H-bridge has been reported in [10]. In the symmetrical configuration, topology uses lower count of power electronic devices for the same output levels as compared to NPC and CHB. Likewise, some other symmetrical topologies have been discussed in [11]- [15].
Asymmetrical topologies like E-type [16] and ST-type [17], each module uses four dc voltage sources for 13 and 17 output voltage levels, respectively. A cascade MLI has been conferred in [18] which can produce 25 levels by using 10 switches and 8 power diodes. In [16]- [18], the suggested topologies can be linked in cascade to realize an additional voltage level. Furthermore, 4×m number of dc voltage sources are required for m modules connected in cascade. Such selection of dc voltage sources limits the applications of MLIs. A modular MLI using H-bridge have been reported in [19], however, it produces less number of levels using higher input source count. Moreover, it requires higher voltage rating of switches used in H-bridge. Few structures based on H-bridge have been presented in [13], [20]- [24] for asymmetrical configurations. All of these topologies have high voltage stresses on switches which is equal to the sum of all dc voltage sources.
In this paper, a new multilevel inverter topology based on switched dc voltage sources is proposed. By adding a multiple number of switched dc voltage sources, the proposed topology can produce more levels at the output. This paper is organized as follows. Section II describes the basic unit of the proposed topology along with the generalized structure with the working principle in the symmetrical and asymmetrical mode of operation. The mathematical formulations for total standing voltage (TSV) in both configurations are also presented in this section. SHE-PWM technique is described in Section III. Sections IV deals with the comparative study with some recent and popular topologies in both configurations. Results and discussion are given in Section V. An application of the proposed topology for the utility grid has been explained in Section VI and the conclusion is drawn in Section VII.

II. PROPOSED MULTILEVEL INVERTER
In this section, the operating principle of the proposed multilevel inverter topology is discussed in detail. This section also describes the different modes of configuration together with the total standing voltage calculations.

A. PROPOSED TOPOLOGY
The basic unit for the suggested MLI is illustrated in Fig. 1. It contains four dc voltage sources, two bidirectional switches (S 1 , S 2 ) along with six unidirectional switches (S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 ). The bidirectional switch is made of two unidirectional switches configuration in common emitter connection, which needs only one gate driver circuit. The basic unit produces 9 levels in symmetrical configuration and 13 levels with asymmetrical configuration. For the safe operation of the proposed basic module, the pair of switches (S 1 , S 2 ),  (S 1 , S 3 ), (S 2 , S 4 ), (S 3 , S 4 ), (S 5 , S 6 ), and (S 8 , S 9 ) should be worked in complementary mode, to prevent short-circuiting of the dc input voltage sources. Table 1 shows the different switching combinations of the basic unit together with their respective voltages at the output.

B. GENERALIZED STRUCTURE OF THE PROPOSED BASIC UNIT
To attain more voltage levels at the output, the basic module/unit can be expanded by connecting multiple switched dc voltage sources. One switched dc voltage source consists of two unidirectional switches and one dc voltage source. The generalized structure of the proposed multilevel inverter is shown in Fig. 2. The switched dc voltage sources i.e. from V 4 to V m are used to generate a higher number of voltage levels with the addition and subtraction of different combinations of V 1 and V 2 . These voltage sources i.e. V 4 to V m are connected in such an arrangement that all these switched dc voltage sources can be linked in series with additive polarity. For this, the polarity of the switched dc voltage source is opposite to the previously connected one. Accordingly, the connections for different power semiconductor switches are changed. All the IGBTs are connected in a topology such that none of their anti-parallel diodes become forward biased, which can be the reason for the short-circuiting of the dc voltage sources.

C. MULTILEVEL INVERTER CONFIGURATIONS
Based on the appropriate magnitude selection of different dc voltage sources, the proposed topology can work in the VOLUME 8, 2020 asymmetrical and symmetrical configured sources. The number of dc voltage source decides the voltage levels for symmetrical configurations. The magnitude of different dc voltage sources used in an MLI is important to attain a higher voltage level at the output. Both configurations for the proposed structure of the MLI are discussed below.

1) SYMMETRICAL CONFIGURATION
In this mode of operation, the magnitude of all the dc voltage sources connected to the proposed inverter has a similar magnitude, i.e.
The equations for the proposed structure with (m + 1)dc input voltage sources are given as: where N sw , N driver , and N Levels are the number of power semiconductor switches, the required number of the driver circuit, and levels generated in the proposed MLI, respectively.

2) ASYMMETRICAL CONFIGURATION
In the asymmetrical mode of operation, by utilizing the same number switches increases the count of voltage levels at the output. The selection of magnitude of dc voltage sources in asymmetrical configurations determines the number of levels. The equation for the maximum number of levels in the asymmetrical case is given as, For the proposed basic unit, by selecting the magnitude of dc voltage sources as V 1 = 2V dc , and V 2 = V 3 = V dc , 13 levels at the output is achieved. The equations for N sw , and N driver remains the same as that of symmetrical configuration.

D. DETERMINATION OF TSV
Total standing voltage (TSV) is the term which is determined as the sum of the peak magnitude of the blocking voltages across all the switches with all voltage levels considered and is given as: where V S x is the maximum blocking voltage of the switch S x . TSV is one of the important factors that determine the cost of the inverter. In the proposed topology, the voltage stress across each complimentary switch is the same i.e., The maximum voltage stress across switch S 1 appears when switch S 4 is conducting. In this condition, voltage stress of is experienced by switch S 1 . Therefore, Similarly, The voltage stress across S 2m−1 and S 2m is fixed by the magnitude of V m . Hence, The voltage stress across S 2m+1 and S 2m is fixed by 2V 1 +V 2 and is not affected by other switched dc voltage sources connected to the topology. Therefore, Accordingly, from (6) to (12)

III. SHEPWM TECHNIQUE
THD is the main deciding factor for describing the quality of the output voltage which is given by, where  [27]. SHEPWM is used in this paper to achieve staircase output voltage as shown in Fig. 3. In SHEPWM, the lower order harmonics can be eliminated from the output voltage by selecting the optimized switching angles which are calculated at offline stage for each modulation index (MI) and saved in the form of lookup table in memory. In real-time, the calculated optimized switching angles based on the modulation index are recalled from memory to operate MLI. The output voltage can be expressed mathematically by using the Fourier series expansion and is given in (15), where n is the harmonic order, a o is the dc components of the output voltage and a n represent the even harmonic components and b n denotes the odd-numbered harmonics in the output voltage waveform. However, due to quarter-wave symmetry of the output voltage, dc component along with all even harmonics and sine terms of odd harmonics become zero.
For a staircase output voltage, b n can be expressed as, In this paper, the proposed single-phase topology is used to generate 9 and 13 levels at the output with symmetrical and asymmetrical configuration respectively. For 9 levels, the harmonic orders eliminated are the 3 rd , 5 th , and 7 th . The equations for different harmonic orders are given as, where V dc is the nominal dc voltage, V Desired is the required fundamental voltage and S is the number of DC sources or optimized switching angles. For 13 levels, the harmonic orders eliminated are the 3 rd , 5 th , 7 th , 9 th and 11 th . The equations for different harmonic orders are given as (20), shown at the bottom of the page. All the above equations (18) and (19) for 9 levels and equations (18) and (20) for 13 levels are solved with the condition of 0 < θ 1 < θ 2 . . . < θ s < π 2 using the PSO method as described in [28]. The feasible solutions that eliminate unwanted harmonics do not exist for the whole range of MI. Therefore, the primary objective of the SHEPWM method is to achieve the fundamental at the desired voltage with the additional benefit of removing the unwanted harmonics if realistic solutions exist. The fitness function given in (21) is used to find the optimized switching angles.
The order of specific harmonic is represented by h s e.g. h 2 = 3 and h 3 = 5, and V 1 is the fundamental voltage.
The control parameter values selected for the PSO algorithm is given in Table 2. Fig. 4 (a) gives the variation of angles with respect to the modulation index for 9 levels. Furthermore, Fig. 4 (b) displays the variation of 3 rd , 5 th , and 7 th harmonic components regarding the modulation index as a percentage of the fundamental component. For 13 levels inverter, 3 rd , 5 th , 7 th , 9 th and 11 th harmonics order are chosen to be eliminated from the output voltage. The solution of (20) gives the results for different angles. Variations for angle and harmonic order associated with a M a for 13 levels is demonstrated in Fig. 4 (c) and 4 (d), respectively. Table 3 gives the optimized switching angles for two different modulation indexes for 9 and 13 levels.

IV. COMPARATIVE STUDIES
The main intention of the proposed inverter is to generate more voltage levels by using a lower switch and source  count. To examine the performance of the proposed inverter in both configurations, a comparative investigation is carried out based on the number of switches, number of driver circuits required, TSV with respect to the voltage levels generated at the output, and dc voltage sources. Table 4 compares the proposed inverter with other structures of the MLI topologies in a symmetrical configuration.  Fig. 5 (a), the proposed inverter involves the least switch count along with [19]. Fig. 5 (b) gives the comparison of number of driver circuits used in a topology with respect to the number of levels. The switches used in NPC, CHB and FC are unidirectional. Therefore, the number of driver circuit required is equal to the switch count used. In some topologies, bidirectional switches are used. If bidirectional VOLUME 8, 2020 switches are connected as common emitter configured, only one driver circuit is required for two switches connected to work as a bidirectional switch. From Fig. 5 (b), the proposed inverter uses less number of driver circuit compare to other structures excluding [9]. Fig. 5 (c) shows the number of dc sources essential to produce N voltage levels. The proposed structure needs the same number of dc voltage sources as other structures except for FC. The TSV of different structures in contradiction of the voltage levels is presented in Fig. 5 (d). Also, the proposed topology has lower TSV than [9], [18] and [19]. Therefore, combining all these merits makes the proposed inverter suitable for low and medium voltage operations in a symmetrical configuration.

B. COMPARISON IN ASYMMETRICAL CONFIGURATION
A comparative study is carried out among the proposed topology and recently introduced asymmetrical MLI topologies in terms of the required dc voltage sources, driver circuit, number of switches, and TSV for N number of level generation. This comparison is presented in Table 5. Topologies [22] and [24] used for comparison are selected with an optimized design which generates the highest number of voltage levels using the least source and switch count. Fig. 6 (a) -(d) graphically compares the variation of the driver circuit, number of switches, TSV, and dc voltage sources, in terms of the resulting number of levels generated at the output. The proposed MLI involves less number of switches compared to other structures except [18]. Furthermore, based on Fig. 6 (c), the proposed topology requires less number of dc voltage sources compare to [13], [17] and [20]. Likewise, the proposed topologies give a lower amount of TSV compare to others except [24]. Furthermore, without any additional circuit, the negative voltage levels can be generated. So along with this ability, in addition to requiring a lower number of switches, dc voltage sources and TSV confirm that the proposed topologies can perform better than other existing topologies in the asymmetrical configuration.

V. RESULTS AND DISCUSSION
The operation of the proposed MLI structure is validated by various experimental results. The simulation work has been performed for both symmetrical and asymmetrical configurations. The experimental setup for the proposed topology is shown in Fig. 7. TOSHIBA IGBT GT50J325 switch is used in the laboratory prototype. The gate pulses for the power switching devices are generated using Vertix-5, XC5VLX50T controller, Field Programmable Gate Array (FPGA) with SHEPWM. To avoid the DC sources being from short circuit, a delay of 2µs has been introduced between complementary switches. The experimental results have been carried out for two modulation indexes using the angles given in Table 3 for both symmetrical and asymmetrical modes of operation.

A. SYMMETRICAL OPERATION
For the symmetrical configuration, the voltage magnitude of dc voltage sources is set to 30V. The peak output voltage is 120V for 9 levels at the output with four dc voltage sources. Fig. 8 (a) and 8 (b) show the waveforms of the output voltage at the modulation index 0.80 and 0.65 respectively. Their respective harmonic spectrums are shown in Fig. 8 (c) and (d). The eliminated harmonics for 9 levels have been selected as 3 rd , 5 th , and 7 th . These three harmonic orders are zero as shown by the harmonic spectrum in Fig. 8 (c) and (d).
With the symmetrical configuration, the proposed topology has been tested with different loading conditions. Fig. 9 (a) and (b) shows the waveforms of load voltage and current with resistive (R) and resistive-inductive (RL) loads respectively. A 150 resistor has been used as an R-load and for RL load, the load parameters are 150 and 120mH. Furthermore, the dynamic performance of the proposed topology has also been tested. Fig. 10 (a) depicts the output waveforms of voltage and current with a change of load from no-load condition to 150 and from 150 to 75 . A similar waveform with RL has been shown in Fig. 10 (b) where the load is changed from no load to (150 + 120mH) to (75 + 120mH). In addition, the change of load type has also been considered for evaluating the performance of the proposed topology in symmetrical configuration. Fig. 11 shows the waveforms with a change of load from 150 to (150 + 120mH).

B. ASYMMETRICAL OPERATION
Similarly for 13 levels, the magnitude of V 1 , V 2 and V 3 are selected as 60V, 30V, and 30V, respectively. Fig. 12 (a)-(d) demonstrates the experimentally obtained output voltage and their harmonic spectrum for the 13 levels output voltage at m a of 0.8 and 0.69 respectively. The optimized angles are used to synthesize the output voltage for 13 levels. The harmonic order 3 rd , 5 th , 7 th , 9 th , and 11 th are removed from VOLUME 8, 2020  the output voltage and is verified by the harmonic spectrums shown in Fig. 12 (b) and (d). Furthermore, the performance of the proposed structure is also examined for the dynamic change of resistive (no-load, R=150 , 75 ) and series-connected resistive-inductive load (no-load, 150 + L=120mH and 75 + L=120mH) have been demonstrated  in Fig. 13 (a) and (b) respectively. In addtion, the change of load type from 150 to (150 + L=120mH) has been demonstrated in Fig. 14 (a). The frequency of the output voltage has also been changed at the modulation index of 0.69 with a load parameter of (150 + L=120mH). The output frequency has been changed from 25Hz to 100Hz as illustrated in Fig. 14 (b). The harmonic spectrum for the output frequency of 25Hz and 100Hz is provided in Fig. 15 (a) and (b) respectively. From all these waveforms, it can be concluded that the performance of the proposed topology is satisfactory with different real-time operating conditions. VOLUME 8, 2020

VI. APPLICATION OF THE PROPOSED TOPOLOGY
The main contribution of the proposed topology is the reduction in the number of components which is essential for the grid-tied applications as shown in Fig. 16. Further, for the power quality improvement, the selective harmonic elimination pulse width modulation (SHEPWM) technique has been  used for the gate pulse generation as shown in Fig. 16. The accessible solar energy from solar PV panels is in the form of dc and a dc/dc converter is used to tracks its maximum power point (MPP). The output of the dc/dc converter forms the dclink for the inverter. Several combinations of solar panels with MPPT can be used for the isolated dc voltage sources of the proposed topology with different magnitude. These dc-links are used as an input for the multilevel inverter MLI. The output of the inverter is ac and is suitable to feed to the utility grid through an output filter. For the control of the power, the grid voltage and current (v g , i g ) is tracked and based on the available power, the modulation index (MI) is selected to control the output voltage of the inverter. The phase angle φ is used for the phase-locked loop (PLL) which is necessary to synchronize the inverter output voltage with the utility grid.

VII. CONCLUSION
A new MLI structure is suggested, which can work in both symmetrical and asymmetrical modes. The proposed structure comprises several features including lower switch count with lesser voltage stress across them. Moreover, the proposed topology uses a lower number of dc voltage sources for a certain voltage levels compared to other MLIs used for comparison. SHEPWM method is used to improve the output voltage by removing the lower order harmonics. Experimentation for both symmetrical and asymmetrical is carried for two different modulation indexes. For both modulation indexes, the selected harmonic orders are eliminated from the output voltage. Finally, the proposed topology is tested under different combinations of loads and gives satisfactory results. VOLUME 8, 2020 ATIF IQBAL (Senior Member, IEEE) received the B.Sc. and M.Sc. degrees in power system and drives (engineering) from Aligarh Muslim University (AMU), Aligarh, India, in 1991 and 1996, respectively, the Ph.D. degree from Liverpool John Moores University, Liverpool, U.K., in 2006, and the D.Sc. (Habilitation) degree in control, informatics and electrical engineering from the Gdansk University of Technology, Poland, in 2019. He has been employed as a Lecturer with the Department of Electrical Engineering, AMU, since 1991, where he has served as a Full Professor until August 2016. He is currently a Full Professor with the Department of Electrical Engineering, Qatar University, and a Former Full Professor of electrical engineering with AMU. He has published widely in international journals and conferences. His research findings related to power electronics, variable speed drives, and renewable energy sources. He has authored/coauthored more than 420 research articles and four books and several chapters in edited books. He has supervised several large Research and Development projects worth more than multimillion USD. He has supervised and co-supervised several Ph.D. students. His research interests include smart grid, complex energy transition, active distribution networks, electric vehicles drivetrain, sustainable development and energy security, distributed energy generation, and multiphase motor drive systems. He is also a Fellow of IET, U. SAAD MEKHILEF (Senior Member, IEEE) received the bachelor's degree in electrical engineering from the University of Setif, Setif, Algeria, in 1995, and the master's degree in engineering science and the Ph.D. degree in electrical engineering from the University of Malaya, Kuala Lumpur, Malaysia, in 1998 and 2003, respectively. He is currently a Professor and the Director of the Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, University of Malaya. He is also the Dean of the Faculty of Engineering, University of Malaya. He is also a Distinguished Adjunct Professor with the Faculty of Science, Engineering and Technology, School of Software and Electrical Engineering, Swinburne University of Technology, Melbourne, VIC, Australia. He has authored or coauthored more than 550 publications in international journals and conference proceedings. His current research interests include power converter topologies, control of power converters, renewable energy, and energy efficiency. He is also serving as an Editor for Renewable and Sustainable Energy Reviews; an Associate Editor for IEEE TRANSACTIONS ON VOLUME 8, 2020