Fast Bus Voltage Control of Single-Phase Grid-Connected Converter With Unified Harmonic Mitigation

This paper presents a comprehensive analysis of the harmonic sources of the single-phase grid-connected voltage source converter (VSC), which leads to an alternative approach for DC bus voltage control of the VSC under grid voltage distortion with a significant switching dead time. A selective current harmonic controller with the zero-reference structure plays a vital role in rejecting the harmonic components in the grid reference current created by the bus voltage control loop and the harmonic components in the grid voltage and in the VSC caused by the switching dead time. Therefore, the bus voltage control can adopt a conventional proportional-integral regulator tuned at a fast bandwidth. The proposed control scheme implemented in the multiple unbalanced synchronous reference frames was validated with a bidirectional 2-kVA VSC under grid voltage distortion and a significant dead time. Furthermore, the proposed control scheme exhibited the transient response and grid current quality superior to the conventional bus voltage control methods with a notch filter and a low-pass filter. The proposed control scheme has inherent frequency adaption.


I. INTRODUCTION
Single-phase voltage source converters (VSCs) are widely used for grid integration of renewable energy sources [1], [2], [3], [4], battery storage systems [5], railway traction systems [6], and on-board battery chargers of plug-in vehicles [7], [8].Fig. 1 depicts a typical application of the VSC, where the DC bus voltage v D (t) usually connects to a DC-DC converter or a 3-phase VSC.The control system of such VSCs generally comprises the cascade configuration with the outer DC bus voltage control loop and the inner grid current loop.The main control objectives are to have low bus voltage fluctuation and fast transient response under a sudden change in the bus power, and low grid current distortion.However, the distorted grid reference current i * g (t), the distorted voltage v pcc (t) at the point of common coupling (PCC), and the VSC The associate editor coordinating the review of this manuscript and approving it for publication was Qiang Li .terminal voltage v c (t) distorted by a dead-time voltage v DT (t), introduce harmonic components in the grid current i g (t).
The presence of the double-frequency ripple in the DC bus voltage control loop distorts the reference current for the grid current control loop.The distorted reference current is conventionally minimized by tuning the bus voltage at a bandwidth much lower than the double frequency, says 10 Hz [2].So, bulky aluminum electrolytic capacitors are used to limit large bus voltage transient fluctuation.In addition, active ripple cancellation circuits [9], [10] decoupled the pulsating power from the average power, which resulted in a lower bus capacitance and a higher loop bandwidth.However, these techniques require extra semiconductor switches, additional passive components, and additional control schemes.
The ripple voltage can be permitted to reduce the bus capacitance [11].Thus, increasing the bandwidth of the bus voltage control loop decreases the transient voltage fluctuation.Furthermore, distortion in the reference current is generally minimized by blocking the ripple voltage into the bus voltage control loop.The most common solution is a notch filter to block the double-frequency ripple [1], [12], [13], [14] [15].Alternative methods are adaptive bus voltage control [16], ripple voltage estimators [17], [18], nonlinear observers [19], and bus voltage sampling synchronized with the grid frequency [20].Thus, these approaches create a clean reference current with a fast DC bus voltage control.
The harmonic voltages also cause grid current distortion at the PCC and the VSC terminals due to a dead time T DT in each VSC leg [21], [22].Feedforward of the PCC voltage partly mitigates the grid current distortion [22].However, a DC offset in the voltage measurement induces an undesirable DC component injecting to the grid [23].The dead-time effect is highly nonlinear, depending on the VSC current direction.The dead-time voltage can be minimized by the compensated duty ratio calculated from an adaptive algorithm [24] or an immune algorithm [25].The PCC and dead-time harmonic voltages are the grid current control loop's disturbances, which can be mitigated by using a grid current controller with selective harmonic mitigation.Multi-frequency synchronous reference frame controllers [22], multi-frequency proportional-resonant controllers [22], [26], [27], and repetitive controllers (RC) were proven to be effective solutions [21].
To this end, the grid current problems due to the distorted reference current and the harmonic voltages have yet to be considered simultaneously.The bus voltage control schemes in [12], [13], [14], [16], [17], [18], [19], and [20] were carried out under a sinusoidal voltage with negligible dead time.Meanwhile, a sinusoidal reference was applied to the current control loop under the grid voltage harmonics [21], [22] and the dead-time voltage compensation schemes [21], [22], [24], [25], which do not guarantee a sinusoidal grid current with the bus voltage control loop.Therefore, we present a comprehensive analysis of the current harmonic sources of the single-phase grid-connected VSC, which results in an alternative approach to the VSC bus voltage control under a distorted PCC voltage and a  significant VSC dead time.This study adopts the unbalanced synchronous reference frame current controller [28] with the zero-reference configuration of selective harmonic compensators for simultaneous attenuation of the harmonic components in the reference current, PCC voltage, and VSC terminals due to the dead time.
With this current control structure, a conventional proportional-integral (PI) regulator can be applied for the bus voltage control.The proposed control structure allows the bandwidth of the DC bus voltage control loop to increase without sacrificing the grid current quality.The proposed control methodology was validated with a single-phase 2-kVA LCL-filtered VSC with a dual active bridge (DAB) DC-DC as the second stage converter, which was compared with the existing control methods under grid frequency variation, distorted grid voltage, and a significant dead time.

II. SYSTEM DESCRIPTION AND ANALYSIS OF HARMONIC SOURCES
A 2-kVA LCL-filtered grid-connected VSC shown in Fig. 2 with the parameters summarized in Table 1 is selected in this study.According to the grid current notation, the VSC is operated as the rectifier mode.The DC bus is connected to a DAB DC-DC converter as the second-stage converter for interfacing with a 400-V bidirectional DC source.This VOLUME 11, 2023 topology can be employed in bidirectional onboard electric vehicle chargers, and locomotive traction transformers.The bidirectional bus power is controlled by the phase shift modulation of the DAB DC-DC converter through the phase angle δ between the primary and secondary voltages of the medium frequency transformer.
A. GRID CURRENT DISTORTION DUE TO VOLTAGE HARMONICS Fig. 3 shows the VSC's grid current control block diagram in the stationary reference frame.The distorted PCC voltage v pcc (t) is considered in this study, which is written by where θ = ωt, V1 , and Vh are the voltage amplitudes, and ψ h is the phase angle of each harmonic component.The current controller G ci (s) can be a proportional-resonant (PR) regulator in the stationary reference framer or a PI regulator in the synchronous reference frame, which provides an infinite gain at the grid frequency ω for a zero steady-state error.The LCL filter governs the grid current i g (t) as follows.
Neglecting the switching frequency components, the VSC ideal output voltage v c1 (t) in ( 5) is controlled through the modulation signal m * (t) given by Equations ( 2)-( 6) illustrate that the grid current i g (t) is controlled through the modulation signal m * (t) with v pcc (t) and v DT (t) as the disturbances, which will introduce loworder harmonics into the grid current.The dead-time voltage v DT (t) in (5) can be approximated by where T SW is the switching period.This v DT (t) can be compensated in m * (t) using (7).However, for the LCL filter with the grid current feedback control used in this study, an additional current sensor is required for the dead time voltage compensation.A feedforward of v pcc (t) mitigates the grid current distortion to some extent [22].However, there can be a DC offset in the voltage measurement, inducing a DC component in the grid current [23].

B. GRID CURRENT DISTORTION DUE TO THE BUS VOLTAGE CONTROL
Fig. 4 depicts the simplified block diagram of the bus voltage control loop, where the grid current control loop is approximated as a unity gain.The bus voltage v D (t) passes through the bus voltage filter G fv (s) to compare with the reference bus voltage V * D for the bus voltage controller G cv (s) .The bus voltage filter can be a low-pass filter or a notch filter tuned at 2ω.A PI regulator is normally employed as the bus voltage controller.The bus voltage controller generates the reference current i * d representing the required active power drawn from/injected into the grid.The reference current i * q is used to set the reactive power.The reference currents i * d and i * q are multiplied by cos θ and sin θ templates obtained from a phase-locked loop (PLL), forming the reference signal i * g for the inner current control loop.
Let us consider that the grid current i g (t) initially consists of a DC component I g0 and the AC fundamental component AC i g1 (t) in this analysis.The grid current i g (t) is given as where Î1 and φ 1 are the amplitude and phase angle of i g1 (t).Asymmetry in semiconductor properties, gate driver delays, and an offset in the grid current measurement cause the DC component current I g0 [29].The grid current i g1 (t) can be decomposed into the active and reactive power-producing components i d (t) and i q (t), as given by With the fundamental component of the PCC voltage, the instantaneous grid power can be written as follows sin 2θ The instantaneous grid power consists of the average power P g1 and the oscillating power components pg1 (t) and p0 (t) due to the AC and DC components of the grid current.Neglecting losses in the LCL filter and VSC, the power balance at the DC bus can be written as where P D (t) is the bus output power feeding the DAB DC-DC converter.Assume v D (t) is tightly regulated around the reference value V * D [19].Therefore, the linearization of (11) yields The bus voltage v D (t) consists of the average value V D (t) and the ripple component ṽD (t) as given by Thus, substitution of ( 10) and ( 13) into ( 12) results in the average and oscillating components as follows.
Note that the dynamic of the average bus voltage ( 14) is accurate when the loop bandwidth is less than the oscillating frequency components.The oscillating powers pg1 (t) and p0 (t) lead to an approximation of the bus voltage ripple as The oscillating power component pg1 (t) causes the 2ω ripple component ṽD2ω (t), and the ω component ṽDω (t) is due to I g0 .These two ripple components pass through the bus voltage control loop.Then, the bus voltage controller G cv (s) creates the reference current i * d (t) as where the ripple components ĩ * dω (t) and ĩ * d2ω (t) in i * d (t) are the residues from the bus voltage regulator.The bus voltage control loop governs the amplitudes Îrp2 and Îrp1 , and phase angles ψ 2 and ψ 1 .The reference grid current is given by Substitution of ( 17) into ( 18) results in The desired components of i * g (t) are the first two terms in (19).The 2ω ripple component creates the 3rd harmonic and additional reactive power components, which are generally attenuated by a low-bandwidth bus voltage control loop [2] or by a notch filter.The DC component I g0 of the grid current causes the DC and 2nd harmonic components in i * g (t).This DC component I g0 can be minimized by carefully calibrating of the grid measurement.Suppression techniques with additional circuits provide an online adjustment of the DC component [29].

III. ANALYSIS OF HARMONIC MITIGATION TECHNIQUES A. HARMONIC REJECTION ANALYSIS OF THE GRID CURRENT CONTROL LOOP
where L 1 , L 2 , C f , and R f are the LCL filter parameters.The VSC's ideal voltage v c1 (t) is obtained from the pulse width modulation (PWM) with the modulation signal m * from the current controller output.The transfer function of the PWM process is modeled as  where T d = 2T s is the delay time caused by the sampling process and transport delay [30], with T s as the sampling period.The current controller G ci (s) can be a proportionalresonant (PR) regulator in the stationary reference framer or a proportional-integral (PI) regulator in the synchronous reference frame, where K p1 and K i1 are the controller gains.The closed-loop transfer function of the grid current control is given by The current controller G ci (s) in ( 23) has an infinite gain at the grid frequency ω, which forces |G cl (jω)| ≈ 1.Meanwhile, the controller's finite gain at the frequencies 2ω and 3ω still partly tracks the 2ω and 3ω components of i * g (t) in (19).The admittances Y DT (s) and Y pcc (s) represents the influence of the dead-time and PCC voltages on the grid current as follows .
(26) Equations ( 25) and (26) indicate that G ci (s) in ( 23) can reject only the fundamental components of v DT (t) and v pcc (t).A feedforward of the PCC voltage optionally improves the dynamic performance and mitigation of the PCC voltage harmonics [22], as given by

B. UNIFIED HARMONIC MITIGATION STRUCTURE
Mitigation of the voltage harmonics typically adopts a plugged-in harmonic compensator (HC) G cih (s), of which transfer function in the stationary reference frame is given by where K ih is the controller gain at the harmonic order h.This HC G cih (s) can be realized from PI controllers in the multiplesynchronous reference frame, proportional-multi-resonant (PMR) regulators, and repetitive controllers, which exhibit sufficient large gains at the selected frequencies.Fig. 6 shows the typical parallel HC structure of the grid current control with a harmonic controller in the stationary reference frame.The outputs m * 1 and m * h of the fundamental and harmonic controllers form the modulation signal m * .Equations ( 29)- (31) in Table 2 summarize the harmonic responses of this parallel structure.Equation 29indicates that this structure tracks the harmonic components of the reference current i * g (t) at the selected frequencies thanks to the HC's large gains.The large gains of HC attenuate the harmonic components of the PCC and dead-time voltages, as indicated in (30) and (31) [22].Fig. 7(a) depicts an alternative grid current control structure.This control structure is equivalent to Fig. 7(b), where the reference signal for the selective harmonic controller is zero.The transfer functions of this zero-reference HC structure are summarized in ( 32)- (34)   have identical rejection characteristics of the dead-time and PCC voltages, as indicated in ( 30) and (33), and ( 31) and (34).According to (32), the zero-reference HC scheme can increase the bandwidth of the conventional bus voltage control to improve the dynamic response and reduce the bus capacitance without restriction in grid current distortion.On the other hand, the existing bus voltage control schemes only focused on creating a clean reference for the grid current control loop.

IV. PROPOSED VSC CONTROL SCHEME A. UNBALANCED SYNCHRONOUS REFERENCE FRAME CONTROL
The unbalanced synchronous reference frame control [28] is chosen for the fundamental and harmonic component current control.Fig. 8 depicts the stationary frame representation of the transfer function H DC (s) implemented on the synchronous reference frame at hωt [31].The error signals in the stationary reference frame e α (t) and e β (t) derive from where For the single-phase application, the α-component output y α (t) is only considered.According to [31], the α-component output y α (s) is derived from the convolution and modulation properties of the Laplace transformation, which yields  Thus, substituting H DC (s) = K ih /s and e β (t) = 0 into (37), the equivalent transfer function in the stationary reference frame H AC (s) becomes This so-called unbalanced synchronous reference frame control is equivalent to the resonant controller [28].There are different control structures to make the error in the β− axis zero e β (t) = 0 with identical performance.Fig. 9 depicts the unified structure of the unbalanced synchronous reference control.The arbitrary signal x * β (t) is used for the Park transformations on the reference and feedback sides, which causes e β (t) = 0. Fig. 10 portrays an implementation structure of the unbalanced synchronous reference frame control with the reference signals in the dq− axes, where the reference signal in the β− axis x βref (t) is used as the orthogonal signal for the axis transformation of the feedback signal x α (t).The signal x d (t) and x q (t) in Fig. 10 are identical to those of the conventional synchronous reference frame control in the steady state [28].Meanwhile, Fig. 11 shows another implementation configuration of the unbalanced synchronous reference frame control with x αref (t) as the reference signal, where e β (t) = 0.This structure is suitable for an AC reference signal such as  HCs.It has been proven that the error signals e d (t) and e q (t) in Fig. 9 are identical to those in Fig. 10 and Fig. 11, which yields a similar performance [28].

B. PROPOSED BUS VOLTAGE CONTROL SCHEME
The existing bus voltage control methodologies of the singlephase VSC try to create a clean reference for the grid current control loop [12], [13], [15], [18], [20], [32].This study proposes an alternative approach using a conventional bus voltage control system tuned at a fast bandwidth.However, this makes the grid reference current i * g (t) distorted.So instead, we employ the current control with zero-reference HC scheme in Fig. 7(a) as the main mechanism for simultaneous attenuation of the harmonic components in the grid reference current i * g (t), PCC voltage v pcc (t), and VSC's deadtime voltage v DT (t).
Fig. 12 shows the proposed bus voltage control scheme of the VSC.The bus voltage control loop applies a conventional PI regulator.The bus voltage passes through the low-pass filter G fv (s) given by Note that G fv (s) is used for loop shaping, not for attenuating the ripple component, which is explained in the controller design.The fundamental current control system G ci (s) adopts the unbalanced synchronous reference frame with the reference current in the β-axis i * β (t) as the orthogonal signal for the Park transformation, which is simplified from Fig. 10.This configuration results in the virtual β-axis current error signal e iβ (t) = 0.According to (37), the equivalent transfer function of the fundamental current control loop in the stationary reference frame is identical to (23).Moreover, this unbalanced synchronous reference frame control configuration has intrinsic frequency adaptation and power extraction capabilities.
The harmonic current controller G cih (s) is plugged into the fundamental current control G ci (s).This current control structure is equivalent to Fig. 7(a).Fig. 13 illustrates the implementation of G cih (s), where each harmonic component is simplified from the unbalanced synchronous reference frame control in Fig. 11.The transfer function of each harmonic order is equivalent to (28).Therefore, the proposed fundamental and harmonic current controllers in Fig. 12 are equivalent to the stationary reference frame current control system in Fig. 7(a).Note that this configuration of G cih (s) also exhibits inherent frequency adaptability.The  harmonic controllers, orders 3 rd , 5 th , 7 th , 9 th , 11 th , and 13 th were adopted.The second-order harmonic controller was also added to suppress the 2ω component of i * g (t) caused by the DC component of the grid current as demonstrated in (19).Furthermore, multiple-resonant regulators with frequency adaptation can be employed as the harmonic controller to reduce the computational effort [22].The inverse Park transformation PLL is used in this study [33].
The proposed control scheme is compared with the conventional control scheme as shown in Fig. 14 and the notch filter-based control as shown in Fig. 15, where only the fundamental component controller is adopted for the grid current control.Meanwhile, for the notch filter-based control scheme, the low-pass filter is replaced by the notch filter G NF (s) given by where ω d is the damping frequency.This notch filter blocks the 2ω component of the bus voltage.

V. CONTROLLER DESIGN AND HARMONIC REJECTION ANALYSIS A. GRID CURRENT CONTROLLER DESIGN
The LCL filter with the parameters listed in Table 1 has a resonant frequency f r of 5.03 kHz, and the control system operates  at the sampling frequency of f s = 20 kHz.This resonant frequency f r satisfies the stability criterion of f s /6 < f r < f s /2 for the grid current feedback [34].First, the fundamental component current controller is designed in the stationary reference frame.The loop bandwidth must be chosen to be lower than f r .The LCL filter can be simplified at such a frequency range as an L filter with [35].The stationary reference frame equivalence of the open-loop grid current control system is given by The maximum cross-over frequency ω ci,max is obtained from [30] where φ mi is the chosen phase margin.This ω ci,max leads to K p1 approximated as The value of K i1 is then determined from at which tan −1 ω ci,max K p1 /K i1 = 85 • .A conservative phase margin of φ mi = 60 • was selected.With the parameters in Table 1 and T d = 2T s , K p1 and K i1 were calculated from ( 43) and ( 44) with ω ci,max = 2, 222π rad/s.The integral gains K ih of the harmonic controller should be selected lower or equal to (44) to create the corresponding negligible magnitude contributions at the cross-over frequency [27].Thus, the integral gains were set as follows With this set of harmonic gains, the phase margin reduces to φ mi = 43 • at the chosen cross-over frequency ω ci , still large enough to guarantee stability, as shown in Fig. 16.The open-loop gains at the selected frequencies are lower than -100 dB, which attenuates the current error signal at such frequencies.Although the harmonic controller decreases the first harmonic gain, it is still large enough to track the fundamental component current with a zero steady-state error.
The open-loop system has multiple gain cross-over frequencies with the harmonic controller at the selected frequencies.However, the system stability is measured at the highest gain cross-over frequency [36].Moreover, the two gain cross-over frequencies around the resonant frequency of the LCL filter with the phase margins φ m1 = 43 • and φ m2 = 189 • shown in Fig. 16 guarantee the stability criteria for the grid current feedback.

B. BUS VOLTAGE CONTROLLER DESIGN
Fig. 17 depicts the block diagram of the bus voltage control, simplified from Fig. 4. The grid current control loop is approximated as a unity gain, and the grid oscillating powers pg1 (t) and p0 (t) are considered the disturbances.The extended symmetrical optimum method [37] is adopted, which is proven to have a better transient response and lower grid current distortion [38] than the method in [2].With this tuning method, the phase angle of the forward path reaches  the maximum at the cross-over frequency ω cv .The phase margin φ mv is chosen from a constant β as The recommended values of β are from 4 to 16, which relates to φ mv of 36 • to 60 • .The PI controller parameters K pv and K iv and the low-pass filter time constant T f are codesigned from the desired bandwidth ω nv as follows The parameters obtained from (47) yield the closed-loop transfer function given by The bus voltage control loop was designed at ω cv = 50π rad/s and β = 5.83 with φ mv = 45 • .This study compares the proposed control method with the conventional bus voltage control in Fig. 14 with ω cv = 20π rad/s and ω cv = 50π rad/s.The notch filter in Fig. 15 is simplified as the lowpass filter with T f = ω d /(2ω 2 ) so that so that the above design method of the bus voltage control can be adopted.The notch filter G NF (s) tuned at 2ω with ω d = 140π rad/s has a frequency response below 2ω close to a low-pass filter for ω cv = 50π rad/s.Thus, K pv and K iv for the notch filterbased control can be adopted from the conventional control with ω cv = 50π rad/s.

C. HARMONIC REJECTION ANALYSIS
Fig. 18 shows the closed-loop frequency response of the grid current control with the reference current plotted from (32).The closed-loop grid current system exhibits a unity gain with a zero-phase angle at the grid frequency, which provides a zero steady-state error.Meanwhile, the harmonic controller rejects the reference current at the selected frequencies.Fig. 19 illustrates the frequency responses of the admittances Y DT (jω) in (33) and Y pcc (jω) in (34).The proposed grid current control scheme with the harmonic controller G cih (s) rejects the disturbances from the dead-time voltage v DT and grid voltage v pcc at the fundamental and selected harmonic frequencies.On the other hand, the harmonic components of  the grid voltage are even amplified if the fundamental current controller is only adopted.

VI. SIMULATION
A switched-circuit model of the VSC was developed in MATLAB/Simulink.Voltage harmonic orders 3 rd of 5%, order 5 th of 2%, and orders 7 th , 9 th , 11 th 13 th of 1% to the fundamental component of the PCC voltage were added.The added harmonics resulted in a total harmonic distortion (THD) of 5.74%.The dead-time voltage v DT (t) determined from (7) with T DT = 4µs was added to the VSC terminal voltage v c (t).The bus voltage control loop was tuned at a bandwidth of 50π rad/s with a PLL bandwidth of 20π rad/s.The VSC was simulated to operate in mode with the nominal bus power of P D = 2 kW and i * q = 0 for a unity power factor.
Fig. 20 compares the steady state performance of the conventional control and the proposed control schemes under the sinusoidal PCC voltage in Fig. 20(a), the sinusoidal PCC voltage and the dead-time voltage in Fig. 20(b), the distorted PCC voltage in Fig. 20(c), and the distorted PCC and dead-time voltages in Fig. 20(d).The conventional control scheme's grid current i g (t) under the sinusoidal PCC alone still distorts.Meanwhile, the proposed control method with HC rejects the harmonic contents in the reference current i * g (t), as shown in Fig. 20(a).As a result, the disported PCC and dead-time voltages heavily affect the grid current waveform with the conventional control scheme, as depicted in Fig. 20(b) to Fig. 20(d).On the other hand, the proposed control method with HC forces the grid current to be near sinusoidal with the simultaneous presence of the dead-time voltage and PCC harmonic voltage v h (t).microcontroller's PWM outputs.A Chroma 61860 60-kVA grid simulator emulated the PCC voltage.The DC output voltage V B for the DAB DC-DC converter was set at a constant voltage of 400 V using a Chroma 17020 bidirectional DC source.The output power was controlled in the range of ±2 kW through the angle δ * of the single phase-shift modulation implemented on the same microcontroller.The q-axis reference current was set at i * q = 0 for a unity power factor.

B. EXPERIMENTAL RESULTS
Fig. 23 shows the transient response of the v D (t) and i g (t) under the distorted PCC voltage and T DT =1 µs when the output power changes from 2 kW to zero.The reference current i * d (t) in the discrete-time control system was sent to an embedded 12-bit digital to analog converter of the microcontroller with appropriate scaling.The proposed bus voltage control system compares the conventional control schemes tuned at ω cv = 20π rad/s and ω cv = 50π rad/s and the notch filter-based control system tuned at ω cv = 50π rad/s.The proposed control, 50π-rad/s conventional and notch filter-based control schemes, have voltage fluctuations of approximately 50 V and recover to the 400-V reference within two cycles.The experimental transient response agrees with the simulation result in Fig. 21.However, the 20π-rad/s conventional control gives rise to v D (t) to 540 V.It takes ten cycles to go back to the 400-V reference, which temporarily forces the grid current control into the unstable range.Thus, the bus capacitance C D should be increased for this 20π-rad/s conventional control scheme.
Fig. 24 compares the steady-state waveforms of v pcc (t), v D (t), i g (t) and i * d (t) of different control schemes when the VSC operates in the rectifier mode with the output power of 2 kW under the sinusoidal PCC voltage and T DT =1 µs.Although the reference current i * d (t) of the proposed control system contains ripple components, the grid current waveform is still near sinusoidal.Meanwhile, i g (t) under the 50π-rad/s conventional control scheme under the sinusoidal voltage is slightly distorted due to the ripple component of i * d (t).The 20π-rad/s conventional and notch filter-based control systems under the sinusoidal voltage create the clean reference current i * d (t), which also results in near sinusoidal grid currents.caused by the DC component of i g (t).Therefore, the 2 nd harmonic component of the grid current is noticeable for the 50π-rad/s conventional and notch filter-based control systems compared with the 20π-rad/s conventional system.Meanwhile, the harmonic controller G cih (s) of the proposed control scheme successfully damps the 2 nd harmonic current.
For the distorted PCC voltage and the sizeable dead time T DT =4 µs in Fig. 26, grid current distortion can be observed with the conventional and notch filter-based control schemes.The dead time mainly distorts i g (t) during the zero crossings [21].The distortion due to the PCC voltage harmonics can be observed during the peaks of the current waveform.The harmonic controller G cih (s) of the proposed control scheme mitigates the harmonic disturbances due to the deadtime effect and PCC voltage.The grid current harmonics with the proposed control system under the distorted PCC voltage in Fig. 27   proposed harmonic mitigation structure.Meanwhile, the distorted PCC voltage adversely affects the grid current waveforms under the conventional and notch filter-based control schemes.
Fig. 28 compares the THD i values under the sinusoidal and distorted PCC voltages and the dead times of T DT =1 µs and T DT = 4 µs with the output power of ±2 kW.The proposed bus control system exhibits the lowest THD i values.The difference is highly noticeable with PCC voltage harmonics and a significant dead time.Fig. 29 compares the current distortion under the sinusoidal voltage and T DT =1 µs with the output power of 2 kW with the allowable frequency between 47-52 Hz for Thailand's grid.The proposed control system has inherent frequency adaptation.The detuned notch frequency causes THD i to vary with the grid frequency.The conventional control scheme with a bandwidth of 20π rad/s, far below 2ω, virtually has no impact on the grid frequency variation compared with the 50π-rad/s bandwidth.
Table 3 compares the performance of the proposed bus voltage control scheme with the existing VSC control methods.The power extraction in the table refers to the decomposition capability of the grid current.It indicates that the proposed methodology covers all the performance criteria, which has advantages over the existing methods.

VIII. CONCLUSION
Grid current control with selective harmonic mitigation is proposed for bus voltage control of the single-phase grid-connected VSC.Zero-reference current configuration of the harmonic controller rejects harmonic components in the grid reference current, VSC dead-time harmonics, and PCC voltage harmonics.Thus, a conventional bus voltage control with the proposed selective harmonic mitigation structure tuned at a fast bandwidth minimizes the bus capacitance without sacrificing the grid current quality.The proposed control scheme implemented in the unbalanced synchronous reference frame has superiority over the low-bandwidth conventional and notch filter-based control schemes as follows 1) Simultaneous rejection of harmonic components in the reference current, dead-time voltage, and grid voltage at the selected frequencies.2) Second harmonic mitigation due to a DC component in the grid current.3) Inherent frequency adaptation through the axis transformation.

FIGURE 1 .
FIGURE 1. Single-phase LCL-filtered VSC and DAB DC-DC converter under this study.

FIGURE 2 .
FIGURE 2. Single-phase LCL-filtered VSC and DAB DC-DC converter under this study.

FIGURE 3 .
FIGURE 3. Single-phase LCL-filtered VSC and DAB DC-DC converter under this study.

FIGURE 4 .
FIGURE 4. Equivalent bus voltage control block diagram.

Fig. 5
Fig. 5 shows the equivalent grid current control block diagram in the stationary reference frame.The LCL filter's transfer functions G LCL (s) and G FW (s) are given by

FIGURE 6 .
FIGURE 6. Grid current control with parallel HC scheme.

FIGURE 7 .
FIGURE 7. (a) Proposed grid current control with zero-reference HC scheme.(b) Equivalence of the grid current control with zero-reference HC scheme.

FIGURE 8 .
FIGURE 8. Stationary frame representation of the synchronous reference frame control.

FIGURE 9 .FIGURE 10 .
FIGURE 9. Unified structure of the unbalanced synchronous reference frame.

FIGURE 11 .
FIGURE 11.Unbalanced synchronous reference frame control with the reference in the α−axis.

FIGURE 12 .
FIGURE 12.Proposed DC bus voltage control system with unified current harmonic mitigation.

FIGURE 13 .
FIGURE 13.Harmonic controller G cih (s) in the unbalanced synchronous reference frame.

FIGURE 14 .
FIGURE 14. Conventional bus voltage control of the single-phase grid-connected VSC.

FIGURE 15 .
FIGURE 15.Notch filter-based bus voltage control of the single-phase grid-connected VSC.

FIGURE 16 .
FIGURE 16.Open-loop frequency response of the grid current control systems.

FIGURE 17 .
FIGURE 17. Equivalent bus voltage control block diagram and its open-loop frequency response.

FIGURE 18 .
FIGURE 18.Frequency response OF the grid current to the reference current G cl (jω) in(33).

FIGURE 19 .
FIGURE 19.Frequency response of the grid current to the deadtime voltage Y DT (jω) in (34) the grid voltage Y pcc (jω) in (35).

FIGURE 20 .FIGURE 21 .
FIGURE 20.Simulation results of the VSC in the rectifier mode supplying the bus power of 2 kW (v pcc (t): 100 V/division, i g (t): 10 A/division): (a) Sinusoidal PCC voltage, (b) Sinusoidal PCC with the dead-time voltages, (c) Distorted PCC voltage, (d) Distorted PCC with the dead-time voltages.

Fig. 21
Fig.20(d).On the other hand, the proposed control method with HC forces the grid current to be near sinusoidal with the simultaneous presence of the dead-time voltage and PCC harmonic voltage v h (t).Fig. 21 depicts the transient response of the proposed bus voltage control system under the distorted grid voltage and dead-time voltage v DT (t).The DC bus initially supplies a power of P D = 2 kW.Although there is a 2ω ripple component in the reference current i * d (t), the grid current i g (t) remains sinusoidal similar to that in Fig. 20.At t = 0.2 s, P D is removed, which behaves as a step load change.The bus voltage v D (t) increases by approximately 50 V and recovers to V * D =400 V within 50 ms.VII.EXPERIMENTAL VALIDATION A. EXPERIMENTAL SETUP Fig. 22 illustrates the experimental setup of this study.The VSC and DAB DC-DC converter assembled from Infineon FF50R12RT4 insulated-gate bipolar transistor (IGBT) modules with the control schemes implemented on a 32-bit TMS320F28379D microcontroller.Dead times of T DT = 1µs and T DT = 4µs in each VSC leg were adjusted on the

FIGURE 22 .
FIGURE 22. Experimental setup of the VSC.

FIGURE 23 .
FIGURE 23.Transient response of the VSC when the output power changing from 2 kW to zero under the distorted PCC voltage and T DT = 1 µs (v pcc (t) and v D (t): 100 V/division, i g (t) and i * d (t): 10 A/division).

Fig. 25
Fig. 25 compares the resultant harmonic components of the grid current under the sinusoidal PCC voltage with T DT =1 µs and T DT = 4 µs.The proposed bus voltage system effectively mitigates the grid current harmonics caused by the large dead time T DT =4 µs with THD i = 1.85% compared with THD i = 1.18% for the short dead

FIGURE 24 .
FIGURE 24.Steady state waveforms of the VSC with the output power of 2 kW under the sinusoidal PCC voltage and T DT =1 µs, (v g (t) and v D (t): 100 V/division, i g (t) and i * d (t): 10 A/division).

FIGURE 25 .
FIGURE 25.Harmonic components of the VSC current with the output power of 2 kW under the sinusoidal PCC voltage with T DT =1 µs, and T DT =4 µs).

FIGURE 26 .
FIGURE 26.Steady state waveforms of the VSC with the output power of 2 kW under the sinusoidal PCC voltage and T DT =1 µs, (v g (t) and v D (t): 100 V/division, i g (t) and i * d (t): 10 A/division).

FIGURE 27 .
FIGURE 27.Harmonic components of the VSC current with the output power of 2 kW under the distorted grid voltage with T DT =1 µs, and T DT =4 µs.

FIGURE 28 .
FIGURE 28.THD i values of the grid current with the output power under: (a) sinusoidal PCC voltage, and (b) distorted PCC voltage.

FIGURE 29 .
FIGURE 29.THD i values of the grid current under sinusoidal PCC voltage and T DT =1 µs at the output power of 2 kW with varied grid frequency.
are very close to those under the sinusoidal voltage in Fig.25, which confirms the effectiveness of theVOLUME 11, 2023

TABLE 1 .
Parameters of the VSC and DAB DC-DC converter.

TABLE 2 .
Harmonic rejection characteristics of the grid current control structures.
FIGURE 5. Equivalent grid current control block diagram in the stationary reference frame.
in Table2.The large gains of HC at the selected frequencies simultaneously attenuate the harmonic components in i * g (t), v DT (t), and v pcc (t).Furthermore, the parallel and zero-reference HC schemes 6456VOLUME 11, 2023 x α (t) and x β (t) are the controlled signals, and x αref (t) and x βref (t) are the reference signals in the αβ− axes.The error signals e α (t) and e β (t) are transformed to the error signals e d (t) and e q (t) in the synchronous reference frame using the Park transformation as e d (t) + je q

TABLE 3 .
Performance comparison of the proposed control schemes with the existing methods.