A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

A novel hardware digital architecture for the space vector pulsewidth modulation (SVPWM) technique is proposed and based on a novel algorithm for the evaluation of the dwell times. Indeed, the complexity of the calculation of trigonometric functions is solved by introducing a Taylor series decomposition and using a convenient definition of the space vector $\alpha -\beta $ plane. Our architecture can modify the dwell times as a function of the fundamental and switching frequencies, of the phase and of the modulation index. Compared to other techniques, it avoids the use of external reference voltages as well as of the precalculated dwell times, like for the LUT-based architectures. Although it can be implemented in several logic devices, an Altera Cyclone V field programmable gate array (FPGA) is used as a digital controller of a three-phase power inverters and its resources are 16% and 2%, respectively, of the look-up tables and of the flip flops. Several cases are studied in order to show the goodness of the output waveforms during the real-time variations of the inputs.

A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition Luigi Di Benedetto , Senior Member, IEEE, Andrea Donisi , Member, IEEE, Rosalba Liguori , Member, IEEE, Alfredo Rubino , Member, IEEE, and Gian Domenico Licciardo , Senior Member, IEEE Abstract-A novel hardware digital architecture for the space vector pulsewidth modulation (SVPWM) technique is proposed and based on a novel algorithm for the evaluation of the dwell times.Indeed, the complexity of the calculation of trigonometric functions is solved by introducing a Taylor series decomposition and using a convenient definition of the space vector α − β plane.Our architecture can modify the dwell times as a function of the fundamental and switching frequencies, of the phase and of the modulation index.Compared to other techniques, it avoids the use of external reference voltages as well as of the precalculated dwell times, like for the LUT-based architectures.Although it can be implemented in several logic devices, an Altera Cyclone V field programmable gate array (FPGA) is used as a digital controller of a three-phase power inverters and its resources are 16% and 2%, respectively, of the look-up tables and of the flip flops.Several cases are studied in order to show the goodness of the output waveforms during the real-time variations of the inputs.

I. INTRODUCTION
T HE recent increase in air pollution is leading the interna- tional academic and industrial research studies to improve the power electronics systems in terms of energy efficiency and power density.Several fields of applications can find interest from transportation [1], [2] to distributed generation [3].Although the new semiconductor technologies, like the wide bandgap semiconductor devices in Silicon Carbide [4], [5], [6] and in Gallium Nitride [7], [8], can help to achieve such goal, thanks to higher switching frequencies, power density, and efficiency than Silicon one, an increase of the complexity of the electronics power systems is also required.Indeed, in addition to the management of the energy conversion, the controllers of the modern power converters supervise the auxiliary and communication circuits or the activities of the single stages in the multistage converters [9].This complexity The authors are with the Department of Industrial Engineering, University of Salerno, Fisciano, 84084 Salerno, Italy (e-mail: ldibenedetto@unisa.it;adonisi@unisa.it;rliguori@unisa.it;arubino@unisa.it;gdlicciardo@unisa.it).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/JESTPE.2023.3349217.
In this scenario, the performance of the system is also related to the control strategy and, in particular, for threephase dc/ac power converters of Fig. 1(a), the space vector pulsewidth modulation (SVPWM), technique has a lower harmonic content and a higher dc bus utilization than other control techniques [17], but has a higher computational cost.Indeed, the calculation of trigonometrical function makes impracticable its implementation with analog circuits [18].However, there are several effort to implement SVPWM technique in FPGA controllers in order to simplify and to reduce the complexity of the algorithm, and there are solutions based on coordinate rotation digital computer (CORDIC), algorithms [19] or on Lookup table approaches [20], [21] and that can use DSPs [22] or external flash memory with an external signal reference [23].However, there are some drawbacks: first, in the case of the external PCs or DSPs, one needs powerful hardware that limits the fields of applications, like stand-alone applications because SVPMW signal generator requires external reference signals; second, although hardware architectures based on LUT reduce the complexity and do not require external resources, the variations of the three-phase output waveform are only possible for multiple values of the reference value [20], [21], [24].Moreover, FPGA manufacturers provide FPGA core Intellectual Property modules to implement SVPWM technique, but they cannot be modified in order to optimize the resource for specific applications as well as to improve the algorithm.
In this article, we propose a novel hardware architecture as well as a novel algorithm of the SVPWM technique.They are based on a linearization of the trigonometric functions through the Taylor series decomposition and on an optimized construction of the space vector in the α − β plane.The architecture has been implemented in an Altera Cyclone V and in an Xilinx Artix 7 FPGAs, where a fixed-point customized arithmetic logic unit (ALU), executes the calculations for the dwell times at each switching period with only multipliers, adders, and divisors and without DSP or external reference voltage.Indeed, we discretize the circumference of the space vector so that its rotation can be described through an integer number, easily implemented with an internal counter.Furthermore, the values of the fundamental, f C , and switching, f SW , frequencies, of the modulation index, m a , and of the phase can be changed without external reference signals and it is also possible to introduce a phase shift of the three-phase waveform as well as a variation of the rotation direction of the rotor, when the power converter drives an asynchronous motor.The possibility to change in real-time the three-phase output voltage parameters is useful both in an open-loop architecture, similar to Fig. 1(b), and in a closed-loop configuration, like in Fig. 1(c) where the controller evaluates m a and sends it to the input of our SVPWM block to generate the gate driver signals.
The article is organized as follows: in Section II the theory of the proposed algorithm is reported; in Section III its implementation in a hardware architecture based on an open-loop control scheme of Fig. 1(b); in Section IV the experimental results obtained from a three-phase power converter; finally, Section V the conclusions.

II. THEORY OF THE PROPOSED SVPWM
SVPWM technique controls the configurations and the turn-on and -off timings of the transistors for a three-phase power converter dc/ac of Fig. 1(a).The aim is to generate a three-phase sinusoidal output voltage with f C and amplitude, V M , which is related to the input dc voltage, V dc , through m a = 2V M /V dc .f SW depends on the power transistor characteristics as well as on the f C .The three-phase output voltages referred to neutral potential are as follows: and can be represented on the polar plane of Fig. 1(d) in terms of the vectors V α and V β through the following Clarke transformation [25]: The vector form of ( 2) is expressed in terms of the voltage reference vector, V REF , whose amplitude, V REF , and angle referred to the α-axis, θ , are The circle described by V REF is descretized in step angles of θ = 2π f C / f SW and its rotation speed and radius are, respectively, related to f C and V M of (1).
The vector representation on the polar plane is useful for the evaluation of the inverter configurations and for the calculation of the dwell times, T A , T B , and T 0 , when the power converter of Fig. 1(a) generates the three-phase output voltages of (1).Indeed, observing Fig. 1(d) the polar plane is divided into six sectors, S i , by six active vectors, V i , which represent the eight different configurations of the inverter together with the two null vectors (i.e., V 0 and V 7 ).It is worth to note that the digits in the round bracket of To describe the rotation of V REF and, hence, to modulate the three-phase output voltage with the power converter, the V REF is projected along the two vectors V i and V i+1 when it is in S i and the single switching period, T SW , is lower than the fundamental period, T C , i.e., f SW ≫ f C , one obtains at jth time-step where the dwell-time T 0 is equally divided between V 0 and V 7 .
Assuming that for each switching interval, θ and V REF are constant and that each S i covers π/3 of the circle, the dwell times can be calculated using the trigonometric projections along V i and V i+1 , as follows [26]: where S i is the ith sector and its value is from 1 to 6.

A. Proposed SVPWM Algorithm
The dwell times of ( 5) can be rewritten applying the following assumptions.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
Graphic representation of the proposed SVPWM algorithm for (a) 2) T A and T B values are symmetric respect to φ = π/6 in each S i .Resources are reduced being by reducing the number of bits of each variable.
3) The angle φ can be expressed as φ • j, where j is an integer from 0 to j MAX = f SW /(12 f C ). 4) S i defines the inverter configuration.5) T A , T B , and T 0 are multiplied by f CLK for the counting.Hence, (5a) and (5b) can be discretized as follows: and, applying the Taylor series up to the third order, we obtain where the coefficients are reported in Table I.The expansion up to third order is due to the narrow domain of the variable j ∈ [0; j MAX ], i.e., φ ∈ [0; π/6].From (7) the dwell times can be calculated by changing only the integer number j, which is implemented with a digital counter, and maintain their dependencies on f SW , f C , and m a .Once (7) are calculated, T 1 and T 2 are related to the effective dwell-times T A and T B of Fig. 1(d), as follows.
equivalently.The SUB 1 of ( 8) is the subsector defined for φ ∈ [0; π/6) and the SUB 2 of (9) the subsector defined for φ ∈ [π/6; π/3).In Fig. 3 the comparisons between the effective dwell-times evaluated from (5) and the proposed algorithm are reported for different f SW and m a values and for a f CLK = 50 MHz.In particular, Fig. 3(a) shows the effect of the m a , when it changes from 0.73 to 1.15, whereas Fig. 3(b) shows the variation of f SW from 100 to 1 kHz, whose clock counts is higher.In both cases, the theoretical and the proposed SVPWM dwell-time calculations give the same results.

III. HARDWARE ARCHITECTURE
In this section the proposed hardware architecture implements the SVPWM algorithm of Section II-A: it calculates the effective dwell-times through ( 7)-( 9), manages the counters and the inverter configurations, and generates the six signals for the gate drivers of the power transistors.Our architecture is generic and can be implemented in any digital controller and, as an example, in Section IV we report an example of FPGA application.The block diagram of the proposed architecture is shown in Fig. 4(a) and is based by three macro blocks: COUNTING, TIME CALCULATOR and INVERTER CONFIGURATOR.The five inputs are f C , f SW , m a , and θ * , which are related to the three-phase output voltage and can be changed in real-time for each T SW , and CNT θ , which is the input signal for the phase function (see Section III-A).Its outputs are the six signals for the gate drivers.The description of the control signals and the main procedure is reported in the flux diagram of Fig. 5.

A. Phase Input Function
In several applications, for example in field-oriented-control technique, the controller needs to instantaneously change θ Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.and, in our architecture, we can do it through the inputs θ * and CNT θ .The one-bit control signal, CNT θ , defines if the value of θ * refers to the position of the V REF in the α − β plane, i.e., position function and θ * = θ new , or refers to the shift respect the actual angle, i.e., Shift function and θ * = θ delay , which is delay respect to the actual phase.In terms of the HW architecture, the difference between the two phase variations is related to the updating of the counter j.
1) Position Function: When the angle changes, i.e., θ * = θ new , we can calculate the related sector, S * , and the related counter index, j θ * , as follows: 2) Shift Function: When a delay is desired, i.e., θ * = θ delay , first, we evaluate the relative number of counts. 1) 2) and, then, S * and j θ * are as follows: Once S * is evaluated from (10a) or (13a), the new sector, S θ , is calculated with the following relation: instead, starting from (10b) or (13b), we obtain the new counter index, j, as follows:

B. COUNTING Macro-Block
The COUNTING macro-block synchronizes the entire system and is composed of two finite state j-CALCULATOR and COUNTER, which communicate with ENABLE, DONE, HALF SECTOR signals and the least significative bit of the ACTUAL SECTOR signal.
1) j-CALCULATOR Block: As shown in Fig. 4(a), j-CALCULATOR block has three input signals and four output signals, and its task is the setting-up of the j variable.Indeed, when the COUNTER block sends the ENABLE signal, one of the following cases can occur.
1) φ ≤ (π/6): the value of j increases by 1 and HALF SECTOR is set to 0, i.e., V REF ∈ SUB 1 .2) (π/6) < φ ≤ (π/3): the value of j decreases by 1 and HALF SECTOR is set to 1, i.e., V REF ∈ SUB 2 .3) φ = (π/3): ACTUAL SECTOR increases by 1 and, if ACTUAL SECTOR = 6, it carries to 0, i.e., a complete round of the α − β plane is done.4) f C or f SW change: the values of j MAX and j are updated through j MAX and j n signals from ALU block.Once the new value of j is sent to ALU block, j-CALCULATOR sends the DONE signal.2) COUNTER Block: It has two output and ten input signals, whose seven are the sub dwell-times used in a single T SW .These last are obtained from the TIME DIVISOR block, as explained in Section III-C.This block controls the multiplexer with the MUX signal: indeed, it selects the configuration of the top transistors for each sub-interval [21].Fig. 6(a) and (b) report the temporal sequences of the gate signals for 5th and sixth sectors, respectively, for a single T SW and there are also shown the sequences of the sub-interval times for odd and even S i .

C. TIME CALCULATOR Macro-Block
The TIME CALCULATOR macro-block is composed by two blocks and its aim is the algebraic calculation of the dwell-times.The ALU block is a custom made fixed point 32-bit ALU and implements (7), whereas the TIME DIVISOR block performs the division of the dwell-times in the seven sub-intervals for the COUNTER block.
1) ALU Block: The internal structure of the ALU block is shown in Fig. 4(b), whose three output signals are the dwell-times evaluate from (7).A finite state machine CONTROLLER manages the sequence of operations by carrying out the multiplication, the division, and the addition through the multiplexer and by redirecting the relative results to the flip-flops and to the outputs.The aim of the flip-flops is to store the results of each 25 sequential steps, which are shown in Table II.Two different sequences are defined by the CONTROLLER through the signal CNT θ and they are the sequence refers to position and that to shift of the Phase input functions (see Section III-A).It is worth to note that the new values j θ and S θ are calculated only when a new value of θ is given.Moreover, our architecture performs an update of the defined f SW in order to have an integer number of the θ , which, equivalently, means an integer value of j MAX .This last is done between steps 1 and 4 of Table II, where the new switching frequency, f SWn , is calculated as follows: Finally, when one or both of f SW and of f C change their values, a scaling of the j must be done (see steps 11-12 and 24-25 of Table II), otherwise a discontinuity of the waveform is shown.Indeed, the ALU keeps the proportionality between the new and the old values of j and of j MAX as follows: It is worth note that, since sequences of Table II are in the last 25 clock T CLK , and the input signals vary this interval time, the dwell-times variation has a maximum delay of CLK + T SW .
2) TIME DIVISOR Block: This block divides the three dwell-times in the seven subintervals of the COUNTER block (see Fig. 6) as follows [20]: In Fig. 4(a) the DIV.sub-block, which performs (19), and the internal wiring of the TIME DIVISOR block are shown.It is worth noting that the division by 2 are carried out by a one bit right shift.

D. INVERTER CONFIGURATOR Macro-Block
The INVERTER CONFIGURATOR macroblock generates the six gate driver signals and it is composed by a SECTOR SELECT with a MULTIPLEXER and by the DEAD TIME and L/R blocks.
1) SECTOR SELECT and MULTIPLEXER Blocks: The SECTOR SELECT block is an LUT and contains the configurations of the inverter related to each sector, as reported in table of Fig. 1(d).Its input is the ACTUAL SECTOR signal from the j-CALCULATOR and selects the four configurations, C i , of the desired single sector.The four 3-bits outputs go to the MULTIPLEXER, which routes one of them to the output through MUX signal from COUNTER block.
2) DEAD TIME and L/R Blocks: The DEAD TIME block has three inputs, which are related to the top transistor gate signals, and generates the three couple of the gate outputs.In particular, each signal has a delay when a rising edge appears and it is configurable (in Section IV it is 500 ns).Before sending the three signals to the DEAD TIME block, the signals of the B and C legs of the inverter can be switched in order to impose either a clockwise or a counterclockwise direction of rotation for V REF [21].

IV. EXPERIMENTAL RESULTS
The proposed architecture has been implemented in an Altera Cyclone V 5CEBA4F17C17 FPGA [27] used to drive a three-phase power inverter composed by STMicroelectronics IGBT STGW40M120DF3, whose maximum f SW is 10 kHz, and with a dc-input voltage of V dc = 100 V and a 100 resistor load for each phase output    = θ delay of ( 11)-( 12).In Table III the hardware resources are reported for our implementation both in Altera Cyclon V [27] and in Xilinx Artix 7 [28], which has less resource.In both cases, DSPs are avoided and a 16% and 2% of the overall LUT and FF are, respectively, used for Cyclon V [27], whereas a 23% and 3.58% for Artix 7 [28].Moreover, Cyclon V [27] shows a dynamic power consumption of 4.7 mW, evaluated by PowerPlay Power Analyzer Tool from Altera, whereas Artix 7 [28] of 1.69 mW, evaluated with Xilinx Power Estimator.In Table III we report an equivalent comparison among different implementations of the ALU block using LUT-base architecture [21] and CORDIC-algorithms on the same FPGAs and with the same configurations.The architecture of [21], which is based on LUT-memory, has around twice that of LUT and less than half of FF, thanks to a lower number of operations compared to our proposal, but has a less resolution of f C , i.e., 1 Hz, and of f SW , because only integer multiple of f C and 2 −n multiple of f SW can be selected.The CORDIC is designed with a 14-bits for the decimal part of the angle (see φ = 2π 10 −5 = 0.0036), and two architectures are proposed: the CORDIC Cascade has 15 evaluation layers and calculates the dwell-times in 13 clock periods; instead, the CORDIC Iterative one has a single evaluation layer invoked for 16 clock interval times and in 29 clock periods the dwell-times are obtained.For Cyclon V [27], among all cases our proposal needs less number of LUTs, whereas a high number of FFs needs due to the partial results of our ALU, as reported in Fig. 4(b), which also justifies the few increasing of the dynamic power.Finally, in Table III we also reported comparisons from the state-of-art: if on one hand they need lower LUT and FF, on the other hand, [29] shows a higher dynamic power dissipation, [22] needs 11 DSPs, [30] require three BRAM (for a total of 54 kbit) and [31] outputs an overmodulated SVPWM.Although such differences can also depend on the implementation of the HW in the particular FPGA, they need an external controller, i.e., PC or microcontroller, that generates external three-phase reference signals to define f C , m a , and θ, limiting their applications in stand-alone systems.

V. CONCLUSION
In this article, we show a novel hardware architecture for the generation of the gate drive signals of three-phase inverters through SVPWM technique and is based on the Taylor series decomposition of the dwell-times.The variation of inputs is useful in real-time digital controls, for example in closed-loop system for the asynchronous motor.Moreover, the proposed architecture can be also implemented in micro-controllers as well as in integrated circuits, making it attractive for System-On-Chip products.Limitations are the maximum f SW,max ≤ f CLK /25 and the minimum required resources, that depend on the resolution of the dwell-times and on the minimum number of bits of a 4 , due to f C,min and f SW,max .

Fig. 1 .
Fig. 1.(a) Three-phase power converter basic schematic.SVPWM block in (b) open-loop and (c) closed-loop configurations.(d) Polar plane and vector representation of the three-phase voltages based on the SVPWM technique, where the round brackets are the configurations of top transistor of (a).

Fig. 1 (
d) are the state condition of the top gate signals of Fig. 1(a), for example V 6 = (101) means that G A+ and G C+ are high and G B+ is low, whereas the bottom gate signals are inverted, i.e., (G A− , G B− , G C− ) ≡ (010).

Fig. 3 .
Fig. 3. Comparisons of the dwell-time counts for a f CLK = 50 MHz calculated through (5) and the proposed algorithm.(a) f SW = 100 kHz, m a = 0.73 and 1.15 and (b) f SW = 1 kHz, m a = 0.73.Continuous lines are from the proposed model, dashed lines are from (6).

Fig. 5 .
Fig. 5. Flux diagram of the main process steps of the proposed architecture.The colors are related to those of Fig. 4(a).

Fig. 6 .
Fig. 6.Gate signals sequence for a single T SW for (a) odd and (b) even sectors.
. The architecture is designed to have f C ∈ [1, 512] Hz with an incremental step of 0.125 Hz, f SW ∈ [1, 100] kHz with an incremental step of 1 Hz, φ = 2π 10 −5 = 3.6 • 10 −3 , θ ∈ [0 • , 360 • ] with a step of 1 • , m a ∈ [0, 1.06] with a step of 0.01, and f CLK = 50 MHz.In Fig. 7 the phase and line output voltages of the power inverter are shown for a f C = 50 Hz and a m a = 0.5 and the typical SVPWM third-harmonics injection in the phase Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Fig. 8 .
Fig. 8. (a) Experimental waveforms of the gate driver signal for the top transistors for a variation of f SW from 100 to 25 kHz.(b) Experimental waveforms of G A+ and G A− show a dead-time of 500 ns.m a = 1, f CLK = 50 MHz.

Fig. 9 .
Fig. 9. Experimental voltage waveforms with (a) instantaneous variation of f C = [50, 1, 10] Hz and (b) continuous variation of f C from 1 to 50 Hz and a proportional m a = 0.02 • f C in an interval time of 4 s.Set-up is f SW = 10 kHz, f CLK = 50 MHz, V dc = 100 V. (c) Phase voltages and current of the phase-A during load variations between 50 and 100 with f C = 10 Hz, f SW = 10 kHz, f CLK = 50 MHz, and V dc = 70 V.

TABLE II ALU
SEQUENCE OF OPERATIONS FOR THE CALCULATION OF THE DWELL-TIMES

TABLE III COMPARISONS
OF THE SYNTHESIS WITH THE STATE-OF-ART